Lattice Semiconductor ECP5-5G Manuals

Manuals and User Guides for Lattice Semiconductor ECP5-5G. We have 4 Lattice Semiconductor ECP5-5G manuals available for free PDF download: Technical Note, Technical Notes, Usage Manual, User Manual

Lattice Semiconductor ECP5-5G Technical Note (86 pages)

High-Speed I/O Interface

Brand: Lattice Semiconductor | Category: Recording Equipment | Size: 3.15 MB

Table of Contents
3
Acronyms in this Document
9
1 Introduction

10
2 External Interface Description

10
- Figure 2.1. External Interface Definitions
  10
3 High-Speed I/O Interface Building Blocks

11
- Edge Clocks
  11
- Primary Clocks
  11
- DQS Lane
  11
- Figure 3.1. ECP5 and ECP5-5G Device Clocking Diagram
  11
- Pll
  12
- Ddrdll
  12
- Dqsbuf
  12
- Figure 3.2. DDRDLL Connectivity
  12
- Dlldel
  13
- Input DDR (IDDR)
  13
- Output DDR (ODDR)
  13
- Edge Clock Dividers (CLKDIV)
  13
- Input/Output DELAY
  13
4 Building Generic High Speed Interfaces

14
- Types of High-Speed DDR Interfaces
  14
- Table 4.1. Generic High-Speed I/O DDR Interfaces
  14
5 High-Speed DDR Interface Details

15
6 ECP5 and ECP5-5G Memory Interfaces

31
- Figure 6.1. Typical DDR2/DDR3/DDR3L Memory Interface
  31
7 Using Clarity Designer to Build and Plan High Speed DDR Interfaces

49
- Figure 7.1. Clarity Design Main Window
  49
8 DDR Software Primitives and Attributes

64
- Input/Output DELAY
  64
- Table 8.1. Software Primitives
  64
- Delayf
  65
- Delayg
  65
- Figure 8.1. DELAYF Primitive
  65
- Figure 8.2. DELAYG Primitive
  65
- Table 8.2. DELAYF Port List
  65
- Table 8.3. DELAYG Port List
  65
- DELAY Attribute Description
  66
- DDRDLL (Master DLL)
  66
- DLL Delay (DLLDEL)
  67
- Figure 8.4. DLLDELD Primitive
  67
- Table 8.5. DDRDLLA Port List
  67
- Table 8.6. DDRDLL Attributes
  67
- Table 8.7. DLLDELD Port List
  67
- Generic DDR Input and Output Primitives
  68
- Input DDR Primitives
  68
  - Iddrx1F
    68
  - Figure 8.5. IDDDRX1F Primitive
    68
  - Table 8.8. DLLDELD Attributes
    68
  - Table 8.9. IDDRX1F Port List
    68
  - Iddrx2F
    69
  - Iddr71B
    69
  - Figure 8.6. IDDRX2F Primitive
    69
  - Figure 8.7. IDDR71B
    69
  - Table 8.10. IDDRX2F Port List
    69
  - Table 8.11. IDDRX2F Port List
    69
- Output DDR Primitives
  70
  - Oddrx1F
    70
  - Oddrx2F
    70
  - Figure 8.8. ODDRX1F
    70
  - Figure 8.9. ODDRX2F
    70
  - Table 8.12. ODDRX1F Port List
    70
  - Table 8.13. ODDRX2F Port List
    70
  - Oddr71B
    71
- Memory DDR Primitives
  71
  - DQSBUF (DQS Strobe Control Block)
    71
  - Figure 8.10. ODDR71B Primitive
    71
  - Table 8.14. ODDR71B Port List
    71
  - Dqsbufm
    72
  - Figure 8.11. DQSBUFM Primitive
    72
  - Table 8.15. DQSBUF Port List
    72
- Input and Output Memory DDR Primitives
  73
- Table 8.16. DQSBUFM Attributes
  73
- Table 8.17. Summary of All DDR Memory Primitives
  73
- Memory Input DDR Primitives
  74
- Memory Output DDR Primitives for DQ Output
  75
  - Oddrx2Dqa
    75
- Memory Output DDR Primitives for DQS Output
  75
  - Oddrx2Dqsb
    75
  - Figure 8.13. ODDRX2DQA
    75
  - Figure 8.14. ODDRX2DQSB Primitive
    75
  - Table 8.20. ODDRX2DQA Port List
    75
- Memory Output DDR Primitives for Tristate Output Control
  76
  - Tshx2Dqa
    76
  - Tshx2Dqsa
    76
  - Figure 8.15. TSHX2DQA Primitive
    76
  - Figure 8.16. TSHX2DQSA Primitive
    76
  - Table 8.21. ODDRX2DQA Port List
    76
  - Table 8.22. TSHX2DQA Port List
    76
- Memory Output DDR Primitives for Address and Command
  77
  - Oshx2A
    77
  - Figure 8.17. OSHX2A Primitive
    77
  - Table 8.23. TSHX2DQSA Port List
    77
  - Table 8.24. OSHX2A Port List
    77
9 Soft IP Modules

78
- Detailed Description of each Soft IP
  78
  - Gddr_Sync
    78
  - Figure 9.1. GDDR_SYNC Ports
    78
  - Table 9.1. List of Soft Ips Supported
    78
  - Table 9.2. Soft IP Used in each Interface
    78
  - Rx_Sync
    79
  - Figure 9.2. RX_SYNC Ports
    79
  - Table 9.3. GDDR_SYNC Port List Description
    79
  - Table 9.4. GDDR_SYNC Port List Description
    79
  - Mem_Sync
    80
  - Bw_Align
    80
  - Figure 9.3. MEM_SYNC Ports
    80
  - Figure 9.4. BW_ALIGN Ports
    80
  - Table 9.5. MEM_SYNC Port Description
    80
  - Mipi_Filter
    81
  - Figure 9.5. MIPI_FILTER Ports
    81
  - Table 9.6. BW_ALIGN Port Description
    81
  - Table 9.7. MIPI_FILTER Port Description
    82
- Technical Support Assistance
  83
- Revision History
  84

Lattice Semiconductor ECP5-5G Technical Notes (78 pages)

High-Speed I/O Interface

Brand: Lattice Semiconductor | Category: Recording Equipment | Size: 8.59 MB

Lattice Semiconductor ECP5-5G User Manual (33 pages)

Brand: Lattice Semiconductor | Category: Motherboard | Size: 3.41 MB

ECP5-5G Device
3
Applying Power to the Board
3
Programming/Fpga Configuration
4
Alternate Programmer Download Interface
4
Diamond Programmer Requirements
4
Setting the Configuration Mode
5
Board Programming
5
PROGRAMN and GSRN
7
Programming Serial SPI Flash Memory
7
On-Board Clock Capabilities
9
General Purpose Clock Source
10
FPGA Test Pins
11
General Purpose DIP Switches
11
General Purpose Leds
12
Alpha-Numeric LED Display
12
DDR3 Memory Device
13
Ethernet Interfaces
15
Ordering Information
17
Technical Support Assistance
17
Revision History
17
Appendix A. Schematics
18
Appendix B. Bill of Materials
28

Lattice Semiconductor ECP5-5G Usage Manual (43 pages)

Brand: Lattice Semiconductor | Category: Computer Hardware | Size: 4.95 MB

Lattice Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Controller Recording Equipment

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Lattice Semiconductor ECP5-5G Manuals

Lattice Semiconductor ECP5-5G Technical Note (86 pages)

Table of Contents

1 Introduction

2 External Interface Description

3 High-Speed I/O Interface Building Blocks

4 Building Generic High Speed Interfaces

5 High-Speed DDR Interface Details

6 ECP5 and ECP5-5G Memory Interfaces

7 Using Clarity Designer to Build and Plan High Speed DDR Interfaces

8 DDR Software Primitives and Attributes

9 Soft IP Modules

Lattice Semiconductor ECP5-5G Technical Notes (78 pages)

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Lattice Semiconductor ECP5-5G User Manual (33 pages)

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Lattice Semiconductor ECP5-5G Usage Manual (43 pages)

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