The cylinder number may be from zero to the number of cylinders minus one.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15,
and the "previous content" contains Bits 32-39.
7.5 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the
register through which sector information is transferred on a Format Track command, and configuration
information is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are
PIO only.
The register contains valid data only when DRQ=1 in the Status Register.
7.6 Device Control Register
7
HOB
Table 41 Device Control Register
Bit Definitions
HOB
SRST (RST)
-IEN
7.7 Drive Address Register
7
HIZ
-WTG
Table 42 Drive Address Register
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ
-WTG
HITACHI Deskstar & CinemaStar P7K500 Hard Disk Drive specification (Rev 1.1)
Device Control Register
6
5
4
-
-
-
HOB (high order byte) is defined by the 48-bit Address feature set. A write to
any Command Register shall clear the HOB bit to zero.
Software Reset. The device is held reset when RST=1. Setting RST=0
reenables the device.
The host must set RST=1 and wait for at least 5 microseconds before setting
RST=0, to ensure that the device recognizes the reset.
Interrupt Enable. When -IEN=0, and the device is selected, device interrupts to
the host will be enabled. When -IEN=1, or the device is not selected, device
interrupts to the host will be disabled.
Drive Address Register
6
5
4
-H3
-H2
High Impedance. This bit is not driven and will always be in a high impedance state.
-Write Gate. This bit is 0 when writing to the disk device is in progress.
3
2
1
1
SRST
-IEN
3
2
-H1
-H0
-DS1
60
0
0
1
0
-DS0