ABB FSK II S + Operating And Maintenance Manual page 19

6.2.5. Binary Signal Outputs
The used binary inputs can differ from project to project. Please refer to the valid wiring diagram.
Designation Description
S1 CB Open
S2 CB Close
S3 Aux. CB Open
S4 Aux. CB Close
S5 Unit Ready
S6 WD Ready
S7 Undervoltage detection
Table 5 Signal Outputs
Observation
This output is a copy of the "OPEN" position as determined by the sensor
In the event of an error, the CPU activates the watchdog alarm
This output is a copy of the "CLOSE" position as determined by the sensor
In the event of an error, the CPU activates the watchdog alarm.
This output is a copy of the "OPEN" position as determined by the sensor
This output is a copy of the "CLOSE" position as determined by the sensor
Standby indicator for:
• Correct capacitor charge
•
Coil continuity
•
Valid and coherent position indication
• <10 faulty switching attempts
Self-monitoring signal of CPU – readiness
Closed when:
• WD in NOT READY = CPU is not working properly or MABS not supplied
Open when:
•
MABS is supplied AND CPU is working
Display of the input Y7 with 100 ms response delay
Closed when:
• Under voltage is low (active) = voltage failure
Open when:
•
Under voltage is high = voltage correct
19/36