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IC BLOCK DIAGRAM & DESCRIPTION
IC101BU4066BCF(ANALOG SW)(DVD)
V
C1
C4 I/O4
DD
14
13
12
2
3
1
I/O1 O/I1 O/I2 I/O2
IC550 LE28C1001ATS(Flash Memory)
X-
A16~A0
10~20
Address
Decoder
Buffers
&
Latches
CE
30
OE
32
Control Logic
7
WE
A11
1
A9
2
A8
3
A13
4
A14
5
NC
6
WE
7
32 Pin TSOP Normal
Vcc
8
NC
9
A16
10
A15
11
A12
12
A7
13
A6
14
A5
15
A4
16
IC806,807 EM636165TS-8(SDRAM)
V
1
DD
DQ0
2
DQ1
3
V
4
SSQ
DQ2
5
DQ3
6
V
7
DDQ
DQ4
8
DQ5
9
V
10
SSQ
DQ6
11
DQ7
12
V
13
DDQ
LDQM
14
WE#
15
CAS#
16
PAS#
17
CS#
18
A11
19
A10
20
A0
21
A1
22
A2
23
A3
24
V
25
DD
O/I4 O/I3
I/O3
11
10
9
8
4
5
6
7
C2
C3
V
SS
1,048,576 bit
Super Flash
Pin Name
EEPROM
Cell Array
A16-A0
Address Inputs
DQ7-DQ0
Data Input/Output
CE
Chip Enable
OE
Output Enable
Y-Decoder
WE
Write Enable
Vcc
Power Supply
Vss
Ground
I/O Buffers &
Data Latches
NC
No Connection
29~25,23~21
DQ7~DQ0
32
31
30
29
28
27
26
25
(Top View)
24
23
22
21
20
19
18
17
V
50
SS
DQ15
49
DQ14
48
V
47
SSQ
DQ13
46
DQ12
45
V
44
DDQ
DQ11
43
DQ10
42
V
41
SSQ
DQ9
40
DQ8
39
V
38
DDQ
NC
37
UDQM
36
CLK
35
CKE
34
NC
33
A9
32
A8
31
A7
30
A6
29
A5
28
A4
27
V
26
SS
IC900 BA033FP(REGULATER)
IC804,805 74LCX373MTC(Low Voltage Octal
Logic Diagram
D
0
3
D
O
G
CP
11
OE
1
OE
A10
CE
DQ7
Pin Descriptions
DQ6
Pin Names
DQ5
DQ4
D
-D
0
DQ3
LE
Vss
DQ2
OE
DQ1
O
-O
0
DQ0
A0
A1
A2
A3
IC481 KIA78R05PI(Voltage Regulator)
- 55 -
1
2
3
GND
V
OUT
CC
Transparent Latch)
D
D
D
D
D
1
2
3
4
4
7
8
13
14
D
D
D
D
O
O
O
O
G
G
G
G
2
5
6
9
O
O
O
O
O
0
1
2
3
Description
Data Inputs
7
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
7
D
D
5
6
7
17
18
D
D
D
O
O
O
G
G
G
12
15
16
19
O
O
O
4
5
6
7
Truth Table
Inputs
Outputs
LE
OE
Dn
On
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
H = HIGH Voltege Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
= Previous O
before HIGH-to-LOW
0
0
transition of Latch Enable
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