System Control Block Diagram (Vhs) - JVC SR-VS30U Service Manual

4.33

SYSTEM CONTROL BLOCK DIAGRAM (VHS)

0
CN3003
CAP MDA
CAP REV ( L )
6
M
CAP CTL V
3
CAP FG
2
WF1
CON1 CN3001
DRUM CTL V
DRUM MOTOR
3 3
D.PG
4 4
D.FG
5 5
M
5 5 LOADING MOTOR
CN3002
LDM2
M 2
LDM1
1
ROT AR Y
CN3004
ENCODER
LSB
1
LSC 2
LSA 3
1 2
A/C HEAD
A/C HEAD CN2001
CN1
CTL HEAD ( - )
2 6
CTL
CTL HEAD ( + )
1 7
8 5 JOG 2 8 SW/DISPLAY(FRONT)
FW7003
FW7004
1
1
2
2
JOG/SHUTTLE
UNIT
4
4
IC7001
(FLD CTL)
9
AN2
10 AN1
OPE 11
AN0
2 7 POWER SW
DATA
1 1
3 3
FW7002 FW7001
Note : For the waveforms in this block diagram, refer to page 4-54.
MAIN ( VHS SYSCON, CONNECTION )
3
WF2
WF3 PC3001 PHOTO SENSOR
PC3002
PHOTO SENSOR
Q3002 START SENSOR
IC3004
( LOADING MOTOR
Q3003
END SENSOR
VOLTAGE CONTROL )
2 9
LDM2 LMC1
4 7
LDM1 LMC2
1
DRIVE VOL T AGE
Vref
CONTROL
Q3001
WF4
IC3002
TP3905
( RESET )
D3004
2 1
AL5.8V RESET
3
Vcc
CN7001 CN3011
JSA/SHUTTLE A
20 20
JSB/SHUTTLE B
19 19
13 S.DATA FRSYS
Sin 4
4
14 S.DATA TOSYS
Sout 3
3
15 S.CLK
SCLK 2 2
PAUSE
10 10
J7195
TO OSD
REMOTE
S.DATA FRSYS
PAUSE
S.CLK
3
2 SYNC_DET(H)
1 OSD_CS
DI7001
IC3001
( SYSTEM CONTROL MICRO PROCESSOR )
77
VHS_DUB(H)
28
CAP REV ( L )
101
CAPPWM
8
CFG
TP3910
96
EXP2_DATA
102
DRUMPWM
107 11
DPG
NORM/MESEC/S
108 93
DFG FAN_CTL(H)/MESECAM(H)
54 65
SP FG
X1
55
TU FG
64
14
X2
START SENSOR
69
15
OSC2 ( OUT )
END SENSOR
67
OSC1 ( IN )
35
LMC1
36
LMC2
33
EXP1_DATA
37 79
EXP_CLK
LMC3
46
RXD/KBUS_IN
47
TXD/KBUS_OUT
56
DIAL_OFF[H]/KBUS_REQ
57
26 DV_HOUSING_SW/HDD_RESET
LSB
27
LSC
25
LSA
TP4001
44
ANT_CTL(H)/RMO
CTL.P
106
P_MUTE(L)
6
110
CTLAMPOUT V.PULSE
105
SP(H)
87
FLY_ON(H)
3
CTL ( - )
58
N_REC_ST(H)
1
CTL ( + ) 88
H_REC_ST(H)
49
I2C_DATA_A/V
WF5 50
I2C_CLK_A/V
100
V.FF
66
99
A.FF
RES
22
A.ENV/ND(L)
TP3904 98
C. SYNC
WF6
71
MODE 61
TU_DATA
TP3903
60
TU_CLK
62
FWE
97
17
JSA/STLA S_CASS(H)
94
JSB/STLB
41
52 REC_SAFETY
S.DATA_FRSYS
51
S.DATA_TOSYS
76
53
S.CLK I2C_DATA2
78 75
PAUSE I2C_CLK2
18
SYNC_DET(H)
91
OSD_CS
4-59 4-60
IC3651
( AUDIO CTL )
6
INSEL_A
7
INSEL_B
8
OUTSEL_A
9
OUTSEL_B
10
FULL_E_ON(L)
2
4
DATA2
N.REC(L)
3
CLK
X3001
TIMER CLOCK
IC3601
(32KHz)
( VIDEO/TUNER/REG CTL )
Q7501 SW
13
X3002
D_OUT(L)
MAIN SYSTEM
5
SP_CONV(H)
14
CLOCK
P.CTL(H)
EE(L) 4
(10MHz) 10
P.SAVE(L)
6
TP3911
FLY_REC(L)
8
VHS(H)
2
DATA2
3
CLK
AL5V
Q3010,Q3011
SW
ONLY USED FOR HR-DVS3U/SR-VS30U
AL5V
S3002
S.CASS
S3001
REC_SAFETY
5 IC3003
SDA
( SERIAL MEMORY )
6
SCL
VHS_DUB(H)
INSEL_A TO
INSEL_B AUDIO I/O
OUTSEL_A
OUTSEL_B
TO
FULL_E_ON(L)
VIDEO/AUDIO
N.REC ( L )
NORM/MESEC/S
CN7509
TO
FAN_CTL(H)
1
REG
2 P.SAVE(L)
CN5321
3 P.CTL(H)
OSD_P.CTL(L)
TO
D_OUT(L)
VIDEO I/O
SP_CONV(H)
EE(L)
TO
CN3014
DV MAIN (DV MSD)
RXD
1
CN1503
2 TXD
DIAL_OFF(H)/KBUS_REQ
3
4 DV_H.SW
EE(L)
FLY_REC(L)
VHS(H)
C.BOX/SAT_CTL
P.MUTE(L)
V.PULSE
SP(H)
TO
FLY_ON(H)
VIDEO/AUDIO
N.REC_ST(H)
H.REC_ST(H)
I2C_DATA_A/V
I2C_CLK_A/V
D.FF
A.FF
A.ENV/ND(L)
C.SYNC/VREF
TO
TU_DATA
TUNER
TU_CLK
TO
I2C_DATA2
TUNER
I2C_CLK2