Description Of Major Ics - JVC UX-A52 Service Manual

UX-A52

Description of major ICs

UPD784216AGF (IC701) : System micon
1. Pin layout
1
25
2. Block diagram
INTP2/NMI
PROGRAMMABLE
INTP0.INTP1.
INTP3-INTP6
CONTROLLER
TI00
TIMER/EVENT
TI01
TO0
TI1
TO1
TIMER/EVENT
TI2
TO2
TIMER/EVENT
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
WATCH TIMER
WATCHDOG TIMER
RTP0-RTP7
OUTPUT PORT
ANO0
ANO1
AV
REF1
AV
SS
ANI0-ANI7
AV
REF0
AV
D0
AV
SS
P03/INTP3
CLOCK OUTPUT
PCL
BUZZER OUTPUT
BUZ
1-30
100 76
75
51
26 50
INTERRUPT
COUNTER
(16BITS)
TIMER/EVENT
COUNTER1
(8BITS)
COUNTER2
(8BITS)
COUNTER5
(8BITS)
TIMER/EVENT
78K/1V
COUNTER6
CPU CORE
(8BITS)
TIMER/EVENT
COUNTER7
(8BITS)
TIMER/EVENT
COUNTER8
(8BITS)
RAM
8192BITS
REAL-TIME
D/A
CONVERTER
A/D
CONVERTER
CONTROL
UART/IOE1
BAUD-RATE
GENERATOR
UART/IOE2
BAUD-RATE
GENERATOR
CLOCKED
SERIAL
INTERFACE
BUS I/F
ROM
128K BITS
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT12
PORT13
SYSTEM CONTROL
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0
SO0
SCK0
AD0-AD7
A0-A7
A8-A15
A16-A19
RD
WR
WAIT
ASTB
P00-P06
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P80-P87
P90-P95
P100-P103
P120-P127
P130.P131
RESET
X1
X2
XT1
XT2
V
DD
V
SS
TEST