Panasonic FP7 User Manual page 22

Operation
E x a m p l e
Time chart of D/A conversion
22
 Conversion processing is enabled for 4 channels:
Order of conversion: channel 0channel 1channel 2channel
3channel 0channel 1channel 2channel 3....
1 cycle = 4 channels  25μs = 100μs
 Conversion processing is enabled for 2 channels:
Order of conversion: channel 0channel 1channel 0channel 1...
1 cycle = 2 channels  25μs = 50μs (The conversion time for the disa-
bled channels 2 and 3 is saved.)
The digital input values are written to the CPU's output area at the CPU's
I/O refresh time. D/A conversion in the analog unit and the CPU's pro-
cessing cycles are not synchronized. Therefore, the latest digital input val-
ue from the CPU will only be processed by the analog unit after D/A con-
version has been completed.
Q Digital input value, channel 0 of CPU
W CPU processing cycles
E I/O refresh
R Conversion processing
T Analog signal, channel 0 of analog output unit
FP7 Analog Output Unit User's Manual