Pinout And Package Definitions; Pin Definitions For The C8051F340/1/2/3/4/5/6/7/8/9/A/B - JBL MS-8 Service Manual

MS-8
4.

Pinout and Package Definitions

Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B
Name
V
DD
GND
RST/
C2CK
C2D
P3.0 /
C2D
REGIN
VBUS
D+
D-
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
C8051F340/1/2/3/4/5/6/7/8/9/A/B
Pin Numbers
Type
48-pin 32-pin
10 6 Power In
Power
Out
7 3
13 9 D I/O
D I/O
14 — D I/O
— 10 D I/O
D I/O
11 7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
12 8 D In
8 4 D I/O
9 5 D I/O
6 2 D I/O or
A In
5 1 D I/O or
A In
4 32 D I/O or
A In
3 31 D I/O or
A In
2 30 D I/O or
A In
1 29 D I/O or
A In
48 28 D I/O or
A In
47 27 D I/O or
A In
Description
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See
Ground.
Device Reset. Open-drain output of internal POR or V
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See
Clock signal for the C2 Debug Interface.
Bi-directional data signal for the C2 Debug Interface.
Port 3.0. See Section 15
3.
Bi-directional data signal for the C2 Debug Interface.
age regulator.
VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
USB D+.
USB D–.
Port 0.0. See Section 15
0.
Port 0.1.
Port 0.2.
Port 0.3.
Port 0.4.
Port 0.5.
Port 0.6.
Port 0.7.
51
Section 8.
Section
for a complete description of Port
for a complete description of Port
DD
11.