GE CM6 Hardware Reference Manual page 47

CPLD Registers
GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
One device connected at the LBC is the CPLD (U1949) which provides seven
CM6 specific control and status registers. The CPLD register are connected to
the Local Bus Controller at chip select LCS1 with 8-bit data width. The bit
description is in little endian, least significant bit is at the right and most
significant bit at the left end of the byte.
Reset Source Register (RSR)
Address: Base + Offset 0
Size: 8 bit
Table 9: Reset Source Register (RSR)
Bit Name
0 R_PWR
1 R_THERM
2 R_PCI
3 reserved
4 R_HRSTREQ
5 R_COPRST
6 R_WDGRST
7 PWR_ON
* Any write to the Reset Source Register clears all bits of this register.
After a power-on cycle all bits of this reset register should be cleared. If
afterwards there is an unexpected (or expected) reset the source can be
determined by the bits which are set.
Write Read
any write clears 1: last reset caused by
the bit * voltage monitor
any write clears 1: last reset caused by
the bit * power down of the thermal
protection
any write clears 1: 1ast reset caused by
the bit * Reset button, cPCI Reset
(non System only) or
RESETOUT# from PMC
- 0
any write clears 1: last reset caused by CPU
the bit * reset request
Must be cleared before a
CPU reset request is
performed
any write clears 1: last reset caused by COP
the bit * Interface HRESET or
SRESET
any write clears 1: last reset caused
the bit * watchdog circuit
any write clears 0 – warm reset
the bit * 1 – cold reset (power-on)
Default
not
defined
not
defined
not
defined
n/a
not
defined
not
defined
not
defined
1 – after
power
on reset
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