Clock Domains; Table 2. Clock Domains On Tms570Ls Microcontrollers - Texas Instruments TMS570LS Getting Started

3.9

Clock Domains

There are multiple clock domains on the TMS570LS microcontrollers to ease the configuration
and controllability of the different modules using these clock domains.
Table 2.
Domain Name
CPU clock domain
System bus clock domain
System peripheral clock
domain
Peripheral clock domains
Asynchronous clock domains
Real-Time Interrupt clock
domains
Clock Domains on TMS570LS Microcontrollers
Clock Name
GCLK
HCLK
VCLK_sys
VCLK and VCLK2
VCLKA1 and VCLKA2
RTI1CLK
Overwrite this text with the Lit. Number
Comments
GCLK controls all the CPU sub-systems, including
the floating point unit (FPU), and the memory
protection unit (MPU)
HCLK shares the same clock source as GCLK, and
is always the same frequency as HCLK.
VCLK_sys is used for the system modules such as
VIM, ESM, SYS, etc. VCLK_sys is divided down
from HCLK by a programmable divider from 1 to 16.
VCLK is the primary peripheral clock, and is
synchronous with VCLK_sys.
VCLK2 is a secondary peripheral clock and is
reserved for use by the enhanced timer module
(NHET) and the associated transfer unit (HTU).
VCLK2 is also divided down from HCLK by a
programmable divider from 1 to 16.
f must be an integer multiple of f
HCLK
f must be an integer multiple of f
VCLK2
These clock domains are reserved for use by
special communication modules that have strict jitter
constraints. The protocols for these communication
modules (e.g. CAN, FlexRay) do not allow
modulated clocks to be used for the baud rate
generation. The asynchronous clocks allow the
clock sources for the baud clocks to be decoupled
from the GCLK, HCLK and VCLKx clock domains.
This clock is used for generating the periodic
interrupts by the RTI module.
Getting Started With TMS570LS Microcontrollers
,
VCLK2
.
VCLK
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