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MPS MP5515 User Manual

High-efficiency bidirectional, power back-up manager
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DESCRIPTION
The MP5515 is an input power conditioning
PMIC targeting enterprise solid-state drives,
NVDIMM, and other applications with back-up
system requirements. The MP5515 consists of
input current limiting, input reverse current
blocking, and an MPS-patented, high-efficiency,
bidirectional, boost-buck converter with only
one inductor for energy storage and system
back-up power when there is an input power
failure. The MP5515 also provides I
and ADC. By using the I
input current limit, slew rate, and perform cap
health tests. The MP5515 can also monitor
system status, such as input voltage, input
current, storage voltage, temperature, and
provide interrupt options for these features.
The internal input current-limit block prevents
inrush current during system start-up while the
reverse-current block prevents backup energy
from flowing to the failing VIN port. MPS's
patented
energy
management control circuit minimizes the
storage capacitor requirement. It pumps the
input voltage to a higher backup voltage and
releases the energy over a hold-up time to the
system bus voltage in case of an input outage.
The MP5515 requires a minimal number of
standard, external components and is available
in a 30-pin QFN (5mmx5mm) package.
TYPICAL APPLICATION
C2
22µF
R3
105kΩ
VB
FBB
R4
12.4k
Ω
VIN
12V
VIN
R1
C1
DET
100kΩ
D1
0.1µF
EN
TVS
R2
optional
11kΩ
R9
SAS
for spike
200kΩ
OVP
R10
TPOR
11kΩ
DVDT
ICH
TEMP
VCC
C3
1µF
MP5515 Rev. 1.02
1/18/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
2
C interface
2
C, users can set the
storage
and
release
C6
10nF
C5
1µF
BST
CST
SW
L1
10µH
VBO
R8
RTEST
STRG
5.1kΩ
30V
MP5515
STRG
R5
365kΩ
FBS
R6
SDA
10kΩ
SCL
PGS
PGB
PFI
INT
ILIM
AGND
PGND
R7
12kΩ
www.MonolithicPower.com
© 2018 MPS. All Rights Reserved.
Wide Input 2.7 - 18V, 5A, High-Efficiency
Bidirectional, Power Back-Up Manager
with Integrated Hot-Swap, I
FEATURES
Wide 2.7V-to-18V Operating Input Range
Up to 32V Programmable Storage Voltage
Up to 6A Programmable Input Current Limit
5A Buck Load Capability
Adjustable Slew Rate for VB Voltage Rising
Input Current Limiter with Integrated 14mΩ
MOSFET
Input Over-Voltage Protection (OVP)
Reverse-Current Protection (RCP)
Input Power Failure Indicator
Backup Capacitor Health Test
Comprehensive Voltage, Current,
Temperature Sensor ADC Conversion
Thermal Protection
Available in a QFN-30 (5mmx5mm)
Package
APPLICATIONS
Solid-State Drives (SSD)
NVDIMMs
Hard-Disk Drives
Power Back-Up Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
"MPS" and "The Future of Analog IC Technology" are registered trademarks of
Monolithic Power Systems, Inc.
V
VB
STRG
To DCDC
V
= 12V, V
IN
CH1: V
B
5V/div.
CH2: V
STRG
10V/div.
CH3: V
PFI
C4
1000µF
5V/div.
CH4: I
L
5A/div.
MP5515
and Cap Health Test
Release
= 7.5V, VB load = 5A
B
5ms/div.
2
C, ADC,
1

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Summary of Contents for MPS MP5515

  • Page 1 It pumps the input voltage to a higher backup voltage and All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. releases the energy over a hold-up time to the “MPS”...
  • Page 2 Supply Input USB Cable Ribbon Cable USB to I2C Dongle EV5515-U-00A Output Load Figure 1: EVKT-5515 Evaluation Kit Set-Up MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 3 Max input current ........... 6A Max buck-release current ......5A EN current ..........0.5mA Operating junction temp. (T ). .. -40°C to +125°C MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 4 0.792 0.808 FBB-REF Feedback voltage FBS-REF = -40°C to 125°C 0.786 0.812 DET-REF FBB, FBS, Feedback current = 0.85V MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 5 Voltage range 1.28 (12) ADC resolution bits μs (12) ADC conversion time ADC conversion for one data MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 6 11) Refer to the “Power-On Reset Delay and VB Rising Control” section on page 19 for detailed calculations. 12) Guaranteed by characterization, not tested in production. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 7 SDAH and SCLH line Capacitive load for each SDAH + SDA line and bus line SCLH + SCL line MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 8 DVDT Charge Current vs. Temperature TPOR Charge Current vs. Temperature 100 120 140 100 120 140 JUNCTION TEMPERATURE( JUNCTION TEMPERATURE( MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 9 Boost switching Peak Current vs. Boost switching Peak Current vs. Temperature ICH Resistor =200kΩ 100 120 140 JUNCTION TEMPERATURE( ICH RESISTANCE(kΩ) MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 10 JUNCTION TEMPERATURE(°C ) FBB vs. Temperature Hot-Swap Current Limit vs. Temperature -40 -20 80 100 120 140 JUNCTION TEMPERATURE(°C ) MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 11 Buck Efficiency Buck Efficiency =7.5V, L=10uH =10V, L=10uH IB=1A IB=1A IB=3A IB=3A IB=5A IB=5A STORAGE VOLTAGE (V) STORAGE VOLTAGE (V) MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 12 CH1: B_AC B_AC 100mV/div. 100mV/div. CH3: V 20V/div. CH3: V 20V/div. CH4: I 2A/div. CH4: I 2A/div. 2µs/div. 2µs/div. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 13 STRG VB load = 5A CH1: V 5V/div. CH2: V STRG 10V/div. CH3: V 5V/div. CH4: I 5A/div. 5ms/div. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 14 Over-voltage detection. A resistor divider from VIN to OVP can program the input over-voltage threshold. If the OVP voltage is higher than 0.81V, the MP5515 is forced into buck mode and recovers when the OVP voltage drops to 0.765V and VB triggers VB_UVLO with a new TPOR time as the first power-on in default.
  • Page 15 IC is disabled, but if both VIN and VCC power are not available, PGB is pulled low to about 1.3V. Interrupt output from the MP5515. INT is an open-drain output. Even if INT is pulled up to external DC source, INT is pulled low when EN is low and the IC is not in buck switching mode.
  • Page 16 Control for Current Limit & Energy Management Circuit LS Drive PGND DVDT TPOR Register TEMP Memory AGND Vin Iin Vs Figure 2: Functional Block Diagram MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 17 (see Figure 3). default with ICH bits = 11 (for typical 12V input and 10µH inductor application conditions). MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 18 Buck mode has a max current limit 1.5V is applied on ILIM externally, the ISOFET function to limit the release current. In each is shut down, and the MP5515 enters a buck-up buck mode switching cycle, the high-side switch process.
  • Page 19 Power-On Reset Delay and VB Rising Start-Up Sequence Control After the IC is enabled, MP5515 starts to work TPOR controls the power-on reset function for with the TPOR reset time and DVDT soft-start hot swapping. By floating TPOR, the TPOR time.
  • Page 20 ADC Backup Voltage The MP5515 starts the ADC only when V drops to the V threshold. ADC reads REF-FBS MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 21 Reset ‘Cap Test Start’ bit Unmask Backup_Not_OK and ADC Done Boost Mode Charging interrupt, Reset LDO_EN Figure 6: Backup Capacitance Test Work Flow MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 22 VB voltage is lower than 5V. FBB-REF STRG Voltage Power Good Indicator (PGS) The MP5515 can start up from a 2.7V low input power at 25°C or a higher temperature. If the The storage power good threshold can be temperature is lower than 25°C, the UVLO rises programmed by the PGS Threshold bits.
  • Page 23 By default, the LDO_EN bit is 0. Interrupt Control Second Event The MP5515 pulls INT high if any fault condition in the interrupt register occurs when the fault bits are not masked. This interrupt signal is asserted to inform the SOC that certain fault conditions have occurred.
  • Page 24 Cap Test POR, write 1 to the Refer to cap test state Cap test complete Done action (high) diagram. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 25 SDA signal Figure 11: Complete Data Transfer transitioning from low to high while the SCL is high (see Figure 10). MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 26 NA = NOT Acknowledge (SDA = HIGH) P = Stop Condition Slave to Master C Read Example Figure 12: I C Read and Write MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 27 Cap Test Timer High Byte 0000 0000 LDO_E 0x1Bh Recover Recover 0000 Control mode 0011 (13) 0x1Fh Reserve Reserve 0011 MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 28 This bit will not affect the buck release after V is charged high STRG even if ENCH is set to 0. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 29 0: no TEMP ADC result, or TEMP ADC result is lower than Temp ADC Warn Level. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 30 °C, write 1 IC TJ Shut down D[4] to this bit to reset it to 0 and reset the interrupt event. The MP5515 resumes working when the temperature drops, even if the interrupt signal is not cleared. 0: no OTP occurs.
  • Page 31 TEMP ADC Warn D[4:0] 1 1111 external sensor). High bits of TEMP ADC results are compared with Level this warn level. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 32 Low bits of cap test timer results, LSB = 1ms. D[7:0] Cap Test Timer 0000 0000 High bits of cap test timer results. D[7:0] MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 33 110: 860kHz 111: 1.25MHz 1: force IC into buck mode. Force Buck Release D[0] After resetting this bit to 0, the MP5515 continues in buck mode until VB_UVLO is triggered. Register Name: System Control3, 21h (read/write) Name Bits Default Value Description Internal input current limit option.
  • Page 34 010: increase 2% of the ILIM set current limit. 011: decrease 4% of the ILIM set current limit. 100: increase 4% of the ILIM set current limit. MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 35 The input power-failure release threshold can offset. Different capacitors have different be calculated with Equation (10):    (10) MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 36 Since boost mode and buck mode share the same inductor (and generally the buck-mode current is higher), an inductor MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 37 MP5515 – ENERGY BACKUP AND MANAGEMENT UNIT The MP5515 can start up from a 2.7V low-input small input capacitor or without an input power under temperatures 25°C or higher. If the capacitor. However, this leads to a possible temperature is lower than 25°C, the UVLO rises high-voltage spike.
  • Page 38 STRG PGND BST 25 1 CST STRG PGND PGND Top Layer AGND PGND Bottom Layer Figure 16: Recommended Layout MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 39 AGND 200kΩ AGND 100kΩ AGND AGND 1MΩ AGND PGND AGND Figure 17: 12V Input, 30V Storage Typical Application Circuit MP5515 Rev. 1.02 www.MonolithicPower.com 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
  • Page 40 NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.