Cpu Core (M8C); Overview; Internal Registers; Address Spaces - Cypress PSoC CY8C24533 Technical Reference Manual

2.

CPU Core (M8C)

This chapter explains the CPU Core, called M8C, and its associated register. It covers the internal M8C registers, address
spaces, instruction formats, and addressing modes. For additional information concerning the M8C instruction set, refer to
the PSoC Designer Assembly Language User Guide available at the Cypress web site (http://www.cypress.com/psoc). For a
complete table of the CPU Core registers, refer to the
ence of all PSoC registers in address order, refer to the
2.1

Overview

The M8C is a four MIPS 8-bit Harvard architecture micropro-
cessor. Selectable processor clock speeds from 93.7 kHz to
24 MHz allow the M8C to be tuned to a particular applica-
tion's performance and power requirements. The M8C sup-
ports a rich instruction set which allows for efficient low level
language support.
2.2

Internal Registers

The M8C has five internal registers that are used in program
execution. The following is a list of these registers.
■ Accumulator (A)
■ Index (X)
■
Program Counter (PC)
■ Stack Pointer (SP)
■ Flags (F)
All of the internal M8C registers are eight bits in width,
except for the PC, which is 16 bits wide. Upon reset, A, X,
PC, and SP are reset to 00h. The Flag register (F) is reset to
02h, indicating that the Z flag is set.
With each stack operation, the SP is automatically incre-
mented or decremented so that it always points to the next
stack byte in RAM. If the last byte in the stack is at address
,
FFh the stack pointer wraps to RAM address 00h. It is the
firmware developer's responsibility to ensure that the stack
does not overlap with user-defined variables in RAM.
With the exception of the F register, the M8C internal regis-
ters are not accessible via an explicit register address. The
internal M8C registers are accessed using the following
instructions:
■
MOV A, expr
■
MOV X, expr
■
SWAP A, SP
■
OR F, expr
■
JMP LABEL
Document # 001-20559 Rev. *D
"Summary Table of the Core Registers" on page
Register Details chapter on page
The F register can be read by using address F7h in either
register bank
2.3

Address Spaces

The M8C has three address spaces: ROM, RAM, and regis-
ters. The ROM address space includes the supervisory
ROM (SROM) and the Flash. The ROM address space is
accessed via its own address and data bus.
The ROM address space is composed of the Supervisory
ROM and the on-chip Flash program store. Flash is orga-
nized into 64-byte blocks. The user need not be concerned
with program store page boundaries, as the M8C automati-
cally increments the 16-bit PC on every instruction making
the block boundaries invisible to user code. Instructions
occurring on a 256-byte Flash page boundary (with the
exception of jmp instructions) incur an extra M8C clock
cycle, as the upper byte of the PC is incremented.
The register address space is used to configure the PSoC
microcontroller's programmable blocks. It consists of two
banks of 256 bytes each. To switch between banks, the XIO
bit in the Flag register is set or cleared (set for Bank1,
cleared for Bank0). The common convention is to leave the
bank set to Bank0 (XIO cleared), switch to Bank1 as needed
(set XIO), then switch back to Bank0.
32. For a quick refer-
47.
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