Kill Operation - Cypress PSoC CY8C24533 Technical Reference Manual

If the width of the PWM low time is reduced to a point where
it is equal to the dead band period, the corresponding
phase, PHI2, disappears altogether. Note that after the ris-
ing edge of the PWM, the opposite phase still has the pro-
grammed dead band. Figure 17-12
where the dead band period is two and the PWM width is
two. In this case, the high time of PHI2 is zero clocks. Note
that the phase 1 dead band time is still two clocks.
Figure 17-12. PWM Width Equal to Dead Band Period
CLK
PWM
PHI1
PHI2
In the case where the dead band period is greater than the
high or low of the PWM reference, the output of the associ-
ated phase is not asserted high.
17.3.3.2

Kill Operation

It is assumed that the KILL input is not synchronized at the
row input. (This is not a requirement; however, if synchro-
nized, the KILL operation has up to two 24 MHz clock cycles
latency, which is undesirable.) To support the restart modes,
the negation of KILL is internally (in the block) synchronized
to the 24 MHz system clock.
There are three KILL modes supported. In all cases, the
KILL signal asynchronously forces the outputs to logic 0.
The differences in the modes come from how dead band
processing is restarted.
1. Synchronous Restart Mode : When KILL is asserted
high, the internal state is held in reset and the initial dead
band period is reloaded into the counter. While KILL is
held high, incoming PWM reference edges are ignored.
When KILL is negated, the next incoming PWM refer-
ence edge restarts dead band processing. See
Figure 17-13.
2. Asynchronous Restart Mode : When KILL is asserted
high, the internal state is not affected. When KILL is
negated, the outputs are restored, subject to a minimum
disable time between one-half and one and one-half
clock cycle. See Figure
3. Disable Mode : There is no specific timing associated
with this mode. The block is disabled and the user must
re-enable the function in firmware to continue process-
ing.
Document # 001-20559 Rev. *D
shows an example
2
2 2
17-14.
Figure 17-13. Synchronous Restart KILL Mode
Short KILL, outputs off for
remainder of current cycle.
PWM
REFERENCE
PHI1
PHI2
KILL
Output is off for duration
of KILL on time.
PWM
REFERENCE
PHI1
PHI2
KILL
Figure 17-14. Asynchronous Restart Kill Mode
Outputs are disabled
immediately on KILL.
BLOCK CLK
PHI1 or PHI2
KILL
Example of KILL shorter
than the minimum.
PWM
REFERENCE
PHI1
PHI2
KILL
Example of KILL longer
than the minimum.
PWM
REFERENCE
PHI1
PHI2
KILL
Digital Blocks
Operation resumes on
the next PWM edge.
Operation resumes
These edges
on this edge.
are skipped.
Minimum disable time
is between ½ and 1½
block clock cycle.
Outputs are forced low only as
long as the KILL is asserted,
subject to the minimum disable
time. Internal operation is
unaffected.
201