Related Manuals for GigaDevice Semiconductor GD32VF103
Summary of Contents for GigaDevice Semiconductor GD32VF103
- Page 1 GD32VF103 User Manual GigaDevice Semiconductor Inc. GD32VF103 RISC-V 32-bit MCU User Manual Revision 1.0 ( Jun. 2019 )
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Page 2: Table Of Contents
GD32VF103 User Manual Table of Contents Table of Contents ....................... 2 List of Figures ........................14 List of Tables ........................20 1. System and memory architecture ................22 1.1. RISC-V CPU ......................... 22 1.2. System architecture ......................22 1.3. Memory map ........................24 On-chip SRAM memory ........................ - Page 3 GD32VF103 User Manual Option byte status register (FMC_OBSTAT) ................. 45 2.4.7. Erase/Program Protection register (FMC_WP) ................45 2.4.8. Product ID register (FMC_PID) ...................... 46 2.4.9. 3. Power management unit (PMU) ................47 3.1. Overview ........................... 47 3.2. Characteristics ........................47 3.3.
- Page 4 GD32VF103 User Manual APB1 reset register (RCU_APB1RST) ..................79 5.3.5. AHB enable register (RCU_AHBEN) ..................... 82 5.3.6. APB2 enable register (RCU_APB2EN) ..................83 5.3.7. APB1 enable register (RCU_APB1EN) ..................85 5.3.8. Backup domain control register (RCU_BDCTL) ................87 5.3.9. Reset source/clock register (RCU_RSTSCK) ................88 5.3.10.
- Page 5 GD32VF103 User Manual TIMER AF remapping ........................109 7.4.4. USART AF remapping ........................110 7.4.5. I2C0 AF remapping ......................... 110 7.4.6. SPI0 AF remapping ........................111 7.4.7. SPI2/I2S2 AF remapping ....................... 111 7.4.8. CAN0 AF remapping ........................111 7.4.9. CAN1 AF remapping ........................111 7.4.10.
- Page 6 GD32VF103 User Manual Circular mode ..........................137 9.4.5. Memory to memory mode ......................137 9.4.6. Channel configuration ........................137 9.4.7. Interrupt ............................138 9.4.8. DMA request mapping ........................139 9.4.9. 9.5. Register definition ......................142 Interrupt flag register (DMA_INTF) ....................142 9.5.1.
- Page 7 GD32VF103 User Manual Programmable resolution (DRES) - fast conversion mode ..........164 11.4.12. On-chip hardware oversampling ....................165 11.4.13. 11.5. ADC sync mode ......................166 11.6. Free mode ........................167 11.6.1. Regular parallel mode ........................168 Inserted parallel mode ........................168 11.6.2.
- Page 8 GD32VF103 User Manual DAC concurrent conversion ......................192 12.3.9. 12.4. Register definition ......................193 Control register (DAC_CTL) ......................193 12.4.1. Software trigger register (DAC_SWT) ..................195 12.4.2. DAC0 12-bit right-aligned data holding register (DAC0_R12DH) ..........196 12.4.3. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ..........196 12.4.4.
- Page 9 GD32VF103 User Manual RTC divider low register (RTC_DIVL) ..................219 14.4.6. RTC counter high register (RTC_CNTH) ..................220 14.4.7. RTC counter low register (RTC_CNTL)..................220 14.4.8. RTC alarm high register (RTC_ALRMH) ..................221 14.4.9. RTC alarm low register (RTC_ALRML) ................... 221 14.4.10.
- Page 10 GD32VF103 User Manual 16.4. Register definition ......................344 Status register (USART_STAT) ....................344 16.4.1. Data register (USART_DATA) ....................... 346 16.4.2. Baud rate register (USART_BAUD) ..................... 346 16.4.3. Control register 0 (USART_CTL0) ....................347 16.4.4. Control register 1 (USART_CTL1) ....................349 16.4.5.
- Page 11 GD32VF103 User Manual 18.4. SPI signal description ....................381 Normal configuration ........................381 18.4.1. 18.5. SPI function overview ....................382 SPI clock timing and data format ....................382 18.5.1. NSS function ............................ 382 18.5.2. SPI operating modes ........................383 18.5.3.
- Page 12 GD32VF103 User Manual Register definition ....................424 19.4. NOR/PSRAM controller registers ....................424 19.4.1. Controller area network (CAN) ................427 Overview ........................427 20.1. Characteristics ......................427 20.2. Function overview ....................428 20.3. 20.3.1. Working mode ..........................428 20.3.2. Communication modes ........................429 20.3.3.
- Page 13 GD32VF103 User Manual 21.3. Block diagram ....................... 462 21.4. Signal description ......................462 21.5. Function overview ......................462 21.5.1. USBFS clocks and working modes ....................462 21.5.2. USB host function ........................... 464 USB device function ........................466 21.5.3. OTG function overview ........................467 21.5.4.
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Page 14: List Of Figures
GD32VF103 User Manual List of Figures Figure 1-1. GD32VF103 system architecture ....................24 Figure 2-1. Process of page erase operation ....................34 Figure 2-2. Process of mass erase operation ..................... 35 Figure 2-3. Process of word program operation ..................37 Figure 3-1. - Page 15 GD32VF103 User Manual Figure 11-19. Trigger rotation: inserted channels in discontinuous mode ......... 171 Figure 11-20. Regular parallel & trigger rotation mode ................172 Figure 11-21. Trigger occurs during inserted conversion ..............172 Figure 11-22 Follow-up single channel with inserted sequence CH1, CH2 ......... 173 Figure 12-1.
- Page 16 GD32VF103 User Manual Figure 15-32. Pause TIMER0 with O0CPREF signal of Timer2 ............... 251 Figure 15-33. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input ..........252 Figure 15-34. General Level 0 timer block diagram ................. 280 Figure 15-35. Normal mode, internal clock divided by 1 ................. 281 Figure 15-36.
- Page 17 GD32VF103 User Manual Figure 17-4. Clock synchronization ......................357 Figure 17-5. SDA Line arbitration ........................ 357 Figure 17-6. I2C communication flow with 7-bit address ................ 358 Figure 17-7. I2C communication flow with 10-bit address (Master Transmit) ........358 Figure 17-8. I2C communication flow with 10-bit address (Master Receive) ........358 Figure 17-9.
- Page 18 GD32VF103 User Manual CHLEN=0, CKPL=1) ..........................397 Figure 18-34. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ..........................397 Figure 18-35. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ..........................397 Figure 18-36. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ..........................
- Page 19 GD32VF103 User Manual Figure 20-8. 16-bit mask mode filter ......................434 Figure 20-9. 32-bit list mode filter........................ 434 Figure 20-10. 16-bit list mode filter ......................434 Figure 20-11. The bit time ..........................438 Figure 21-1. USBFS block diagram ......................462 Figure 21-2.
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Page 20: List Of Tables
List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ........23 Table 1-2. Memory map of GD32VF103 devices ..................25 Table 1-3. Boot modes ............................ 29 Table 2-1. Base address and size for flash memory .................. 32 Table 2-2. - Page 21 GD32VF103 User Manual Table 13.1. Min/max FWDGT timeout period at 40 kHz (IRC40K) ............203 Table 13.2. Min/max timeout value at 54 MHz (f ) ................210 PCLK1 Table 15-1. Timers (TIMERx) are devided into three sorts ..............222 Table 15-2. Complementary outputs controlled by parameters ............240 Table 15-3.
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Page 22: System And Memory Architecture
1.2. System architecture A 32-bit multilayer bus is implemented in the GD32VF103 devices, which makes the parallel access paths between multiple masters and slaves in the system possible The multilayer bus consists of an AHB interconnect matrix, one AHB bus and two APB buses. The... -
Page 23: Table 1-1. The Interconnection Relationship Of The Ahb Interconnect Matrix
GD32VF103 User Manual interconnection relationship of the AHB interconnect matrix is shown below. In Table 1-1. The matrix, “1” indicates the interconnection relationship of the AHB interconnect corresponding master is able to access the corresponding slave through the AHB interconnect matrix, the blank indicates the corresponding master cannot access the corresponding slave through the AHB interconnect matrix. -
Page 24: Memory Map
GD32VF103 User Manual Figure . GD32VF103 system architecture JTAG POR/ PDR Flash Flash Ibus Memory RISC_V Memory Controller : 108MHz Dbus Fmax:108MHz 1.2V ECLIC Master Slave AHB Peripherals 8MHz SRAM GP DMA0 SRAM Controller Master Slave GP DMA1 HXTAL 3-25MHz... -
Page 25: Table 1-2. Memory Map Of Gd32Vf103 Devices
Table 1-2. Memory map of GD32VF103 devices shows the memory map of the GD32VF103 series devices, including Code, SRAM, peripheral, and other pre-defined regions. Almost each peripheral is allocated 1KB of space. This allows simplifying the address decoding for each peripheral. - Page 26 GD32VF103 User Manual Pre-defined Address Peripherals Regions 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF...
- Page 27 GD32VF103 User Manual Pre-defined Address Peripherals Regions 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF...
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Page 28: On-Chip Sram Memory
0x0000 0000 - 0x0001 FFFF 1.3.1. On-chip SRAM memory The GD32VF103 series of devices contain up to 32 KB of on-chip SRAM which address starts at 0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) accesses. 1.3.2. -
Page 29: Boot Configuration
1.4. Boot configuration The GD32VF103 devices provide three kinds of boot sources which can be selected by the BOOT0 and BOOT1 pins. The details are shown in the following table. The value on the two pins is latched on the 4th rising edge of CK_SYS after a reset. User can select the required boot source by set the BOOT0 and BOOT1 pins after a power-on reset or a system reset. -
Page 30: Memory Density Information
GD32VF103 User Manual 1.5.1. Memory density information Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes. - Page 31 GD32VF103 User Manual UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID...
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Page 32: Flash Memory Controller (Fmc)
GD32VF103 User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the flash. It also provides page erase, mass erase, and word/half-word program operations for flash memory. -
Page 33: Read Operations
GD32VF103 User Manual Note: The Information Block stores the boot loader. This block cannot be programmed or erased by user. 2.3.2. Read operations The flash can be addressed directly as a common memory space. Any instruction fetch and the data access from the flash are through the IBUS or DBUS from the CPU. -
Page 34: Mass Erase
GD32VF103 User Manual if the target erase page is being used to fetch codes or to access data. The FMC will not provide any notification when this occurs. Additionally, the page erase operation will be ignored on erase/program protected pages. In this condition, a flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTL registers is set. -
Page 35: Main Flash Programming
GD32VF103 User Manual registers. Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT registers. Read and verify the flash memory if required using a DBUS access. When the operation is executed successfully, the ENDF in FMC_STAT registers is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL registers is set. - Page 36 GD32VF103 User Manual Unlock the FMC_CTL registers if necessary. Check the BUSY bit in FMC_STAT registers to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
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Page 37: Option Bytes Erase
GD32VF103 User Manual Figure 2-3. Process of word program operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0... -
Page 38: Option Bytes Modify
GD32VF103 User Manual When the operation is executed successful, the ENDF in FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. 2.3.8. Option bytes modify The FMC provides an erase and then program function which is used to modify the option bytes block in flash. -
Page 39: Page Erase/Program Protection
0x1fff f80e WP[31:24] Page Erase/Program Protection bit 31 to 24 WP[30:24]: Each bit is related to 4KB flash protection, that means 4 pages for GD32VF103. Bit 0 configures the first 4KB flash protection, and so on. 0x1fff f80f WP_N[31:24] WP complement value bit 31 to 24 2.3.10. -
Page 40: Security Protection
GD32VF103 User Manual the Flash Memory page protection functions will be disabled. When WP in the option bytes is modified, a system reset followed is necessary. 2.3.11. Security protection The FMC provides a security protection function to prevent illegal code/data access on the Flash memory. -
Page 41: Register Definition
GD32VF103 User Manual 2.4. Register definition FMC base address: 0x4002 2000 2.4.1. Wait state register (FMC_WS) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. -
Page 42: Option Byte Unlock Key Register (Fmc_Obkey)
GD32VF103 User Manual Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock key These bits are only be written by software. Write KEY[31:0] with keys to unlock FMC_CTL register 2.4.3. Option byte unlock key register (FMC_OBKEY) Address offset: 0x08 Reset value: 0x0000 0000... -
Page 43: Control Register (Fmc_Ctl)
GD32VF103 User Manual When erase/program on protected pages, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. -
Page 44: Address Register (Fmc_Addr)
GD32VF103 User Manual Reserved Must be kept at reset value. FMC_CTL lock bit This bit is cleared by hardware when right sequence written to FMC_KEY register. This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC. -
Page 45: Option Byte Status Register (Fmc_Obstat)
GD32VF103 User Manual ADDR[31:16] ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase/program command address bits These bits are configured by software. ADDR bits are the address of flash erase/program command 2.4.7. Option byte status register (FMC_OBSTAT) Address offset: 0x1C Reset value: 0x0XXX XXXX. -
Page 46: Product Id Register (Fmc_Pid)
GD32VF103 User Manual WP[31:16] WP[1 Bits Fields Descriptions 31:0 WP[31:0] Store WP of option bytes block after system reset 2.4.9. Product ID register (FMC_PID) Address offset: 0x100 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) PID[31:16]... -
Page 47: Power Management Unit (Pmu)
The power consumption is regarded as one of the most important issues for the devices of GD32VF103 series. According to the Power management unit (PMU), provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption. -
Page 48: Battery Backup Domain
GD32VF103 User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP1 WKUP4 BREG WKUP2 NRST WKUP3 SLEEPING RISC-V FWDGT SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V PLLs... -
Page 49: Figure 3-2. Waveform Of The Por/Pdr
GD32VF103 User Manual event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in theReal-time Clock (RTC). -
Page 50: Figure 3-3. Waveform Of The Lvd Threshold
GD32VF103 User Manual Figure 3-2. Waveform of the POR/PDR 50mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD... -
Page 51: Power Domain
3.3.4. Power saving modes After a system reset or a power reset, the GD32VF103 MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, PCLK2) or gating the clocks of the unused peripherals. -
Page 52: Table 3-1. Power Saving Mode Summary
GD32VF103 User Manual Deep-sleep mode The Deep-sleep mode is based on the SLEEPDEEP mode of the RISC-V. In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC8M, HXTAL and PLLs are disabled. The contents of SRAM and registers are preserved. The LDO can operate normally or in low power mode depending on the LDOLP bit in the PMU_CTL register. - Page 53 GD32VF103 User Manual Mode Sleep Deep-sleep Standby Any interrupt from EXTI NRST pin Any interrupt for WFI lines for WFI WKUP pin Wakeup Any event (or interrupt) Any event(or interrupt) from FWDGT reset for WFE(WFI) EXTI for WFE(WFI) IRC8M wakeup time,...
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Page 54: Register Definition
GD32VF103 User Manual 3.4. Register definition PMU base address: 0x4000 7000 3.4.1. Control register (PMU_CTL) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved BKPWEN... -
Page 55: Control And Status Register (Pmu_Cs)
GD32VF103 User Manual WURST Wakeup Flag Reset 0: No effect 1: Reset the wakeup flag This bit is always read as 0. STBMOD Standby Mode 0: Enter the Deep-sleep mode when the RISC-V enters SLEEPDEEP mode 1: Enter the Standby mode when the RISC-V enters SLEEPDEEP mode... - Page 56 GD32VF103 User Manual STBF Standby Flag 0: The device has not entered the Standby mode 1: The device has been in the Standby mode This bit is cleared only by a POR/PDR or by setting the STBRST bit in the PMU_CTL register.
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Page 57: Backup Registers (Bkp)
GD32VF103 User Manual Backup registers (BKP) 4.1. Overview The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, they are forty-two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from Standby mode or system reset do not affect these registers. -
Page 58: Tamper Detection
GD32VF103 User Manual 4.3.2. Tamper detection In order to protect the important user data, the MCU provides the tamper detection function, and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. -
Page 59: Register Definition
GD32VF103 User Manual 4.4. Register definition BKP base address: 0x4000 6C00 4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) -
Page 60: Tamper Pin Control Register (Bkp_Tpctl)
GD32VF103 User Manual 1: Enable RTC clock calibration output with the frequency f When enable, the TAMPER pin will output a clock RTCCLK ASOEN has the priority over COEN. When ASOEN is set, the TAMPER pin will output the RTC alarm or second signal whether COEN is set or not. - Page 61 GD32VF103 User Manual Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred This bit is reset by writing 1 to the TIR bit or the TPIE bit being 0. Tamper event flag 0: No tamper event occurred 1: A tamper event occurred This bit is reset by writing 1 to the TER bit.
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Page 62: Reset And Clock Unit (Rcu)
5.1.1. Overview GD32VF103 Reset Control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the Backup domain. The system reset resets the processor core and peripheral IP components except for the JTAG controller and the Backup domain. -
Page 63: Clock Control Unit (Cctl)
GD32VF103 User Manual source (external or internal reset). Figure 5-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us pulse System Reset FWDGT_RSTn generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the Backup domain control... -
Page 64: Figure 5-2. Clock Tree
GD32VF103 User Manual Figure 5-2. Clock tree USB OTG (to FMC) 48 MHz CK_USBFS Prescaler SCS[1:0] 1,1.5,2,2.5 (to USBFS) CK_FMC CK_IRC8M 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M …,32 108 MHz max Prescaler 108 MHz max (to EXMC) EXMC enable ÷... -
Page 65: Characteristics
GD32VF103 User Manual prescaler is not 1). The USBFS is clocked by the clock of CK_PLL as the clock source of 48MHz. The I2S is clocked by the clock of CK_SYS or PLL2*2 which defined by I2SxSEL bit in RCU_CFG1 register. - Page 66 GD32VF103 User Manual Register RCU_CTL. The HXTALSTB flag in Control Register RCU_CTL indicates if the high- speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released for use until this HXTALSTB bit is set by the hardware. This specific delay period is known as the oscillator “Start-up time”.
- Page 67 GD32VF103 User Manual can be generated if the related interrupt enable bit, PLL2STBIE, in the RCU_INT Register, is set as the PLL2 becomes stable. The three PLLs are closed by hardware when entering the Deepsleep/Standby mode or HXTAL monitor fail when HXTAL used as the source clock of the PLLs.
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Page 68: Table 5-1. Clock Output 0 Source Select
GD32VF103 User Manual detected, the HXTAL will be automatically disabled. The HXTAL Clock Stuck interrupt Flag, CKMIF, in the Clock Interrupt Register, RCU_INT, will be set and the HXTAL failure event will be generated. This failure interrupt is connected to the Non-Maskable Interrupt, NMI, of the RISC-V. -
Page 69: Register Definition
GD32VF103 User Manual 5.3. Register definition RCU base address: 0x4002 1000 5.3.1. Control register (RCU_CTL) Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTALB HXTALST HXTALE Reserved... - Page 70 GD32VF103 User Manual Set by hardware to indicate if the PLL output clock is stable and ready for use. 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock.
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Page 71: Clock Configuration Register 0 (Rcu_Cfg0)
GD32VF103 User Manual ± 1%. Reserved Must be kept at reset value. IRC8MSTB IRC8M Internal 8MHz RC Oscillator stabilization Flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable... - Page 72 GD32VF103 User Manual 1000: CK_PLL1 clock selected 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected 1011: CK_PLL2 clock selected 23:22 USBFSPSC[1:0] USBFS clock prescaler selection Set and reset by software to control the USBFS clock prescaler value. The USBFS clock must be 48MHz.
- Page 73 GD32VF103 User Manual 11100: (PLL source clock x 29) 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 32) PREDV0_LSB The LSB of PREDV0 division factor This bit is the same bit as PREDV0 division factor bit [0] from RCU_CFG1. Changing the PREDV0 division factor bit [0] from RCU_CFG1, this bit is also changed.
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Page 74: Clock Interrupt Register (Rcu_Int)
GD32VF103 User Manual 0xxx: CK_SYS selected 1000: (CK_SYS / 2) selected 1001: (CK_SYS / 4) selected 1010: (CK_SYS / 8) selected 1011: (CK_SYS / 16) selected 1100: (CK_SYS / 64) selected 1101: (CK_SYS / 128) selected 1110: (CK_SYS / 256) selected... - Page 75 GD32VF103 User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value CKMIC HXTAL Clock Stuck Interrupt Clear Write 1 by software to reset the CKMIF flag. 0: Not reset CKMIF flag 1: Reset CKMIF flag PLL2STBIC PLL2 stabilization Interrupt Clear Write 1 by software to reset the PLL2STBIF flag.
- Page 76 GD32VF103 User Manual 1: Enable the PLL2 stabilization interrupt PLL1STBIE PLL1 Stabilization Interrupt Enable Set and reset by software to enable/disable the PLL1 stabilization interrupt. 0: Disable the PLL1 stabilization interrupt 1: Enable the PLL1 stabilization interrupt PLLSTBIE PLL Stabilization Interrupt Enable Set and reset by software to enable/disable the PLL stabilization interrupt.
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Page 77: Apb2 Reset Register (Rcu_Apb2Rst)
GD32VF103 User Manual 1: PLL1 stabilization interrupt generated PLLSTBIF PLL stabilization interrupt flag Set by hardware when the PLL is stable and the PLLSTBIE bit is set. Reset when setting the PLLSTBIC bit by software. 0: No PLL stabilization interrupt generated... - Page 78 GD32VF103 User Manual USART0 TIMER0R ADC1RS ADC0RS Reserved Reserved SPI0RST Reserved PERST PDRST PCRST PBRST PARST Reserved AFRST Bits Fields Descriptions 31:15 Reserved Must be kept at reset value USART0RST USART0 Reset This bit is set and reset by software.
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Page 79: Apb1 Reset Register (Rcu_Apb1Rst)
GD32VF103 User Manual 1: Reset the GPIO port C PBRST GPIO port B reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port B PARST GPIO port A reset This bit is set and reset by software. - Page 80 GD32VF103 User Manual 1: Reset power control unit BKPIRST Backup interface reset This bit is set and reset by software. 0: No reset 1: Reset backup interface CAN1RST CAN1 reset This bit is set and reset by software. 0: No reset...
- Page 81 GD32VF103 User Manual Reserved Must be kept at reset value SPI2RST SPI2 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI2 SPI1RST SPI1 reset This bit is set and reset by software. 0: No reset...
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Page 82: Ahb Enable Register (Rcu_Ahben)
GD32VF103 User Manual 1: Reset the TIMER1 5.3.6. AHB enable register (RCU_AHBEN) Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved USBFSE FMCSPE SRAMSP Reserved Reserved EXMCEN Reserved CRCEN Reserved Reserved... -
Page 83: Apb2 Enable Register (Rcu_Apb2En)
GD32VF103 User Manual Reserved Must be kept at reset value SRAMSPEN SRAM interface clock enable when sleep mode This bit is set and reset by software to enable/disable SRAM interface clock during Sleep mode. 0: Disabled SRAM interface clock during Sleep mode. - Page 84 GD32VF103 User Manual TIMER0EN TIMER0 clock enable This bit is set and reset by software. 0: Disabled TIMER0 clock 1: Enabled TIMER0 clock ADC1EN ADC1 clock enable This bit is set and reset by software. 0: Disabled ADC1 clock 1: Enabled ADC1 clock...
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Page 85: Apb1 Enable Register (Rcu_Apb1En)
GD32VF103 User Manual 5.3.8. APB1 enable register (RCU_APB1EN) Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) UART4E UART3E USART2 USART1 Reserved DACEN PMUEN BKPIEN CAN1EN CAN0EN Reserved I2C1EN I2C0EN Reserved WWDGT... - Page 86 GD32VF103 User Manual 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software.
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Page 87: Backup Domain Control Register (Rcu_Bdctl)
GD32VF103 User Manual This bit is set and reset by software. 0: Disabled TIMER6 clock 1: Enabled TIMER6 clock TIMER5EN TIMER5 clock enable This bit is set and reset by software. 0: Disabled TIMER5 clock 1: Enabled TIMER5 clock TIMER4EN TIMER4 clock enable This bit is set and reset by software. -
Page 88: Reset Source/Clock Register (Rcu_Rstsck)
GD32VF103 User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by software. - Page 89 GD32VF103 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGT Reserved RSTFC Reserved RSTF RSTF RSTF RSTF RSTF RSTF IRC40K IRC40KE Reserved Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated.
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Page 90: Ahb Reset Register (Rcu_Ahbrst)
GD32VF103 User Manual 1: External PIN reset generated Reserved Must be kept at reset value RSTFC Reset flag clear This bit is set by software to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags 23:2... -
Page 91: Clock Configuration Register 1 (Rcu_Cfg1)
GD32VF103 User Manual 5.3.12. Clock configuration register 1 (RCU_CFG1) Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PREDV0 Reserved I2S2SEL I2S1SEL PLL2MF[3:0] PLL1MF[3:0] PREDV1[3:0] PREDV0[3:0] Bits Fields Descriptions 31:19 Reserved Must be kept at reset value... - Page 92 GD32VF103 User Manual 1111: (PLL2 source clock x 20) 11:8 PLL1MF[3:0] The PLL1 clock multiplication factor Set and reset by software. 00xx: reserve 010x: reserve 0110: (PLL1 source clock x 8) 0111: (PLL1 source clock x 9) 1000 :(PLL1 source clock x 10)
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Page 93: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32VF103 User Manual 0100: PREDV0 input source clock divided by 5 0101: PREDV0 input source clock divided by 6 0110: PREDV0 input source clock divided by 7 0111: PREDV0 input source clock divided by 8 1000: PREDV0 input source clock divided by 9... -
Page 94: Interrupt/Event Controller (Exti)
GD32VF103 User Manual Interrupt/event controller (EXTI) 6.1. Overview RISC-V integrates the Enhancement Core-Local Interrupt Controller (ECLIC) for efficient interrupts processing. ECLIC is designed to provide low-latency, vectored, pre-emptive interrupts for RISC-V systems. When activated the ECLIC subsumes and replaces the existing RISC-V local interrupt scheme (CLINT). -
Page 95: Table 6-1. Interrupt Vector Table
GD32VF103 User Manual Table Interrupt vector table Vector Interrupt Description Vector Address Number CLIC_INT_SFT 0x0000_000C CLIC_INT_TMR 0x0000_001C CLIC_INT_BWEI 0x0000_0044 CLIC_INT_PMOVI 0x0000_0048 WWDGT interrupt 0x0000_004C LVD from EXTI interrupt 0x0000_0050 Tamper interrupt 0x0000_0054 RTC global interrupt 0x0000_0058 FMC global interrupt 0x0000_005C... - Page 96 GD32VF103 User Manual Vector Interrupt Description Vector Address Number SPI0 global interrupt 0x0000_00D8 SPI1 global interrupt 0x0000_00DC USART0 global interrupt 0x0000_00E0 USART1 global interrupt 0x0000_00E4 USART2 global interrupt 0x0000_00E8 EXTI line[15:10] interrupts 0x0000_00EC RTC alarm from EXTI interrupt 0x0000_00F0 USBFS wakeup from EXTI interrupt...
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Page 97: External Interrupt And Event (Exti) Block Diagram
GD32VF103 User Manual 6.4. External interrupt and event (EXTI) block diagram Figure 6-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~18 Edge detector To ECLIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 6.5. External Interrupt and Event function overview The EXTI contains up to 19 independent edge detectors and generates interrupts request or event to the processer. -
Page 98: Table 6-2. Exti Source
GD32VF103 User Manual Table 6-2. EXTI source EXTI Line Source Number PA0/PB0/PC0/PD0/PE0 PA1/PB1/PC1/PD1/PE1 PA2/PB2/PC2/PD2/PE2 PA3/PB3/PC3/PD3/PE3 PA4/PB4/PC4/PD4/PE4 PA5/PB5/PC5/PD5/PE5 PA6/PB6/PC6/PD6/PE6 PA7/PB7/PC7/PD7/PE7 PA8/PB8/PC8/PD8/PE8 PA9/PB9/PC9/PD9/PE9 PA10/PB10/PC10/PD10/PE10 PA11/PB11/PC11/PD11/PE11 PA12/PB12/PC12/PD12/PE12 PA13/PB13/PC13/PD13/PE13 PA14/PB14/PC14/PD14/PE14 PA15/PB15/PC15/PD15/PE15 RTC Alarm USB Wakeup... -
Page 99: Register Definition
GD32VF103 User Manual 6.6. Register definition EXTI base address: 0x4001 0400 6.6.1. Interrupt enable register (EXTI_INTEN) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10... -
Page 100: Rising Edge Trigger Enable Register (Exti_Rten)
GD32VF103 User Manual 1: Event from Linex is enabled. 6.6.3. Rising edge trigger enable register (EXTI_RTEN) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11... -
Page 101: Software Interrupt Event Register (Exti_Swiev)
GD32VF103 User Manual 6.6.5. Software interrupt event register (EXTI_SWIEV) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4... -
Page 102: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32VF103 User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 80 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE15 for the device to implement logic input/output functions. -
Page 103: Gpio Pin Configuration
GD32VF103 User Manual Configuration mode CTL[1:0] MD[1:0] OCTL don’t care Analog don’t care Input floating Input Input pull-down Input pull-up Push-pull 0 or 1 General purpose 00: Reserved Output (GPIO) Open-drain 0 or 1 01: Speed up to 10MHz 10: Speed up to 2MHz don’t care... -
Page 104: External Interrupt/Event Lines
GD32VF103 User Manual The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen. And the data on the external pins can be captured at every APB2 clock cycle to the port input status register (GPIOx_ISTAT). -
Page 105: Output Configuration
GD32VF103 User Manual Alternate Function Input protection Input Read I/O pin Status Register Schmitt trigger Input driver 7.3.5. Output configuration When GPIO pin is configured as output: The schmitt trigger input is enabled. The weak pull-up and pull-down resistors are disabled. -
Page 106: Analog Configuration
GD32VF103 User Manual 7.3.6. Analog configuration When GPIO pin is used as analog configuration: The weak pull-up and pull-down resistors are disabled. The output buffer is disabled. The schmitt trigger input is disabled. The port input status register of this I/O port bit is “0”. -
Page 107: Io Pin Function Selection
GD32VF103 User Manual Output driver Alternate Function Output Output Control protection I/O pin Alternate Function Input Schmitt trigger Input driver 7.3.8. IO pin function selection Each IO pin can implement many functions, each function selected by GPIO registers. GPIO: Each IO pin can be used for GPIO input function by configuring MDy bits to 0b00 in GPIOx_CTL0/GPIOx_CTL1 registers. -
Page 108: Remapping Function I/O And Debug Configuration
GD32VF103 User Manual 7.4. Remapping function I/O and debug configuration 7.4.1. Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can be configured to have up to four different functions by setting the AFIO Port Configuration Register (AFIO_PCF0/AFIO_PCF1). -
Page 109: Timer Af Remapping
GD32VF103 User Manual 7.4.4. TIMER AF remapping Table . TIMER0 alternate function remapping TIMER0_REMAP [1:0] TIMER0_REMAP [1:0] = TIMER0_REMAP [1:0] = Alternate function = “00” (no remap) “01” (partial remap) “11” (full remap) TIMER0_ETI PA12 TIMER0_CH0 TIMER0_CH1 PE11 TIMER0_CH2 PA10... -
Page 110: Usart Af Remapping
GD32VF103 User Manual 1. For different packages and flash sizes please refer to the datasheet. Table . TIMER4 alternate function remapping Alternate function TIMER4CH3_REMAP = 0 TIMER4CH3_REMAP = 1 IRC40K internal clock is TIMER4_CH3 TIMER4_CH3 is connected to PA3 connected to TIMER4_CH3 input for calibration purpose 1. -
Page 111: Spi0 Af Remapping
GD32VF103 User Manual I2C0_SDA Remap not available on 36-pin package. 7.4.7. SPI0 AF remapping Refer to AFIO port configuration register 0 (AFIO_PCF0). Table . SPI0 alternate function remapping Alternate function SPI0_REMAP = 0 SPI0_REMAP = 1 SPI0_NSS PA15 SPI0_SCK SPI0_MISO SPI0_MOSI 7.4.8. -
Page 112: Clk Pins Af Remapping
GD32VF103 User Manual CAN1_REMAP = “0” CAN1_REMAP = “1” Alternate function CAN1_RX PB12 CAN1_TX PB13 7.4.11. CLK pins AF remapping The LXTAL oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15 individually, when the LXTAL oscillator is off. The LXTAL has priority over the GPIOs function. -
Page 113: Register Definition
GD32VF103 User Manual 7.5. Register definition base address: 0x4001 0000 AFIO GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 7.5.1. Port control register 0 (GPIOx_CTL0, x=A..E) - Page 114 GD32VF103 User Manual refer to MD0[1:0]description 19:18 CTL4[1:0] Port 4 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD4[1:0] Port 4 mode bits These bits are set and cleared by software refer to MD0[1:0]description...
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Page 115: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32VF103 User Manual These bits are set and cleared by software 00: Input mode (reset state) 01: Output mode ,max speed 10MHz 10: Output mode ,max speed 2 MHz 11: Output mode ,max speed 50MHz 7.5.2. Port control register 1 (GPIOx_CTL1, x=A..E) -
Page 116: Port Input Status Register (Gpiox_Istat, X=A
GD32VF103 User Manual refer to CTL0[1:0]description 17:16 MD12[1:0] Port 12 mode bits These bits are set and cleared by software refer to MD0[1:0]description 15:14 CTL11[1:0] Port 11 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description... -
Page 117: Port Output Control Register (Gpiox_Octl, X=A
GD32VF103 User Manual ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 ISTATy Port input status(y=0..15) -
Page 118: Port Bit Clear Register (Gpiox_Bc, X=A
GD32VF103 User Manual Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by software 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy Port Set bit y(y=0..15) -
Page 119: Event Control Register (Afio_Ec)
GD32VF103 User Manual LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can always be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked. -
Page 120: Afio Port Configuration Register 0 (Afio_Pcf0)
GD32VF103 User Manual 011: Select PORT D 100: Select PORT E PIN[3:0] Event output pin selection Set and cleared by software. Select the pin used to output the RISC-V EVENTOUT signal. 0000: Select Pin 0 0001: Select Pin 1 0010: Select Pin 2 …... - Page 121 GD32VF103 User Manual Note: This bit is available only in Extra-density devices and High-density devices. Reserved Must be kept at reset value 26:24 SWJ_CFG[2:0] Serial wire JTAG configuration These bits are write-only (when read,the value is undefined).They are used to configure the SWJ alternate function I/Os.
- Page 122 GD32VF103 User Manual REMAP[1:0] These bits are set and cleared by software 00: No remap (TIMER2_CH0/PA6,TIMER2_CH1/PA7,TIMER2_CH2/PB0, TIMER2_CH3/PB1) 01: Not used 10: Partial remap (TIMER2_CH0/PB4,TIMER2_CH1/PB5,TIMER2_CH2/PB0, TIMER2_CH3/PB1) 11: Full remap (TIMER2_CH0/PC6,TIMER2_CH1/PC7,TIMER2_CH2/PC8, TIMER2_CH3/PC9) TIMER1_REMAP TIMER1 remapping [1:0] These bits are set and cleared by software...
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Page 123: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32VF103 User Manual USART1_RX /PA3, USART1_CK/PA4) Remap (USART1_CTS/PD3, USART1_RTS/PD4,USART1_TX/PD5, USART1_RX /PD6, USART1_CK/PD7) USART0_REMAP USART0 remapping This bit is set and cleared by software 0: No remap (USART0_TX/PA9, USART0_RX /PA10) 1: Remap (USART0_TX/PB6, USART0_RX /PB7) I2C0_REMAP I2C0 remapping This bit is set and cleared by software... -
Page 124: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32VF103 User Manual 0000: PA2 pin 0001: PB2 pin 0010: PC2 pin 0011: PD2 pin 0100: PE2 pin Other configurations are reserved. EXTI1_SS [3:0] EXTI 1 sources selection 0000: PA1 pin 0001: PB1 pin 0010: PC1 pin 0011: PD1 pin 0100: PE1 pin Other configurations are reserved. -
Page 125: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32VF103 User Manual Other configurations are reserved. 11:8 EXTI6_SS [3:0] EXTI 6 sources selection 0000: PA6 pin 0001: PB6 pin 0010: PC6 pin 0011: PD6 pin 0100: PE6 pin Other configurations are reserved. EXTI5_SS [3:0] EXTI 5 sources selection 0000: PA5 pin... -
Page 126: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32VF103 User Manual 0010: PC11 pin 0011: PD11 pin 0100: PE11 pin Other configurations are reserved. 11:8 EXTI10_SS [3:0] EXTI 10 sources selection 0000: PA10 pin 0001: PB10 pin 0010: PC10 pin 0011: PD10 pin 0100: PE10 pin Other configurations are reserved. -
Page 127: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32VF103 User Manual 15:12 EXTI15_SS [3:0] EXTI 15 sources selection 0000: PA15 pin 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin Other configurations are reserved. 11:8 EXTI14_SS [3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin... - Page 128 GD32VF103 User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value EXMC_NADV EXMC_NADV connect/disconnect This bit is set and cleared by software, it controls the use of optional EXMC_NADV signal. 0: The NADV signal is connected to the output(default) 1: The NADV signal is not connected.
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Page 129: Crc Calculation Unit (Crc)
GD32VF103 User Manual CRC calculation unit (CRC) 8.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 32 bit CRC code with fixed polynomial. -
Page 130: Function Overview
GD32VF103 User Manual 8.3. Function overview CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA. -
Page 131: Register Definition
GD32VF103 User Manual 8.4. Register definition CRC base address: 0x4002 3000 8.4.1. Data register (CRC_DATA) Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads. -
Page 132: Control Register (Crc_Ctl)
GD32VF103 User Manual These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will take no effect to the byte. 8.4.3. Control register (CRC_CTL) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). -
Page 133: Direct Memory Access Controller (Dma)
GD32VF103 User Manual Direct memory access controller (DMA) 9.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions. -
Page 134: Block Diagram
GD32VF103 User Manual 9.3. Block diagram Figure 9-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management... -
Page 135: Table 9-1. Dma Transfer Operation
GD32VF103 User Manual Table 9-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 32 bits 32 bits 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 3: Read BBBAB9B8[31:0] @0x8... -
Page 136: Peripheral Handshake
GD32VF103 User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register. If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –... -
Page 137: Address Generation
GD32VF103 User Manual the PRIO bits in the DMA_CHxCTL register. – For channels with equal software priority level, priority is given to the channel with lower channel number. 9.4.4. Address generation Two kinds of address generation algorithm are implemented independently for memory and peripheral, including the fixed mode and the increased mode. -
Page 138: Interrupt
GD32VF103 User Manual 5. Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register. 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register. -
Page 139: Dma Request Mapping
GD32VF103 User Manual 9.4.9. DMA request mapping Several requests from peripherals may be mapped to one DMA channel. They are logically ORed before entering the DMA. For details, see the following Figure 9-4. DMA0 request mapping Figure 9-5. DMA1 request mapping. -
Page 140: Figure 9-5. Dma1 Request Mapping
GD32VF103 User Manual Table 9-3. DMA0 requests for each channel Periphera Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER0_CH3 TIMER0_TG ● ● TIMER0_CH0 TIMER0_CH1 TIMER0_UP TIMER0_CH2 TIMER0 TIMER0_CM TIMER1_CH1 ● ● ● TIMER1 TIMER1_CH2 TIMER1_UP... - Page 141 GD32VF103 User Manual Table 9-4. DMA1 requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER4_CH3 TIMER4_CH2 ● TIMER4 TIMER4_CH1 TIMER4_CH0 TIMER4_TG TIMER4_UP ● ● ● ● TIMER5_UP TIMER5 ● ● ● ● TIMER6_UP TIMER6 ●...
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Page 142: Register Definition
GD32VF103 User Manual 9.5. Register definition DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1. -
Page 143: Interrupt Flag Clear Register (Dma_Intc)
GD32VF103 User Manual 9.5.2. Interrupt flag clear register (DMA_INTC) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3... - Page 144 GD32VF103 User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’.
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Page 145: Channel X Counter Register (Dma_Chxcnt)
GD32VF103 User Manual CMEN Circular mode enable Software set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. -
Page 146: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32VF103 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer. - Page 147 GD32VF103 User Manual This register has to be accessed by word (32-bit) Note: Do not configure this register when channel is enabled. MADDR[31:16] MADDR[15:0] Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’.
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Page 148: Debug (Dbg)
10.1. Overview The GD32VF103 series provide a large variety of debug and test features. They are implemented with a standard configuration of the RISC-V module together with a daisy chained standard TAP controller. Debug functions are integrated into the RISC-V. The debug system supports standard JTAG debug. -
Page 149: Debug Reset
GD32VF103 User Manual first shift 5-bit BYPASS instruction (5’b 11111) for BSD JTAG, and then shift normal 4-bit instruction for RISC-V JTAG. Because of the data shift under BSD JTAG BYPASS mode, adding 1 extra bit to the data chain is needed. -
Page 150: Register Definition
GD32VF103 User Manual 10.4. Register definition DBG base address: 0xE004 2000 10.4.1. ID code register (DBG_ID) Address: 0xE004 2000 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant 10.4.2. - Page 151 GD32VF103 User Manual 1: the receive register of CAN1 stops receiving data when core halted TIMER6_HOLD TIMER 6 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 6 counter for debug when core halted...
- Page 152 GD32VF103 User Manual TIMER0_HOLD TIMER 0 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 0 counter for debug when core halted WWDGT_HOLD WWDGT hold bit This bit is set and reset by software...
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Page 153: Analog-To-Digital Converter (Adc)
GD32VF103 User Manual Analog-to-digital converter (ADC) 11.1. Introduction The 12-bit ADC is an analog-to-digital converter using the successive approximation method. It has 18 multiplexed channels making the ADC convert analog signals from 16 external channels, and 2 internal channels. The analog watchdog allows the application to detect whether the input voltage goes outside the user-defined higher or lower thresholds. -
Page 154: Pins And Internal Signals
GD32VF103 User Manual – Oversampling ratio adjustable from 2 to 256x – Programmable data shift up to 8-bit ADC supply requirements: 2.6V to 3.6V, and typical power supply voltage is 3.3V ≤V ≤V ADC input range: V REF- REF+ 11.3. -
Page 155: Calibration (Clb)
GD32VF103 User Manual … … Trig select Trig select Regular Inserted channels channels EOIC Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Injected data registers （16 bits x 4） Over ADC_IN15 SAR ADC sampler Regular data registers （16 bits）... -
Page 156: Adc Clock
GD32VF103 User Manual 11.4.2. ADC clock The ADCCLK clock provided by the clock controller is synchronous APB2 clock. The RCU controller has a dedicated programmable prescaler for the ADC clock. 11.4.3. ADCON switch The ADCON bit on the ADC_CTL1 register is the enable switch of the ADC module. The ADC module will keep in reset state if this bit is 0. -
Page 157: Figure 11-3. Continuous Conversion Mode
GD32VF103 User Manual After conversion of a single inserted channel, the conversion data will be stored in the ADC_IDATA0 register, the EOC and EOIC will be set. An interrupt will be generated if the EOCIE or EOICIE bit is set. -
Page 158: Figure 11-4. Scan Conversion Mode, Continuous Disable
GD32VF103 User Manual Set the SWRCST bit, or generate an external trigger for the regular group Wait the EOC flag to be set Read the converted in the ADC_RDATA register Clear the EOC flag by writing 0 to it Repeat steps 6~8 as soon as the conversion is in need... -
Page 159: Figure 11-5. Scan Conversion Mode, Continuous Enable
GD32VF103 User Manual Configure ADC_RSQx and ADC_SAMPTx registers Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need Prepare the DMA module to transfer data from the ADC_RDATA. Set the SWRCST bit, or generate an external trigger for the regular group... -
Page 160: Inserted Channel Management
GD32VF103 User Manual Figure 11-6. Discontinuous conversion mode · · · CH11 CH16 CH12 CH17 Regular trigger One circle of regular group, RL=7, DISNUM=2 CH10 CH10 · · · Sample Inserted trigger Convert EOIC One circle of inserted group, IL=2... -
Page 161: Data Alignment
GD32VF103 User Manual Figure 11-7. Auto-insertion, CNT = 1 · · Regular group · Inserted CH15 group Sample Convert EOIC The auto insertion mode cannot be enabled when the discontinuous conversion mode is set. Triggered insertion If the ICA bit is cleared, the triggered insertion occurs if a software or external trigger occurs during the regular group channel conversion. -
Page 162: Programmable Sample Time
GD32VF103 User Manual inserted group data value may be a negative value. The sign value is extended. Figure 11-9. 12-bit Data alignment 6-bit resolution data alignment is different from 12-bit/10-bit/8-bit resolution data alignment, shown as Figure 11-10. 6-bit Data alignment Figure 11-10. -
Page 163: External Trigger
GD32VF103 User Manual 11.4.9. External trigger The conversion of regular or inserted group can be triggered by rising edge of external trigger inputs. The external trigger source of regular channel group is controlled by the ETSRC[2:0] bits in the ADC_CTL1 register, while the external trigger source of inserted channel group is... -
Page 164: Programmable Resolution (Dres) - Fast Conversion Mode
GD32VF103 User Manual be used to measure the ambient temperature of the device. The sensor output voltage can be converted into a digital value by ADC. The sampling time for the temperature sensor is recommended to be set to at least 17.1 µs. When this sensor is not in use, it can be put in power down mode by resetting the TSVREN bit. -
Page 165: On-Chip Hardware Oversampling
GD32VF103 User Manual (min) CONV SMPL DRES[1:0] (ns) at (us) at CONV (ADC clock (ADC clock (ADC clock bits =14MHz =14MHz cycles) cycles) cycles) 464 ns 571 ns 11.4.13. On-chip hardware oversampling The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU. -
Page 166: Adc Sync Mode
GD32VF103 User Manual example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 11-12. Numerical example with 5-bits shift and rounding Table 11-6. Maximum output results vs N and M (Grayed values indicates truncation) below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF. -
Page 167: Free Mode
GD32VF103 User Manual In sync mode, when configure the conversion which is triggered by an external event, the slave ADC must be configured as triggered by the software in order to prevent false triggers to start unwanted conversion. However, the external trigger must be enabled for ADC master and ADC slave. -
Page 168: Regular Parallel Mode
GD32VF103 User Manual 11.6.1. Regular parallel mode This mode converts the regular channel simultaneously. The source of external trigger comes from the regular group MUX of ADC0 (selected by the ETSRC[2:0] bits in the ADC_CTL1 register). A simultaneous trigger is provided to ADC1. -
Page 169: Follow-Up Fast Mode
GD32VF103 User Manual Figure 11-15. Inserted parallel mode on 4 channels 11.6.3. Follow-up fast mode This mode can be running on the regular channel group (usually one channel). The source of external trigger comes from the regular channel MUX of ADC0 (selected by the ETSRC[2:0] bits in the ADC_CTL1 register). -
Page 170: Trigger Rotation Mode
GD32VF103 User Manual after 14 ADC clock cycles, after the second 14 ADC clock cycles the ADC1 runs again. Continuous mode can’t be used in this mode, because it continuously converts the regular channel. The behavior of follow-up slow mode shows in the Figure 11-17. -
Page 171: Combined Regular Parallel & Inserted Parallel Mode
GD32VF103 User Manual Figure 11-18. Trigger rotation: inserted channel group If the discontinuous mode is enabled for both ADC0 and ADC1, when the first trigger occurs, the first inserted channel in ADC0 is converted. When the second trigger occurs, the first inserted channel in ADC1 is converted. -
Page 172: Combined Inserted Parallel & Follow-Up Mode
GD32VF103 User Manual conversion shows in the Figure 11-20. Regular parallel & trigger rotation mode When the inserted event occurs, the inserted rotation conversion is immediately started. If regular conversion is already running, in order to ensure synchronization after the inserted conversion, the regular conversion of both (master/slave) ADCs is stopped and resumed synchronously at the end of the inserted conversion. -
Page 173: Adc Interrupts
GD32VF103 User Manual Figure 11-22 Follow-up single channel with inserted sequence CH1, CH2 11.7. ADC interrupts The interrupt can be produced on one of the events: End of conversion for regular and inserted groups The analog watchdog event Separate interrupt enable bits are available for flexibility. -
Page 174: Adc Registers
GD32VF103 User Manual 11.8. ADC registers ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 11.8.1. Status register (ADC_STAT) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved STRC STIC EOIC... -
Page 175: Control Register 0 (Adc_Ctl0)
GD32VF103 User Manual Cleared by software writing 0 to it or by reading the ADC_RDATA register. Analog watchdog event flag 0: No analog watchdog event 1: Analog watchdog event Set by hardware when the converted voltage crosses the values programmed in the ADC_WDLT and ADC_WDHT registers. - Page 176 GD32VF103 User Manual 1001: Trigger rotation mode only Note: These bits are reserved in ADC1.In sync mode, the change of configuration will cause unpredictable consequences. We must disable sync mode before any configuration change. 15:13 DISNUM[2:0] Number of conversions in discontinuous mode...
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Page 177: Control Register 1 (Adc_Ctl1)
GD32VF103 User Manual 01000: ADC channel 8 01001: ADC channel 9 01010: ADC channel 10 01011: ADC channel 11 01100: ADC channel 12 01101: ADC channel 13 01110: ADC channel 14 01111: ADC channel15 10000: ADC channel16 10001: ADC channel17 Other values are reserved. - Page 178 GD32VF103 User Manual ETERC External trigger enable for regular channel 0: External trigger for regular channel disable 1: External trigger for regular channel enable 19:17 ETSRC[2:0] External trigger select for regular channel For ADC0 and ADC1: 000: Timer 0 CH0...
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Page 179: Sample Time Register 0 (Adc_Sampt0)
GD32VF103 User Manual initialized. 0: Calibration register initialize done. 1: Initialize calibration register start ADC calibration 0: Calibration done 1: Calibration start Continuous mode 0: Continuous mode disable 1: Continuous mode enable ADCON ADC ON. The ADC will be wake up when this bit is changed from low to high and take a stabilization time. -
Page 180: Sample Time Register 1 (Adc_Sampt1)
GD32VF103 User Manual SPT10[2:0] Channel sample time 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 11.8.5. Sample time register 1 (ADC_SAMPT1) Address offset: 0x10... -
Page 181: Inserted Channel Data Offset Register X (Adc_Ioffx) (X=0
GD32VF103 User Manual 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 11.8.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3) Address offset: 0x14-0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) -
Page 182: Watchdog Low Threshold Register (Adc_Wdlt)
GD32VF103 User Manual These bits define the high threshold for the analog watchdog. 11.8.8. Watchdog low threshold register (ADC_WDLT) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved WDLT[11:0] Bits Fields Descriptions... -
Page 183: Regular Sequence Register 1 (Adc_Rsq1)
GD32VF103 User Manual RSQ13[4:0] refer to RSQ0[4:0] description RSQ12[4:0] refer to RSQ0[4:0] description 11.8.10. Regular sequence register 1 (ADC_RSQ1) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RSQ11[4:0] RSQ10[4:0] RSQ9[4:1] RSQ9[0] RSQ8[4:0]... -
Page 184: Inserted Sequence Register (Adc_Isq)
GD32VF103 User Manual 31:30 Reserved Must be kept at reset value 29:25 RSQ5[4:0] refer to RSQ0[4:0] description 24:20 RSQ4[4:0] refer to RSQ0[4:0] description 19:15 RSQ3[4:0] refer to RSQ0[4:0] description 14:10 RSQ2[4:0] refer to RSQ0[4:0] description RSQ1[4:0] refer to RSQ0[4:0] description RSQ0[4:0] The channel number (0..17) is written to these bits to select a channel as the nth... -
Page 185: Inserted Data Register X (Adc_Idatax) (X= 0
GD32VF103 User Manual ISQ3 11.8.13. Inserted data register x (ADC_IDATAx) (x= 0..3) Address offset: 0x3C + 0x4*x,(x=0..3) Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved IDATAn[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value... -
Page 186: Oversample Control Register (Adc_Ovsampctl)
GD32VF103 User Manual 11.8.15. Oversample control register (ADC_OVSAMPCTL) Address offset: 0x80 Reset value: 0x0000_0000 This register has to be accessed by word(32-bit) Reserved Reserved DRES[1:0] Reserved TOVS OVSS[3:0] OVSR[2:0] Reserved OVSEN Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. - Page 187 GD32VF103 User Manual no conversion is ongoing). OVSR[2:0] Oversampling ratio This bit filed defines the number of oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: Software is allowed to write this bit only when ADCON =0 (which ensures that no conversion is ongoing).
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Page 188: Digital-To-Analog Converter (Dac)
GD32VF103 User Manual Digital-to-analog converter (DAC) 12.1. Overview Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability. -
Page 189: Function Overview
GD32VF103 User Manual pins gives the pin description. Figure 12-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRGO TIMER7_TRGO TIMER6_TRGO TIMER4_TRGO TIMER1_TRGO TIMER3_TRGO EXTI9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Table 12-1. DAC pins Name Description Signal type... -
Page 190: Dac Output Buffer
GD32VF103 User Manual 12.3.2. DAC output buffer For the concern of reducing output impedance, and driving external loads without an external operational amplifier, an output buffer is integrated inside each DAC module. The output buffer, which is turned on by default to reduce the output impedance and improve the driving capability, can be turned off by setting the DBOFFx bits in the DAC_CTL register. -
Page 191: Dac Noise Wave
GD32VF103 User Manual 12.3.6. DAC noise wave There are two methods of adding noise wave to the DAC output data: LFSR noise wave and Triangle wave. The noise wave mode can be selected by the DWMx bits in the DAC_CTL register. -
Page 192: Dac Output Voltage
GD32VF103 User Manual 12.3.7. DAC output voltage The analog output voltage on the DAC pin is determined by the following equation: *DAC_DO/4096 (12-1) output REF+ The digital input is linearly converted to an analog output voltage, its range is 0 to V REF+ 12.3.8. -
Page 193: Register Definition
GD32VF103 User Manual 12.4. Register definition DAC base address: 0x4000 7400 12.4.1. Control register (DAC_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DDMAEN1 DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 Reserved DDMAEN0... - Page 194 GD32VF103 User Manual 00: wave disabled 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1. 000: Timer 5 TRGO 001: Timer 2 TRGO 010: Timer 6 TRGO...
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Page 195: Software Trigger Register (Dac_Swt)
GD32VF103 User Manual 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DAC0 noise wave mode These bits specify the mode selection of the noise wave signal of DAC0 when external trigger of DAC0 is enabled (DTEN0=1). -
Page 196: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32VF103 User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled 12.4.3. -
Page 197: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32VF103 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value 12.4.5. -
Page 198: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32VF103 User Manual These bits specify the data that is to be converted by DAC1. 12.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0]... -
Page 199: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32VF103 User Manual 12.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved DAC0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value... -
Page 200: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32VF103 User Manual 19:16 Reserved Must be kept at reset value 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value 12.4.11. DAC concurrent mode 8-bit right-aligned data holding register... -
Page 201: Dac1 Data Output Register (Dac1_Do)
GD32VF103 User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DAC0_DO [11:0] DAC0 data output These bits, which are read only, reflect the data that is being converted by DAC0. 12.4.13. DAC1 data output register (DAC1_DO) -
Page 202: Watchdog Timer (Wdgt)
GD32VF103 User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy. -
Page 203: Figure 13.1. Free Watchdog Block Diagram
GD32VF103 User Manual Figure 13.1. Free watchdog block diagram The free watchdog is enabled by writing the value 0xCCCC in the control register (FWDGT_CTL), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated. - Page 204 Note： For all the GD32VF103 devices, when after the execution of dog reload operation, if the MCU needs enter the deepsleep/standby mode immediately, (more than 3) IRC40K clock interval must be inserted in the middle of reload and deepsleep/standby mode commands by software setting.
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Page 205: Register Definition
GD32VF103 User Manual 13.1.4. Register definition FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. - Page 206 GD32VF103 User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128 110: 1/256 111: 1/256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
- Page 207 GD32VF103 User Manual This register can be accessed by half-word(16-bit) or word(32-bit) access Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
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Page 208: Window Watchdog Timer (Wwdgt)
GD32VF103 User Manual 13.2. Window watchdog timer (WWDGT) 13.2.1. Overview The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of downcounter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared). -
Page 209: Figure 13.2. Window Watchdog Timer Block Diagram
GD32VF103 User Manual Figure 13.2. Window watchdog timer block diagram PCLK1/4096 Prescaler /1/2/4/8 7-Bit Down Counter CNT[6]=0 WDGTEN Reset CNT>WIN Reset Window WIN Write WWDGT_CTL The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. -
Page 210: Figure 13.3. Window Watchdog Timing Diagram
GD32VF103 User Manual Figure 13.3. Window watchdog timing diagram Calculate the WWDGT timeout by using the formula below. × ( CNT [ 5:0 ] +1 ) (ms) ×4096 ×2 (13-1) WWDGT PCLK1 where: : WWDGT timeout WWDGT : APB1 clock period measured in ms... -
Page 211: Register Definition
GD32VF103 User Manual 13.2.4. Register definition WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. - Page 212 GD32VF103 User Manual EWIE Early wakeup interrupt enable. An interrupt occurs when the counter reaches 0x40 or the counter is refreshed before it reaches the window value if the bit is set. It can be cleared by a hardware reset or by a RCU WWDGT software reset. A write operation of ‘0’...
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Page 213: Real-Time Clock (Rtc)
GD32VF103 User Manual Real-time Clock (RTC) 14.1. Overview The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register. -
Page 214: Rtc Reset
GD32VF103 User Manual with the value of current system time. If alarm interrupt is enabled in the RTC_INTEN register, alarm time the RTC will generate an alarm interrupt when the system time equals to the (stored in the RTC_ALRMH/L register), Figure 14.1. -
Page 215: Rtc Configuration
GD32VF103 User Manual 14.3.3. RTC configuration The RTC_PSC, RTC_CNT and RTC_ALRM registers in the RTC core are writable. These registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete. -
Page 216: Figure 14.3. Rtc Second And Overflow Waveform Example (Rtc_Psc= 3)
GD32VF103 User Manual Figure 14.3. RTC second and overflow waveform example (RTC_PSC= 3) RTCCLK RTC_ PSC RTC_Second FFFFFFFD FFFFFFFE FFFFFFFF RTC_ CNT RTC_ Overflow OVIF OVIF flag can be cleared by software... -
Page 217: Register Definition
GD32VF103 User Manual 14.4. Register definition RTC base address: 0x4000 2800 14.4.1. RTC interrupt enable register(RTC_INTEN) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields... -
Page 218: Rtc Prescaler High Register (Rtc_Psch)
GD32VF103 User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode. -
Page 219: Rtc Prescaler Low Register (Rtc_Pscl)
GD32VF103 User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value PSC[19:16] RTC prescaler value high 14.4.4. RTC prescaler low register (RTC_PSCL) Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) -
Page 220: Rtc Counter High Register (Rtc_Cnth)
GD32VF103 User Manual Reserved DIV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated. 14.4.7. -
Page 221: Rtc Alarm High Register (Rtc_Alrmh)
GD32VF103 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] RTC counter value low 14.4.9. RTC alarm high register (RTC_ALRMH) Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) -
Page 222: Timer(Timerx)
GD32VF103 User Manual Timer(TIMERx) Table 15-1. Timers (TIMERx) are devided into three sorts TIMER TIMER0 TIMER1/2/3/4 TIMER5/6 TYPE Advanced General-L0 Basic 16-bit 16-bit 16-bit Prescaler 16-bit 16-bit 16-bit Counter UP,DOWN, UP,DOWN, UP ONLY Count mode Center-aligned Center-aligned ● × ×... -
Page 223: Advanced Timer (Timerx, X=0)
GD32VF103 User Manual 15.1. Advanced timer (TIMERx, x=0) 15.1.1. Overview The advanced timer module (TIMER0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. -
Page 224: Block Diagram
GD32VF103 User Manual 15.1.3. Block diagram Figure 15-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 15-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN... -
Page 225: Figure 15-2. Normal Mode, Internal Clock Divided By 1
GD32VF103 User Manual introduced later. When the slave mode control bits SMC [2:0] are set to 0x4, 0x5 or 0x6, the internal clock TIMER_CK is the counter prescaler driving clock source. Figure 15-2. Normal mode, internal clock divided by 1... -
Page 226: Figure 15-3. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32VF103 User Manual Figure 15-3. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction. - Page 227 GD32VF103 User Manual Figure 15-4. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
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Page 228: Figure 15-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32VF103 User Manual Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) - Page 229 GD32VF103 User Manual Figure 15-6. Timing chart of down counting mode, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG 5C 5B Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear...
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Page 230: Figure 15-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32VF103 User Manual Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG... -
Page 231: Figure 15-8. Timing Chart Of Center-Aligned Counting Mode
GD32VF103 User Manual When an update event occurs, all the registers (repetition counter register, auto-reload register, prescaler register) are updated. Figure 15-8. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 15-8. Timing chart of center-aligned counting mode... -
Page 232: Figure 15-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32VF103 User Manual For odd values of CREP in center-aligned mode, the update event occurs either on the overflow or on the underflow depending on when the CREP register was written and when the counter was started. The update event is generated at overflow when the CREP was written before starting the counter and generated at underflow when the CREP was written after starting the counter. -
Page 233: Figure 15-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32VF103 User Manual Figure 15-11. Repetition counter timing chart of down counting mode TIMER_CK CNT_CLK CNT_REG …. …. …. …. …. Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Capture/compare channels The advanced timer has four independent channels which can be used as capture inputs or compare outputs. -
Page 234: Figure 15-12. Input Capture Logic
GD32VF103 User Manual Figure 15-12. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal... -
Page 235: Figure 15-13. Output Compare Logic (With Complementary Output, X=0,1,2)
GD32VF103 User Manual Direct generation: A DMA request or interrupt is generated by setting CHxG directly. The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connects to CI0 input. Select CI0 as channel 0 capture signals by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) -
Page 236: Figure 15-15. Output-Compare In Three Modes
GD32VF103 User Manual 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(high) level. -
Page 237: Figure 15-16. Timing Chart Of Eapwm
GD32VF103 User Manual Figure 15-15. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL bit to 3’b110 (PWM mode 0) or to 3’b 111(PWM mode 1)), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers. -
Page 238: Figure 15-17. Timing Chart Of Capwm
GD32VF103 User Manual Figure 15-16. Timing chart of EAPWM Figure 15-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF... - Page 239 GD32VF103 User Manual has several types of output function. These include keeping the original level by configuring the CHxCOMCTL field to 0x00, setting to high by configuring the CHxCOMCTL field to 0x01, setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
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Page 240: Table 15-2. Complementary Outputs Controlled By Parameters
GD32VF103 User Manual Table 15-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable:... -
Page 241: Figure 15-18. Complementary Output With Dead Time Insertion
GD32VF103 User Manual Dead time insertion The dead time insertion is enabled when both CHxEN and CHxNEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels except channel 3. Refer to the TIMERx_CCHP register for details about the delay time. -
Page 242: Figure 15-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32VF103 User Manual (CKM) in RCU. The break function is enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is configured by the BRKP bit in TIMERx_CCHP register. When a break occurs, the POEN bit is cleared asynchronously. As soon as POEN is 0, the level of the CHx_O and CHx_ON outputs are determined by the ISOx and ISOxN bits in the TIMERx_CTL1 register. -
Page 243: Figure 15-20. Example Of Counter Operation In Encoder Interface Mode
GD32VF103 User Manual before the counter starts to count. Table 15-3. Counting direction versus encoder signals CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling CI1FE1=High Down CI0 only counting CI1FE1=Low Down CI1 only CI0FE0=High Down counting CI0FE0=Low Down CI1FE1=High... -
Page 244: Figure 15-22. Hall Sensor Is Used To Bldc Motor
GD32VF103 User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 15-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in（Advanced/GeneralL0 TIMER） should accept three Rotor Position signals from Motor. -
Page 245: Figure 15-23. Hall Sensor Timing Between Two Timers
GD32VF103 User Manual Figure 15-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Slave controller... -
Page 246: Figure 15-24. Restart Mode
GD32VF103 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 110: CI1FE1 If ETIFP is selected as For the ETIFP, filter can 111: ETIFP the trigger source, be used by configuring configure the ETP for ETFC and prescaler... -
Page 247: Figure 15-26. Event Mode
GD32VF103 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event mode ETPSC = 1, ETI is The counter will start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. to count when a of ETI does not ETIFP is selected. -
Page 248: Figure 15-27. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
GD32VF103 User Manual Figure 15-27. Single pulse mode TIMERx_CHxCV=0x04, TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, count er stop CNT_REG …. O2CPRE Timers interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode. -
Page 249: Figure 15-29. Triggering Timer0 With Enable Signal Of Timer2
GD32VF103 User Manual We configure TIMER2 as a prescaler for TIMER0. Refer to Figure 15-28. TIMER0 Master/Slave mode timer example for connections. Do as follow: 1. Configure TIMER2 in master mode and select its update event (UPE) as trigger output (MMC=3’b010 in the TIMER2_CTL1 register). -
Page 250: Figure 15-30. Triggering Timer0 With Update Signal Of Timer2
GD32VF103 User Manual 2. Configure the Timer2 period (TIMER2_CARL registers). 3. Configure TIMER0 to get the input trigger from Timer2 (TRGS=3’b010 in the TIMER0_SMCFG register). 4. Configure TIMER0 in event mode (SMC=3’b110 in TIMERx_SMCFG register). 5. Start TIMER2 by writing ‘1 in the CEN bit (TIMER2_CTL0 register). -
Page 251: Figure 15-31. Pause Timer0 With Enable Signal Of Timer2
GD32VF103 User Manual Figure 15-31. Pause TIMER0 with enable signal of TIMER2 TIMER_CK TIMER2_CEN TIMER2_CNT_REG TIMER0_TRGIF TIMER0_CNT_REG In this example, we also can use O0CPRE as trigger source instead of enable signal output. Do as follow: 1. Configure TIMER2 in master mode and output compare 0 prepare signal (O0CPRE) as trigger output (MMS=3’b100 in the TIMER2_CTL1 register). -
Page 252: Figure 15-33. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32VF103 User Manual 3. Configure the TIMER2 in Master/Slave mode by writing MSM=1 (TIMER2_SMCFG register). 4. Configure TIMER0 to get the input trigger from TIMER2 (TRGS=3’b010 in the TIMER0_SMCFG register). 5. Configure TIMER0 in event mode (SMC=3’b110 in the TIMER0_SMCFG register). - Page 253 GD32VF103 User Manual request will be sent by TIMERx. If one more DMA request event occurs, TIMERx will repeat the process above. Timer debug mode When the RISC-V core halted, and the TIMERx_HOLD configuration bit in DBG_CTL register is set to 1, the TIMERx counter stops.
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Page 254: Timerx Registers(X=0)
GD32VF103 User Manual 15.1.5. TIMERx registers(x=0) TIMER0 base address: 0x4001 2C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions... - Page 255 GD32VF103 User Manual After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down This bit is read only when the timer is configured in center-aligned mode or encoder mode. Single pulse mode.
- Page 256 GD32VF103 User Manual Bits Fields Descriptions Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit ISO2 Idle state of channel 2 output...
- Page 257 GD32VF103 User Manual 010: Update. In this mode the master mode controller selects the update event as TRGO. 011: Capture/compare pulse. In this mode the master mode controller generates a TRGO pulse when a capture or a compare match occurred in channal0.
- Page 258 GD32VF103 User Manual Bits Fields Descriptions External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge. 1: ETI is active at low level or falling edge. SMC1 Part of SMC for enable External clock mode1.
- Page 259 GD32VF103 User Manual 1111: f /32, N=8. SAMP Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
- Page 260 GD32VF103 User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TRGDEN CMTDEN CH3DEN CH2DEN CH1DEN CH0DEN UPDEN BRKIE TRGIE CMTIE CH3IE CH2IE CH1IE CH0IE UPIE Bits Fields Descriptions Reserved Must be kept at reset value.
- Page 261 GD32VF103 User Manual 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable...
- Page 262 GD32VF103 User Manual Reserved Must be kept at reset value. BRKIF Break interrupt flag This flag is set by hardware when the break input goes active, and cleared by software if the break input is not active. 0: No active level break has been detected.
- Page 263 GD32VF103 User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G Bits Fields Descriptions 15:8 Reserved Must be kept at reset value. BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
- Page 264 GD32VF103 User Manual 1: Generate a channel 1 capture or compare event Update event generation This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
- Page 265 GD32VF103 User Manual CH0COMCEN Channel 0 output compare clear enable. When this bit is set, the O0CPRE signal is cleared when High level is detected on ETIF input. 0: Channel 0 output compare clear disable 1: Channel 0 output compare clear enable...
- Page 266 GD32VF103 User Manual PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison. 0: Channel 0 output quickly compare disable. The minimum delay from an edge on the trigger input to activate CH0_O output is 5 clock cycles.
- Page 267 GD32VF103 User Manual 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
- Page 268 GD32VF103 User Manual 00: Channel 3 is configured as output 01: Channel 3 is configured as input, IS3 is connected to CI3FE3 10: Channel 3 is configured as input, IS3 is connected to CI2FE3 11: Channel 3 is configured as input, IS3 is connected to ITS, This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register.
- Page 269 GD32VF103 User Manual The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set). This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00.
- Page 270 GD32VF103 User Manual 0100: f /2, N=6 SAMP 0101: f /2, N=8 SAMP 0110: f /4, N=6 SAMP 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f...
- Page 271 GD32VF103 User Manual CH2NEN Channel 2 complementary output enable Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description...
- Page 272 GD32VF103 User Manual When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0. 0: Channel 0 disabled...
- Page 273 GD32VF103 User Manual CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value.
- Page 274 GD32VF103 User Manual When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Channel 1 capture/compare value register (TIMERx_CH1CV)
- Page 275 GD32VF103 User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH3VAL[15:0] Bits Fields Descriptions 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
- Page 276 GD32VF103 User Manual This bit specifies the polarity of the BRKIN input signal. 0: BRKIN input active low 1; BRKIN input active high BRKEN Break enable This bit can be set to enable the BRKIN and CKM clock failure event inputs.
- Page 277 GD32VF103 User Manual This bit-field controls the value of the dead-time, which is inserted before the output transitions. The relationship between DTCFG value and the duration of dead-time is as follow: DTCFG [7:5] =3’b0xx: DTvalue = DTCFG [7:0] x t DTCFG [7:5] =3’b10x: DTvalue = (64+DTCFG [5:0]) x t...
- Page 278 GD32VF103 User Manual DMA transfer buffer register (TIMERx_DMATB) Address offset: 0x4C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) DMATB[15:0] Bits Fields Descriptions 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed.
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Page 279: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32VF103 User Manual 15.2. General level0 timer (TIMERx, x=1, 2, 3, 4) 15.2.1. Overview The general level0 timer module (TIMER1, 2, 3, 4) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. -
Page 280: Function Overview
GD32VF103 User Manual Figure 15-34. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 TIMERx_CHxCV CK_TIMER Counter External Trigger Trigger processor Input logic PSC_CLK Trigger Selector&Counter Polarity selection... -
Page 281: Figure 15-35. Normal Mode, Internal Clock Divided By 1
GD32VF103 User Manual Figure 15-35. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock ... -
Page 282: Figure 15-36. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32VF103 User Manual Figure 15-36. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction. - Page 283 GD32VF103 User Manual Figure 15-37. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF)
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Page 284: Figure 15-38. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32VF103 User Manual Figure 15-38. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) -
Page 285: Figure 15-39. Timing Chart Of Down Counting Mode, Psc=0/1
GD32VF103 User Manual Figure 15-39. Timing chart of down counting mode, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG 5C 5B Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear... -
Page 286: Figure 15-40. Timing Chart Of Down Counting Mode, Change Timerx_Car
GD32VF103 User Manual Figure 15-40. Timing chart of down counting mode, change TIMERx_CAR. TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) -
Page 287: Figure 15-41. Timing Chart Of Center-Aligned Counting Mode
GD32VF103 User Manual When an update event occurs, all the registers (auto-reload register, prescaler register) are updated. Figure 15-41. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 15-41. Timing chart of center-aligned counting mode... -
Page 288: Figure 15-42. Input Capture Logic
GD32VF103 User Manual the channel input, the current value of the counter is captured into the TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is generated if it is enabled when CHxIE=1. Figure 15-42. Input capture logic... - Page 289 GD32VF103 User Manual When the wanted input signal is captured, TIMERx_CHxCV will be set by counter’s Result: value and CHxIF is asserted. If the CHxIF is 1, the CHxOF will also be asserted. The interrupt and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN.
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Page 290: Figure 15-43. Output-Compare In Three Modes
GD32VF103 User Manual Figure 15-43. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL bit to 3’b110 (PWM mode 0) or to 3’b 111(PWM mode 1)), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers. - Page 291 GD32VF103 User Manual Figure 15-44. EAPWM timechart Figure 15-45. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
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Page 292: Table 15-5. Counting Direction Versus Encoder Signals
GD32VF103 User Manual 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content. -
Page 293: Figure 15-46. Example Of Counter Operation In Encoder Interface Mode
GD32VF103 User Manual Figure 15-46. Example of counter operation in encoder interface mode Counter down Figure 15-47. Example of encoder interface mode with CI0FE0 polarity inverted Counter down Hall sensor function Advanced timer (TIMERx, x=0) Refer to Slave controller The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode which is selected by the SMC[2:0] bits in the TIMERx_SMCFG register. -
Page 294: Figure 15-48. Restart Mode
GD32VF103 User Manual Table . Slave controller examples Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC[2:0] TRGS[2:0] If you choose the For the ITIx no filter 3'b100 (restart 000: ITI0 CI0FE0 or CI1FE1, and prescaler can be... -
Page 295: Figure 15-49. Pause Mode
GD32VF103 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 15-49. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF TRGS[2:0]=3’b111 Exam3 Event mode ETP = 0 no polarity ETPSC = 1, divided by The counter will ETIF is the change. -
Page 296: Figure 15-51. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32VF103 User Manual rising occurs in the single pulse mode, the OxCPRE signal will immediately be forced to the state which the OxCPRE signal will change to, as the compare match event occurs without taking the comparison result into account. The CHxCOMFEN bit is available only when the output channel is configured to the PWM mode 0 or PWM mode 1 and the trigger source is derived from the trigger signal. -
Page 297: Timerx Registers(X=1,2,3,4)
GD32VF103 User Manual 15.2.5. TIMERx registers(x=1,2,3,4) TIMER1 base address: 0x40000000 TIMER2 base address: 0x40000400 TIMER3 base address: 0x40000800 TIMER4 base address: 0x40000C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) - Page 298 GD32VF103 User Manual center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when the counter is counting up and counting down, compare interrupt flag of channels can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00.
- Page 299 GD32VF103 User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 15:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input.
- Page 300 GD32VF103 User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge.
- Page 301 GD32VF103 User Manual 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8. SAMP 1010: f /16, N=5. SAMP 1011: f /16, N=6. SAMP 1100: f /16, N=8.
- Page 302 GD32VF103 User Manual disables the counter when it is low. 110: Event mode. A rising edge of the trigger input enables the counter. The counter cannot be disabled by the slave mode controller. 111: External clock mode0. The counter counts on the rising edges of the selected trigger.
- Page 303 GD32VF103 User Manual 0: disabled 1: enabled Reserved Must be kept at reset value. CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled CH1IE Channel 1 capture/compare interrupt enable...
- Page 304 GD32VF103 User Manual When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software. 0: No over capture interrupt occurred...
- Page 305 GD32VF103 User Manual Reserved TRGG Reserved CH3G CH2G CH1G CH0G Bits Fields Descriptions 15:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
- Page 306 GD32VF103 User Manual CH1COM CH1COMCTL[2:0] CH1COM CH1COM CH1MS[1:0] CH0COM CH0COMCTL[2:0] CH0COM CH0COM CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
- Page 307 GD32VF103 User Manual 011: Toggle on match. O0CPRE toggles when the counter matches the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced low level. 101: Force high. O0CPRE is forced high level. 110: PWM mode0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV else inactive.
- Page 308 GD32VF103 User Manual only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler...
- Page 309 GD32VF103 User Manual Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH3COM CH3COMCTL[2:0] CH3COM CH3COM CH3MS[1:0] CH2COM CH2COMCTL[2:0] CH2COM CH2COM CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode:...
- Page 310 GD32VF103 User Manual comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT. 001: Set the channel output. O2CPRE signal is forced high when the counter matches the output compare register TIMERx_CH2CV. 010: Clear the channel output. O2CPRE signal is forced low when the counter matches the output compare register TIMERx_CH2CV.
- Page 311 GD32VF103 User Manual This bit-field is writable only when the channel is not active. (CH2EN bit in TIMERx_CHCTL2 register is reset).). 00: Channel 2 is configured as output 01: Channel 2 is configured as input, IS2 is connected to CI2FE2 10: Channel 2 is configured as input, IS2 is connected to CI3FE2 11: Channel 2 is configured as input, IS2 is connected to ITS.
- Page 312 GD32VF103 User Manual 01: Capture is done every 2 channel input edges 10: Capture is done every 4 channel input edges 11: Capture is done every 8 channel input edges CH2MS[1:0] Channel 2 mode selection Same as output compare mode...
- Page 313 GD32VF103 User Manual When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. 0: CI0 is non-inverted. Input capture is done on a rising edge of CI0. When used as extern trigger, CI0 is non-inverted.
- Page 314 GD32VF103 User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
- Page 315 GD32VF103 User Manual CH1VAL[15:0] Bits Fields Descriptions 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only.
- Page 316 GD32VF103 User Manual corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event.
- Page 317 GD32VF103 User Manual DMATB[15:0] Bits Fields Descriptions 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
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Page 318: Basic Timer (Timerx, X=5, 6)
GD32VF103 User Manual 15.3. Basic timer (TIMERx, x=5, 6) 15.3.1. Overview The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC. -
Page 319: Figure 15-53. Normal Mode, Internal Clock Divided By 1
GD32VF103 User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 15-53. Normal mode, internal clock divided by 1... -
Page 320: Figure 15-54. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32VF103 User Manual Figure 15-54. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB FC CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. - Page 321 GD32VF103 User Manual Figure 15-55. Timing chart of up counting mode, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set...
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Page 322: Figure 15-56. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32VF103 User Manual Figure 15-56. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) -
Page 323: Timerx Registers(X=5,6)
GD32VF103 User Manual 15.3.5. TIMERx registers(x=5,6) TIMER5 base address: 0x40001000 TIMER6 base address: 0x40001400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ARSE Reserved UPDIS Bits... - Page 324 GD32VF103 User Manual The slave mode controller generates an update event. 1: update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UG bit is set or if the slave mode controller generates a hardware reset event.
- Page 325 GD32VF103 User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved UPDEN Reserved UPIE Bits Fields Descriptions 15:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value.
- Page 326 GD32VF103 User Manual Reserved Bits Fields Descriptions 15:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared. The prescaler counter is cleared at the same time.
- Page 327 GD32VF103 User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
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Page 328: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32VF103 User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 16.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the peripheral clock (PCLK1 or PCLK2) to produce a dedicated baud rate lock for the USART transmitter and receiver. -
Page 329: Function Overview
GD32VF103 User Manual Multiprocessor communication – Enter into mute mode if address match does not occur – Wake up from mute mode by idle frame or address match detection Various status flags: – Flags for transfer detection: Receive buffer not empty (RBNE), Transmit buffer empty (TBE), transfer complete (TC). -
Page 330: Usart Frame Format
GD32VF103 User Manual Figure 16-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address... -
Page 331: Baud Rate Generation
GD32VF103 User Manual STB[1:0] stop bit length (bit) usage description normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame. -
Page 332: Figure 16-3. Usart Transmit Procedure
GD32VF103 User Manual the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_DATA when the TBE bit of the USART_STAT register is asserted. The TBE bit is cleared by writing to the USART_DATA register and it is set by hardware after the data is put into the transmit shift register. -
Page 333: Usart Receiver
GD32VF103 User Manual 16.3.4. USART receiver After power on, the USART receiver can be enabled by the follow procedure: Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1. Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. -
Page 334: Use Dma For Data Buffer Access
GD32VF103 User Manual register will be set. An interrupt is generated, If the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set. When a frame is received, if the RBNE bit is not cleared yet, the last frame will not be stored in the receive data buffer. -
Page 335: Hardware Flow Control
GD32VF103 User Manual After all of the data frames are transmitted, the TC bit in USART_STAT is set. An interrupt occurs if the TCIE bit in USART_CTL0 is set. When DMA is used for USART reception, DMA transfers data from the receive data buffer of the USART to the internal SRAM. -
Page 336: Multi-Processor Communication
GD32VF103 User Manual Figure 16-7. Hardware flow control between two USARTs TX module RX module nCTS nRTS USART 1 USART 2 RX module nRTS nCTS TX module RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. -
Page 337: Lin Mode
GD32VF103 User Manual big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, software can put an USART module into a mute mode by setting the RWU bit in USART_CTL0 register. -
Page 338: Synchronous Mode
GD32VF103 User Manual Figure 16-9. Break frame occurs during idle state As shown in Figure 16-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame. -
Page 339: Irda Sir Endec Mode
GD32VF103 User Manual Figure 16-11. Example of USART in synchronous mode Data output Data input USART Device (master mode) (slave mode) Clock input Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1) Idle frame data (8-bit) Idle CK pin (CPL=0, CPH=0) -
Page 340: Figure 16-13. Irda Sir Endec Module
GD32VF103 User Manual Figure 16-13. IrDA SIR ENDEC module inside chip outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX pin and RX pin is different. The TX pin is usually at low state, while the RX pin is usually at high state. -
Page 341: Half-Duplex Communication Mode
GD32VF103 User Manual 16.3.11. Half-duplex communication mode The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. In the half-duplex mode the receive line is internally connected to the TX pin, and the RX pin is no longer used. -
Page 342: Usart Interrupts
GD32VF103 User Manual protocol minus 12. The TC status is forced reset while the guard time counter is counting up. When the counter reaches the programmed value TC is asserted high. During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits. -
Page 343: Figure 16-16. Usart Interrupt Mapping Diagram
GD32VF103 User Manual Figure 16-16. USART interrupt mapping diagram IDLEF IDLEIE ORERR RBNEIE PERR PEIE FERR NERR ERIE ORERR DENR LBDF LBDIE USART_INT RBNE RBNEIE TCIE TBEIE CTSF CTSIE RTIE EBIE... -
Page 344: Register Definition
GD32VF103 User Manual 16.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 16.4.1. Status register (USART_STAT) Address offset: 0x00 Reset value: 0x0000 00C0... - Page 345 GD32VF103 User Manual 0: Transmit data buffer is not empty 1: Transmit data buffer is empty Transmission complete This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
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Page 346: Data Register (Usart_Data)
GD32VF103 User Manual frame. An interrupt occurs if the ERRIE bit in USART_CTL2 is set. Software can clear this bit by reading the USART_STAT and USART_DATA registers one by one. 0: The USART does not detect a framing error 1: The USART has detected a framing error... -
Page 347: Control Register 0 (Usart_Ctl0)
GD32VF103 User Manual Reserved INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value 15:4 INTDIV[11:0] Integer part of baud-rate divider FRADIV[3:0] Fraction part of baud-rate divider 16.4.4. Control register 0 (USART_CTL0) Address offset: 0x0C Reset value: 0x0000 0000... - Page 348 GD32VF103 User Manual 0: Even parity 1: Odd parity PERRIE Parity error interrupt enable If this bit is set, an interrupt occurs when the PERR bit in USART_STAT is set. 0: Parity error interrupt is disabled 1: Parity error interrupt is enabled...
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Page 349: Control Register 1 (Usart_Ctl1)
GD32VF103 User Manual SBKCMD Send break command Software can set this bit to send a break frame. Hardware clears this bit automatically when the break frame has been transmitted. 0: Do not transmit a break frame 1: Transmit a break frame 16.4.5. -
Page 350: Control Register 2 (Usart_Ctl2)
GD32VF103 User Manual This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4. CK phase This bit specifies the phase of the CK pin in synchronous mode. 0: The capture edge of the LSB bit is the first edge of CK pin 1: The capture edge of the LSB bit is the second edge of CK pin This bit field cannot be written when the USART is enabled (UEN=1). - Page 351 GD32VF103 User Manual Reserved CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields Descriptions 31:11 Reserved Must be kept the reset value CTSIE CTS interrupt enable If this bit is set, an interrupt occurs when the CTSF bit in USART_STAT is set.
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Page 352: Guard Time And Prescaler Register (Usart_Gp)
GD32VF103 User Manual 0: Disable NACK transmission 1: Enable NACK transmission This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4. HDEN Half-duplex enable This bit enables the half-duplex USART mode. 0: Half duplex mode is disabled 1: Half duplex mode is enabled This bit field cannot be written when the USART is enabled (UEN=1). - Page 353 GD32VF103 User Manual 15:8 GUAT[7:0] Guard time value in Smartcard mode TC flag assertion time is delayed by GUAT[7:0] baud clock cycles. This bit field cannot be written when the USART is enabled (UEN=1). These bits are reserved for UART3/4.
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Page 354: Inter-Integrated Circuit Interface (I2C)
GD32VF103 User Manual Inter-integrated circuit interface (I2C) 17.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. -
Page 355: Sda And Scl Lines
GD32VF103 User Manual Figure 17-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register Control Registers Timing and SMBA Control Logic Status Flags DMA/ Interrupts Table 17-1. Definition of I2C-bus terminology (refer to the I2C specification of philips... -
Page 356: Data Validation
GD32VF103 User Manual devices connected to the bus must have an open-drain or open-collect to perform the wired- AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the standard-mode and up to 400 kbit/s in the fast-mode. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’... -
Page 357: Arbitration
GD32VF103 User Manual Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line causes the masters concerned to start counting off their LOW period and, once a master clock has gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see Figure 17-4. -
Page 358: Programming Model
GD32VF103 User Manual on the function of the device. An I2C slave will continue to detect addresses after a START condition on I2C bus and compare the detected address with its slave address which is programmable by software. Once the two addresses match, the I2C slave will send an ACK to the I2C bus and responses to the following command on I2C bus: transmitting or receiving the desired data. - Page 359 GD32VF103 User Manual programmed by software and finished sending a START condition on I2C bus, it changes into master mode. The I2C changes back to slave mode after it’s programmed by software and finished sending a STOP condition on I2C bus.
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Page 360: Figure 17-9. Programming Model For Slave Transmitting(10-Bit Address Mode)
GD32VF103 User Manual Figure 17-9. Programming model for slave transmitting(10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND... - Page 361 GD32VF103 User Manual then I2C_STAT1 to clear ADDSEND bit. The I2C begins to receive data to I2C bus as soon as ADDSEND bit is cleared. As soon as the first byte is received, RBNE is set by hardware. Software can now read the first byte from I2C_DATA and RBNE is cleared as well.
- Page 362 GD32VF103 User Manual Software set START bit requesting I2C to generate a START condition to I2C bus. After sending a START condition, the I2C hardware sets the SBSEND bit in I2C status register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA.
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Page 363: Figure 17-11. Programming Model For Master Transmitting(10-Bit Address Mode)
GD32VF103 User Manual Figure 17-11. Programming model for master transmitting(10-bit address mode) I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header... - Page 364 GD32VF103 User Manual Software set START bit requesting I2C to generate a START condition to I2C bus. After sending a START condition, the I2C hardware sets the SBSEND bit in I2C status register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA.
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Page 365: Figure 17-12. Programming Model For Master Receiving Using Solution A(10-Bit Address Mode)
GD32VF103 User Manual Figure 17-12. Programming model for master receiving using Solution A(10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header... - Page 366 GD32VF103 User Manual I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address sent is a header of 10-bit address, the hardware sets ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address toI2C_DATA.
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Page 367: Scl Line Stretching
GD32VF103 User Manual Figure 17-13. Programming model for master receiving using solution B(10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND... -
Page 368: Use Dma For Data Transfer
GD32VF103 User Manual filled with the next transmit data. When the RBNE and BTC bit of a receiver is set, the receiver stretches the SCL line low until the data in the transfer buffer is read out. When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. - Page 369 GD32VF103 User Manual I2C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transaction on SMBus follows the format of one of the defined SMBus protocols.
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Page 370: Status, Errors And Interrupts
GD32VF103 User Manual used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications but passing more data and building on the I2C multi-master mode. -
Page 371: Register Definition
GD32VF103 User Manual 17.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 17.4.1. Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) PECTRA SRESET Reserved... - Page 372 GD32VF103 User Manual ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent STOP Generate a STOP condition on I2C bus This bit is set and cleared by software and set by hardware when SMBUs timeout and cleared by hardware when STOP condition detected.
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Page 373: Control Register 1 (I2C_Ctl1)
GD32VF103 User Manual 17.4.2. Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word (32-bit) Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[5:0] Bits Fields Descriptions 15:13 Reserved Must be kept the reset value. -
Page 374: Slave Address Register 0 (I2C_Saddr0)
GD32VF103 User Manual 8MHz. 17.4.3. Slave address register 0 (I2C_SADDR0) Address offset: 0x08 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) ADDFOR ADDRES Reserved ADDRESS[9:8] ADDRESS[7:1] Bits Fields Descriptions ADDFORMAT Address mode for the I2C slave... -
Page 375: Transfer Buffer Register (I2C_Data)
GD32VF103 User Manual 17.4.5. Transfer buffer register (I2C_DATA) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TRB[7:0] Bits Fields Descriptions 15:8 Reserved Must be kept the reset value. TRB[7:0] Transmission or reception data buffer 17.4.6. - Page 376 GD32VF103 User Manual ACKEN bit. OUERR Over-run or under-run situation occurs in slave mode, when SCL stretching is disabled. In slave receiving mode, if the last byte in I2C_DATA is not read out while the following byte is already received, over-run occurs. In slave transmitting mode, if the current byte is already sent out, while the I2C_DATA is still empty, under-run occurs.
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Page 377: Transfer Status Register 1 (I2C_Stat1)
GD32VF103 User Manual 1: STOP condition detected in slave mode ADD10SEND Header of 10-bit address is sent in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA. 0: No header of 10-bit address sent in master mode 1: Header of 10-bit address is sent in master mode Byte transmission completed. -
Page 378: Clock Configure Register (I2C_Ckcfg)
GD32VF103 User Manual DUMODF Dual Flag in slave mode indicating which address is matched in Dual-Address mode This bit is cleared by hardware after a STOP or a START condition or I2CEN=0 0: SADDR0 address matches 1: SADDR1 address matches... -
Page 379: Rise Time Register (I2C_Rt)
GD32VF103 User Manual FAST DTCY Reserved CLKC[11:0] Bits Fields Descriptions FAST I2C speed selection in master mode 0: Standard speed 1: Fast speed DTCY Duty cycle in fast mode 0: T high 1: T = 16/9 high 13:12 Reserved Must be kept the reset value. -
Page 380: Serial Peripheral Interface/Inter-Ic Sound (Spi/I2S)
GD32VF103 User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 18.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode. -
Page 381: Spi Block Diagram
GD32VF103 User Manual 18.3. SPI block diagram Figure 18-1. Block diagram of SPI SYSCLK MOSI TX Buffer MISO RX Buffer 18.4. SPI signal description 18.4.1. Normal configuration Table 18-1. SPI signal description Pin name Direction Description Master: SPI clock output... -
Page 382: Spi Function Overview
GD32VF103 User Manual 18.5. SPI function overview 18.5.1. SPI clock timing and data format CKPL and CKPH bits in SPI_CTL0 register decide the timing of SPI clock and data signal. The CKPL bit decides the SCK level when idle and CKPH bit decides either first or second clock edge is a valid sampling edge. -
Page 383: Spi Operating Modes
GD32VF103 User Manual and goes low when transmission or reception process begins. When SPI is disabled, the NSS goes high. The application may also use a general purpose IO as NSS pin to realize more flexible NSS. 18.5.3. SPI operating modes Table 18-2. -
Page 384: Figure 18-3. A Typical Full-Duplex Connection
GD32VF103 User Manual Mode Description Register configuration Data pin usage BDEN = 1 BDOEN = 1 MSTMOD = 0 Slave reception with RO = 0 MOSI: Not used bidirectional connection BDEN = 1 MISO: Reception BDOEN = 0 Figure 18-3. A typical full-duplex connection... -
Page 385: Figure 18-6. A Typical Bidirectional Connection
GD32VF103 User Manual Figure 18-6. A typical bidirectional connection Master Slave MTB/MRB SRB/STB MISO MISO MOSI MOSI SPI initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate, or configure the Td time in TI mode, otherwise, ignore this step. -
Page 386: Figure 18-7. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32VF103 User Manual In master mode, software should write the next data into SPI_DATA register before the transmission of current data frame is completed if it desires to generate continuous transmission. Reception sequence After the last valid sample clock, the incoming data will be moved from shift register to the receive buffer and RBNE (receive buffer not empty) will be set. -
Page 387: Figure 18-8. Timing Diagram Of Ti Master Mode With Continuous Transfer
GD32VF103 User Manual Figure . Timing diagram of TI master mode with continuous transfer In master TI mode, SPI can perform continuous or non-continuous transfer. If the master writes SPI_DATA register fast enough, the transfer is continuous, otherwise non-continuous. In non-continuous transfer, there is an extra header clock cycle before each byte. While in continuous transfer, the extra header clock cycle only exists before the first byte and the following bytes’... -
Page 388: Figure 18-10. Timing Diagram Of Nss Pulse With Continuous Transmission
GD32VF103 User Manual NSS pulse mode operation sequence This function is controlled by NSSP bit in SPI_CTL1 register. In order to implement this function, several additional conditions must be met: configure the device to master mode, frame format should follow the normal SPI protocol, select the first clock transition as the data capture edge. -
Page 389: Dma Function
GD32VF103 User Manual TI mode The disabling sequence of TI mode is the same as the sequences described above. NSS pulse mode The disabling sequence of NSSP mode is the same as the sequences described above. 18.5.4. DMA function The DMA frees the application from data writing and reading process during transfer, to improve the system efficiency. -
Page 390: Error Flags
GD32VF103 User Manual This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register. Receive buffer not empty flag (RBNE) This bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register. -
Page 391: I2S Block Diagram
GD32VF103 User Manual Interrupt Flag Description Clear method enable bit Read or write SPI_STAT register, CONFERR Configuration fault error then write SPI_CTL0 register. Read SPI_DATA register, then RXORERR Rx overrun error ERRIE read SPI_STAT register. CRCERR CRC error Write 0 to CRCERR bit... -
Page 392: I2S Function Overview
GD32VF103 User Manual 18.9. I2S function overview 18.9.1. I2S audio standards The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time-multiplexedly on two channels (the left channel and the right channel). -
Page 393: Figure 18-14. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32VF103 User Manual the transmission of to or from the SPI_DATA register is needed to complete a frame. 14 . I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data... -
Page 394: Figure 18-18. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32VF103 User Manual Figure 18-18. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD Figure 18-19. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) -
Page 395: Figure 18-23. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32VF103 User Manual Figure . MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure . MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) -
Page 396: Figure 18-28. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32VF103 User Manual Figure 18-28. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 8-bit 0 24-bit data I2S_SD Figure 18-29. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) -
Page 397: Figure 18-32. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32VF103 User Manual configurable using the PCMSMOD bit in the SPI_I2SCTL register. The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard. The timing diagrams for each configuration of the short frame synchronization mode are shown below. -
Page 398: Figure 18-40. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32VF103 User Manual (DTLEN=01, CHLEN=1, CKPL=1) Figure . PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure . PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 16-bit data 16-bit 0 The timing diagrams for each configuration of the long frame synchronization mode are shown below. -
Page 399: Figure 18-41. Pcm Standard Long Frame Synchronization Mode Timing Diagram
GD32VF103 User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure . PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure . PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 24-bit data... -
Page 400: I2S Clock
GD32VF103 User Manual 18.9.2. I2S clock Figure . Block diagram of I2S clock generator 8-bit I2SCLK Configurable MCKOEN Divider DIV4 CHLEN frequency dividing ratio = DIV * 2 + OF I2S_CK DIV2 MCKOEN The block diagram of I2S clock generator is shown as Figure 18-48. -
Page 401: Operation
GD32VF103 User Manual 18.9.3. Operation Operation modes The operation mode is selected by the I2SOPMOD bits in the SPI_I2SCTL register. There are four available operation modes, including master transmission mode, master reception mode, slave transmission mode, and slave reception mode. The direction of I2S interface signals for each operation mode is shown in the Table 18-6. - Page 402 GD32VF103 User Manual to the SPI_DATA register (TBE goes low), the data is transferred from the transmit buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins. The data is parallel loaded into the 16-bit shift register, and shifted out serially to the I2S_SD pin, MSB first.
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Page 403: Dma Function
GD32VF103 User Manual 16-bit data packed in 32-bit frame in the audio standards except the LSB justified standard (DTLEN = 00, CHLEN = 1, and I2SSTD is not equal to 0b10) 1. Wait for the last RBNE. 2. Then wait one I2S clock cycle. -
Page 404: I2S Interrupts
GD32VF103 User Manual 18.10. I2S interrupts 18.10.1. Status flags There are four status flags implemented in the SPI_STAT register, including TBE, RBNE, TRANS and I2SCH. The user can use them to fully monitor the state of the I2S bus. ... -
Page 405: Table 18-7. I2S Interrupt
GD32VF103 User Manual Table 18-7. I2S interrupt Interrupt Interrupt flag Description Clear method enable bit Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA register RBNEIE TXURERR Transmission underrun error Read SPI_STAT register Read SPI_DATA register and... -
Page 406: Register Definition
GD32VF103 User Manual 18.11. Register definition SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 18.11.1. Control register 0 (SPI_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). - Page 407 GD32VF103 User Manual SPI_DATA register. In receive-only mode, set this bit after the second last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only mode When BDEN is cleared, this bit determines the direction of transfer.
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Page 408: Control Register 1 (Spi_Ctl1)
GD32VF103 User Manual CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle 1: CLK pin is pulled high when SPI is idle CKPH Clock phase selection 0: Capture the first data at the first clock transition 1: Capture the first data at the second clock transition 18.11.2. -
Page 409: Status Register (Spi_Stat)
GD32VF103 User Manual 1: NSS output is enabled. If the NSS pin is configured as output, the NSS pin is pulled low in master mode when SPI is enabled. If the NSS pin is configured as input, the NSS pin should be pulled high in master mode, and this bit has no effect. -
Page 410: Data Register (Spi_Data)
GD32VF103 User Manual RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register. -
Page 411: Crc Polynomial Register (Spi_Crcpoly)
GD32VF103 User Manual Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardware has two buffers, including transmit buffer and receive buffer. Write data to SPI_DATA will save the data to transmit buffer and read data from SPI_DATA will get the data from receive buffer. -
Page 412: Tx Crc Register (Spi_Tcrc)
GD32VF103 User Manual This register can be accessed by half-word (16-bit) or word (32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the received bytes and saves them in RCRC register. -
Page 413: I2S Control Register (Spi_I2Sctl)
GD32VF103 User Manual The hardware computes the CRC value after each transmitted bit, when the TRANS is set, a read to this register could return an intermediate value. The different frame formats (LF bit of the SPI_CTL0) will get different CRC values. -
Page 414: I2S Clock Prescaler Register (Spi_I2Spsc)
GD32VF103 User Manual This bit should be configured when I2S is disabled. This bit is not used in SPI mode. Reserved Must be kept at reset value. I2SSTD[1:0] I2S standard selection 00: I2S Phillips standard 01: MSB justified standard 10: LSB justified standard 11: PCM standard These bits should be configured when I2S is disabled. - Page 415 GD32VF103 User Manual Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: I2S_MCK output is disabled 1: I2S_MCK output is enabled This bit should be configured when I2S is disabled. This bit is not used in SPI mode.
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Page 416: External Memory Controller (Exmc)
GD32VF103 User Manual External memory controller (EXMC) 19.1. Overview The external memory controller EXMC, is used as a translator for MCU to access a variety of external memory, it automatically converts AMBA memory access protocol into a specific memory access protocol defined in the configuration register, such as SRAM, ROM and NOR Flash. -
Page 417: Basic Regulation Of Exmc Access
GD32VF103 User Manual Figure 19-1. The EXMC block diagram AHB Bus Interface HCLK from clock controller EXMC Configuration Register NOR-Flash/PSRAM Controller Shared PSRAM NOR/PSRAM NOR/PSRAM Pins Pins Pins Shared Pin 19.3.2. Basic regulation of EXMC access EXMC is the conversion interface between AHB bus and external device protocol. 32-bit of AHB read/write accesses can be split into several consecutive 8-bit or 16-bit read/write operations respectively. -
Page 418: External Device Address Mapping
GD32VF103 User Manual 19.3.3. External device address mapping Figure 19-2. EXMC memory banks Address Banks Supported memory type 0x6000 0000 NOR/PSRAM Bank0(4x64M) 0x6FFF FFFF EXMC access space is divided into one bank. Bank0 is 4*64 Mbytes. The first bank (Bank0) is further divided into 4 Regions, which is 64 Mbytes (only Bank0 Region0 is used). -
Page 419: Table 19-1. Nor Flash Interface Signals Description
GD32VF103 User Manual PSRAM, SRAM, ROM and honeycomb RAM external memory. EXMC has 1 independent chip-select signals for 1 sub-bank within bank0, named NE[0]. Other signals for NOR/PSRAM access are shared. Each sub-bank has its own set of configuration register. -
Page 420: Table 19-4. Nor / Psram Controller Timing Parameters
GD32VF103 User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Async Use of byte lanes Async EXMC_NBL[1:0] Async PSRAM Async Split into 2 EXMC Async accesses... -
Page 421: Figure 19-4. Multiplex Mode Read Access
GD32VF103 User Manual Table 19-5. EXMC_timing models Timing Extend Write timing Read timing Mode description model mode parameter parameter DSET DSET AHLD AHLD Async Mode AM NOR Flash address/data mux ASET ASET BUSLAT BUSLAT As shown in Table 19-5. EXMC_timing... -
Page 422: Table 19-6. Multiplex Mode Related Registers Configuration
GD32VF103 User Manual Table 19-6. Multiplex mode related registers configuration EXMC_SNCTLx Bit Position Bit Name Reference Setting Value 31-16 Reserved 0x0000 ASYNCWAIT Depends on memory Reserved NRWTEN WREN Depends on memory 11:10 Reserved NRWTPOL Meaningful only when the bit 15 is set to 1... -
Page 423: Figure 19-6. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32VF103 User Manual Figure 19-6. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Output Enable (EXMC_NOE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time... -
Page 424: Register Definition
GD32VF103 User Manual 19.4. Register definition EXMC base address: 0xA000 0000 19.4.1. NOR/PSRAM controller registers SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0) Address offset: 0x00 + 8 * x, (x = 0) Reset value: 0x0000 30DA for region0. This register has to be accessed by word (32-bit) - Page 425 GD32VF103 User Manual Reserved Must be kept at reset value. NREN NOR Flash access enable 0: Disable NOR Flash access 1: Enable NOR Flash access NRW[1:0] NOR region memory data bus width 00: 8 bits 01: 16 bits(default after reset)
- Page 426 GD32VF103 User Manual …… 0xF: Bus latency = 16 * HCLK period 15:8 DSET[7:0] Data setup time This field is meaningful only in asynchronous access. 0x00: Reserved 0x01: Data setup time = 2 * HCLK period …… 0xFF: Data setup time = 256 * HCLK period...
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Page 427: Controller Area Network (Can)
Prioritization of messages Supports Time Stamp at SOF transmission Reception Supports 2 receive FIFOs and each has 3 messages deep 28 scalable/configurable identifier filter banks in GD32VF103 FIFO lock Time-triggered communication Disable retransmission automatically ... -
Page 428: Function Overview
GD32VF103 User Manual 20.3. Function overview Figure 20-1. CAN module block diagram shows the CAN block diagram. Figure 20-1. CAN module block diagram Transmit Receive CAN0 CAN0 Tx/Rx mailbox[0..2] FIFO[0..1] Transmit Receive CAN1 CAN1 Tx/Rx mailbox[0..2] FIFO[0..1] 20.3.1. Working mode The CAN interface has three working modes: ... -
Page 429: Communication Modes
GD32VF103 User Manual Initial working mode When the options of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set. -
Page 430: Data Transmission
GD32VF103 User Manual Loopback communication mode Loopback communication mode means the sending messages are transferred into the reception FIFOs, the RX pin is disconnected from the CAN network and the TX pin can send messages to the CAN network. Set LCMOD bit in CAN_BT register to enter loopback communication mode or clear it to leave. -
Page 431: Figure 20-3. State Of Transmission Mailbox
GD32VF103 User Manual Transmit mailbox state A transmit mailbox can be used when it is free: empty state. If the data is filled in the mailbox, setting TEN bit in CAN_TMIx register to prepare for starting the transmission: pending state. -
Page 432: Data Reception
GD32VF103 User Manual done immediately. In the state of transmit, the abort of transmission does not take effect immediately until the transmission is finished. In case of transmission successful, the MTFNERR and MTF in CAN_TSTAT are set and state changes to empty. In case of transmission failed, the state changes to be scheduled and then the abort of transmission can be done immediately. -
Page 433: Filtering Function
GD32VF103 User Manual by the arriving sequence of the frames. First arrived frame can be accessed by application firstly. The number of frames in the receive FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1. If at least one frame has been stored in the receive FIFO0. The frame data is placed in the... -
Page 434: Figure 20-5. 32-Bit Filter
GD32VF103 User Manual Figure 20-5. 32-bit filter 16-bit: SFID [10:0], FT, FF and EFID[17:15] bits. As shown in Figure 20-6. 16-bit filter. Figure 20-6. 16-bit filter Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match”... -
Page 435: Table 20-1. 32-Bit Filter Number
GD32VF103 User Manual Filter number Each filter within a filter bank is numbered from 0 to a maximum dependent on the mode and the scale of each of the filter banks. For example, there are two filter banks. Bank 0 is configured as 32-bit mask mode. Bank 1 is configured as 32-bit list mode. -
Page 436: Time-Triggered Communication
GD32VF103 User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active Bank Nunber Bank Nunber F3DATA1[15:0]-16bit-ID F5DATA0-32bit-ID F3DATA1[31:16]-16bit- F5DATA1-32bit-ID Mask F7DATA0[15:0]-16bit-ID F6DATA0[15:0]-16bit-ID F7DATA0[31:16]-16bit-ID F6DATA0[31:16]-16bit-ID F7DATA1[15:0]-16bit-ID F6DATA1[15:0]-16bit-ID F7DATA1[31:16]-16bit-ID F6DATA1[31:16]-16bit-ID F8DATA0[15:0]-16bit-ID F10DATA0[15:0]-16bit-ID F8DATA0[31:16]-16bit-ID F10DATA0[31:16]-16bit-Mask F8DATA1[15:0]-16bit-ID F10DATA1[15:0]-16bit-ID F8DATA1[31:16]-16bit-ID F10DATA1[31:16]-16bit-Mask F9DATA0[15:0]-16bit-ID F11DATA0[15:0]-16bit-ID F9DATA0[31:16]-16bit- F11DATA0[31:16]-16bit-ID... -
Page 437: Communication Parameters
GD32VF103 User Manual 20.3.7. Communication parameters Nonautomatic retransmission mode This mode has been implemented in order to fulfill the requirement of the time-triggered communication option of the CAN standard. To configure the hardware in this mode the ARD bit in the CAN_CTL register must be set. -
Page 438: Error Flags
GD32VF103 User Manual but may also be automatically shortened to compensate for negative phase drifts. The bit time is shown as in the Figure 20-11. The bit time. Figure 20-11. The bit time Normal Bit Time Propagation Sync Phase buffer... -
Page 439: Can Interrupts
GD32VF103 User Manual according to the error condition. For detailed information about TECNT and RECNT management, please refer to the CAN standard. Both of them may be read by software to determine the stability of the network. Furthermore, the CAN hardware provides detailed information on the current error status in CAN_ERR register. - Page 440 GD32VF103 User Manual Receive FIFO0 interrupt The Receive FIFO0 interrupt can be generated by the following conditions: Reception FIFO0 not empty: RFL0 bits in the CAN_RFIFO0 register are not ‘00’ and RFNEIE0 in CAN_INTEN register is set. Reception FIFO0 full: RFF0 bit in the CAN_RFIFO0 register is set and RFFIE0 in CAN_INTEN register is set.
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Page 441: Register Definition
GD32VF103 User Manual 20.4. Register definition CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 20.4.1. Control register (CAN_CTL) Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit) Reserved SLPWMO SWRST Reserved ABOR... -
Page 442: Status Register (Can_Stat)
GD32VF103 User Manual SLPWMOD bit in CAN_CTL register will be cleared automatically. 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable Automatic retransmission 1: Disable Automatic retransmission... - Page 443 GD32VF103 User Manual RX level LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state...
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Page 444: Transmit Status Register (Can_Tstat)
GD32VF103 User Manual 1: CAN is the state of sleep working mode Initial working state This bit is set by hardware when the CAN enter initial working mode after set IWMOD bit in CAN_CTL register. If the CAN leave from normal working mode to initial working mode, it must wait the current frame transmission or reception completed. - Page 445 GD32VF103 User Manual TME1 Transmit mailbox 1 empty 0: Transmit mailbox 1 not empty 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
- Page 446 GD32VF103 User Manual This bit is set by hardware while the transmit error is occurred. This bit reset by software when write 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit reset by hardware when next transmit start.
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Page 447: Receive Message Fifo0 Register (Can_Rfifo0)
GD32VF103 User Manual 0: Mailbox 0 transmit is progressing 1: Mailbox 0 transmit finished 20.4.4. Receive message FIFO0 register (CAN_RFIFO0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RFD0 RFO0 RFF0... -
Page 448: Interrupt Enable Register (Can_Inten)
GD32VF103 User Manual This register has to be accessed by word(32-bit) Reserved Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RFD1 Receive FIFO1 dequeue This bit is set by the software to start dequeuing a frame from receive FIFO1. - Page 449 GD32VF103 User Manual Bits Fields Descriptions 31:18 Reserved Must be kept at reset value SLPWIE Sleep working interrupt enable 0: Sleep working interrupt disable 1: Sleep working interrupt enable Wakeup interrupt enable 0: Wakeup interrupt disable 1: Wakeup interrupt enable...
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Page 450: Error Register (Can_Err)
GD32VF103 User Manual RFFIE0 Receive FIFO0 full interrupt enable 0: Receive FIFO0 full interrupt disable 1: Receive FIFO0 full interrupt enable RFNEIE0 Receive FIFO0 not empty interrupt enable 0: Receive FIFO0 not empty interrupt disable 1: Receive FIFO0 not empty interrupt enable... -
Page 451: Bit Timing Register (Can_Bt)
GD32VF103 User Manual Reserved Must be kept at reset value BOERR Bus-off error Whenever the CAN enters bus-off state, the bit will be set by the hardware. The bus-off state is entered on TECNT overflow, greater than 255. PERR Passive error Whenever the TECNT or RECNT is greater than 127, the bit will be set by the hardware. -
Page 452: Transmit Mailbox Identifier Register (Can_Tmix) (X=0
GD32VF103 User Manual Bit segment 1 time quantum=BS1[3:0]+1 15:10 Reserved Must be kept at reset value BAUDPSC[9:0] Baud rate prescaler The CAN baud rate prescaler 20.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) Address offset: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (bit0=0) -
Page 453: Transmit Mailbox Property Register (Can_Tmpx) (X=0
GD32VF103 User Manual 20.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2) Address offset: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. -
Page 454: Transmit Mailbox Data1 Register (Can_Tmdata1X) (X=0
GD32VF103 User Manual Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 20.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX... -
Page 455: Receive Fifo Mailbox Property Register (Can_Rfifompx) (X=0,1)
GD32VF103 User Manual Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:1 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier... -
Page 456: Receive Fifo Mailbox Data0 Register (Can_Rfifomdata0X) (X=0,1)
GD32VF103 User Manual 20.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) Address offset: 0x1B8, 0x1C8 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16... -
Page 457: Filter Control Register (Can_Fctl)
GD32VF103 User Manual 20.4.17. Filter control register (CAN_FCTL) Address offset: 0x200 Reset value: 0x2A1C 0E01 This register has to be accessed by word(32-bit) Reserved Reserved HBC1F[5:0] Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value 13:8 HBC1F[5:0] Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 filter. -
Page 458: Filter Scale Configuration Register (Can_Fscfg)
GD32VF103 User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:0 FMODx Filter mode 0: Filter x with Mask mode 1: Filter x with List mode 20.4.19. Filter scale configuration register (CAN_FSCFG) Address offset: 0x20C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). -
Page 459: Filter Working Register (Can_Fw)
GD32VF103 User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:0 FAFx Filter associated FIFO 0: Filter x associated with FIFO0 1: Filter x associated with FIFO1 20.4.21. Filter working register (CAN_FW) Address offset: 0x21C Reset value: 0x0000 0000... - Page 460 GD32VF103 User Manual Bits Fields Descriptions 31:0 Filter data Mask mode 0: Mask match disable 1: Mask match enable List mode 0: List identifier bit is 0 1: List identifier bit is 1...
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Page 461: Universal Serial Bus Full-Speed Interface (Usbfs)
GD32VF103 User Manual Universal serial bus full-speed interface (USBFS) The USBFS is available on GD32VF103 series. 21.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol). -
Page 462: Block Diagram
GD32VF103 User Manual 21.3. Block diagram Figure 21-1. USBFS block diagram interrupts AHB Slave Device bus Host Port control Control Data FIFO Transcation Scheduler Control VBUS USB Clock 48MHz 21.4. Signal description Table 21-1. USBFS signal description I/O port Type... -
Page 463: Figure 21-2. Connection With Host Or Device Mode
GD32VF103 User Manual or OTG mode) and connection status. A typical connection is shown in Figure 21-2. Connection with host or device mode Figure 21-2. Connection with host or device mode 5V Power Supply GPIO (needed in host mode) VBUS... -
Page 464: Usb Host Function
GD32VF103 User Manual Figure 21-3. Connection with OTG mode 5V Power GPIO Supply VBus VBUS 21.5.2. USB host function USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state. - Page 465 GD32VF103 User Manual Connection, Reset and Speed identification As a USB host, USBFS will trigger a connection flag for application after a connection is detected and will trigger a disconnection flag after a disconnection event. PRST bit is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset.
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Page 466: Usb Device Function
GD32VF103 User Manual USB 2.0 protocol divides these transfers into 2 kinds: non-periodic transfer (control and bulk) and periodic transfer (interrupt and isochronous). Based on this, USBFS includes two request queues: periodic request queue and non-periodic request queue, to perform efficient transaction schedule. -
Page 467: Otg Function Overview
GD32VF103 User Manual As required by USB 2.0 protocol, USBFS doesn’t support low-speed in device mode. Suspend and Wake-up A USB device will enter into suspend state when the USB bus stays at IDLE state and there is no change on data lines for 3ms. When USB device is in suspend state, most of its clock are closed to save power. -
Page 468: Data Fifo
GD32VF103 User Manual The Host Negotiation Protocol (HNP) allows the host function to be switched between two directly connected On-The-Go devices and eliminates the necessity of switching the cable connections for the change of control of communications between the devices. HNP will be initialized typically by the user or an application on the On-The-Go B-Device. -
Page 469: Figure 21-5. Host Mode Fifo Space In Sram
GD32VF103 User Manual transmission packet. All IN channels shares the Rx FIFO for packets reception. All the periodic OUT channels share the periodic Tx FIFO to packets tramsmission. All the non- periodic OUT channels share the non-Periodic Tx FIFO for transmit packets. The size and start offset of these data FIFOs should be configured using these registers: USBFS_GRFLEN, USBFS_HNPTFLEN and USBFS_HPTFLEN. -
Page 470: Figure 21-7. Device Mode Fifo Space In Sram
GD32VF103 User Manual The size and start offset of these data FIFOs should be configured using USBFS_GRFLEN and USBFS_DIEPxTFLEN (x=0…3) registers. Figure 21-7. Device mode FIFO space in SRAM describes the structure of these FIFOs in SRAM. The values in the figure are in term of 32-bit words. -
Page 471: Operation Guide
GD32VF103 User Manual Figure 21-8. Device mode FIFO access register map 21.5.6. Operation guide This section describes the advised operation guide for USBFS. Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the TxFIFO’s empty threshold, etc. - Page 472 GD32VF103 User Manual Channel initialization and enable sequence 1. Program USBFS_HCHxCTL registers with desired transfer type, direction, packet size, etc. Ensure that CEN and CDIS bits keep cleared during configuration. 2. Program USBFS_HCHxINTEN register. Set the desired interrupt enable bits.
- Page 473 GD32VF103 User Manual received data packet into the Rx FIFO and triggers ACK flag. Otherwise, the status flag (NAK) reports the transaction result. 7. If the IN transaction described in step 5 is successful and PCNT is larger than 1 in step2, return to step 3 and continues to receive the remaining packets.
- Page 474 GD32VF103 User Manual 2. Program USBFS_GUSBCS register according to application’s demand, such as: the operation mode (host, device or OTG) and some parameters of OTG and USB protocols. 3. Program USBFS_GCCFG register according to application’s demand. 4. Program USBFS_GRFLEN, USBFS_HNPTFLEN_DIEP0TFLEN, USBFS_DIEPxTFLEN register to configure the data FIFOs according to application’s demand.
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Page 475: Interrupts
GD32VF103 User Manual 1. Initialize USBFS global registers. 2. Initialize and enable the IN endpoint. 3. Write packets into the endpoint’s Tx FIFO. Each time a data packet is written into the FIFO, USBFS decreases the TLEN field in USBFS_DIEPxLEN register by the written packet’s size. - Page 476 GD32VF103 User Manual Interrupt Flag Description Operation Mode PTXFEIF Periodic Tx FIFO empty interrupt flag Host Mode HCIF Host channels interrupt flag Host Mode HPIF Host port interrupt flag Host Mode ISOONCIF/PXNCI Periodic transfer Not Complete Interrupt Host or device mode...
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Page 477: Register Definition
GD32VF103 User Manual 21.7. Register definition USBFS base address: 0x5000 0000 21.7.1. Global control and status registers Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) - Page 478 GD32VF103 User Manual protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes.
- Page 479 GD32VF103 User Manual Note: Only accessible in device mode. SRPS SRP success This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP fails 1: SRP succeeds Note: Only accessible in device mode.
- Page 480 GD32VF103 User Manual Set by the core when a HNP ends. Read the HNPS in USBFS_GOTGCS register to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP.
- Page 481 GD32VF103 User Manual Host mode: 0: NPTXFEIF will be triggered when the non-periodic transmit FIFO is half empty 1: NPTXFEIF will be triggered when the non-periodic transmit FIFO is completely empty 6：1 Reserved Must be kept at reset value GINTEN Global interrupt enable 0: Global interrupt is not enabled.
- Page 482 GD32VF103 User Manual 0: Normal mode 1: Host mode The application must wait at least 25 ms for the change taking effect after setting the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value...
- Page 483 GD32VF103 User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non-periodic Tx FIFO is flushed...
- Page 484 GD32VF103 User Manual Set by the application to reset AHB clock domain circuit. Hardware automatically clears this bit after the reset process completes. After setting this bit, application should wait until this bit is cleared before any other operation on USBFS.
- Page 485 GD32VF103 User Manual Note: Accessible in both device and host modes. Reserved Must be kept at reset value PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the periodic transmit FIFO is either half or completely empty. The threshold is determined by the periodic Tx FIFO empty level bit (PTXFTH) in the USBFS_GAHBCS register.
- Page 486 GD32VF103 User Manual Note: Only accessible in device mode. IEPIF IN endpoint interrupt flag Set by USBFS when one of the IN endpoints in device mode has raised an interrupt. Software should first read USBFS_DAEPINT register to get the device number, and then read the corresponding USBFS_DIEPxINTF register to get the flags of the endpoint that cause the interrupt.
- Page 487 GD32VF103 User Manual flag after the writing to SGINAK takes effect. Note: Only accessible in device mode. NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the non-periodic transmit FIFO is either half or completely empty. The threshold is determined by the non-periodic Tx FIFO empty level bit (TXFTH) in the USBFS_GAHBCS register.
- Page 488 GD32VF103 User Manual This register has to be accessed by word (32-bit) Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable wakeup interrupt 1: Enable wakeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes.
- Page 489 GD32VF103 User Manual HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value PXNCIE Periodic transfer not complete Interrupt enable 0: Disable periodic transfer not complete interrupt 1: Enable periodic transfer not complete interrupt Note: Only accessible in host mode.
- Page 490 GD32VF103 User Manual 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode. SPIE USB suspend interrupt enable 0: Disable USB suspend interrupt 1: Enable USB suspend interrupt Note: Only accessible in device mode.
- Page 491 GD32VF103 User Manual Note: Accessible in both device and host modes. Reserved Must be kept at reset value Global receive status read/receive status read registers (USBFS_GRSTATR/USBFS_GRSTATP) Address offset for Read: 0x001C Address offset for Pop: 0x0020 Reset value: 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO.
- Page 492 GD32VF103 User Manual 01: DATA2 11: MDATA 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to which the current received packet belongs. Device mode: Bits Fields Descriptions 31:21 Reserved...
- Page 493 GD32VF103 User Manual Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit words.
- Page 494 GD32VF103 User Manual Host Mode: Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit words. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx RAM start address The start address for non-periodic transmit FIFO RAM is in term of 32-bit words.
- Page 495 GD32VF103 User Manual 30:24 NPTXRQTOP[6:0] Top entry of the non-periodic Tx request queue Entry in the non-periodic transmit request queue. Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token – 01: Zero-length OUT packet – 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel.
- Page 496 GD32VF103 User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value VBUSIG VBUS ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and always consider VBUS voltage as valid both in host mode and in device mode, then free the VBUS pin for other usage.
- Page 497 GD32VF103 User Manual Bits Fields Descriptions 31:0 CID[31:0] Core ID Software can write or read this field and uses this field as a unique ID for its application Host periodic transmit FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600...
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Page 498: Host Control And Status Registers
GD32VF103 User Manual r/rw r/rw Bits Fields Descriptions 31:16 IEPTXFD[15:0] IN endpoint Tx FIFO depth In terms of 32-bit words. 1≤HPTXFD≤1024 15:0 IEPTXRSAR[15:0] IN endpoint FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32-bit words. - Page 499 GD32VF103 User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CLKSEL[1:0] Clock select for usbclock. 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the frame interval for the current enumerating speed when USBFS controller is enumerating.
- Page 500 GD32VF103 User Manual Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks. 15:0 FRNUM[15:0] Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF.
- Page 501 GD32VF103 User Manual Entry in the periodic transmit request queue. Bits 30:27: Channel Number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 PTXREQS[7:0] Periodic Tx request queue space The remaining space of the periodic transmit request queue.
- Page 502 GD32VF103 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN)
- Page 503 GD32VF103 User Manual register is set by USBFS: PRST, PEDC and PCD. This register has to be accessed by word (32-bit) rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value 18:17 PS[1:0] Port speed Report the enumerated speed of the device attached to this port.
- Page 504 GD32VF103 User Manual Port suspend Application sets this bit to put port into suspend state. When this bit is set the port stops sending SOF tokens. This bit can only be cleared by the following operations: PRST bit in this register is set by application...
- Page 505 GD32VF103 User Manual Bits Fields Descriptions Channel enable Set by the application and cleared by USBFS. 0: Channel disabled 1: Channel enabled Software should following the operation guide to disable or enable a channel. CDIS Channel disable Software can set this bit to disable the channel from processing transactions.
- Page 506 GD32VF103 User Manual EPDIR Endpoint direction The transfer direction of the endpoint that this channel wants to communicate with. 0: OUT 1: IN 14:11 EPNUM[3:0] Endpoint number The number of the endpoint that this channel wants to communicate with. 10:0...
- Page 507 GD32VF103 User Manual a device sends a data packet and the packet length exceeds the endpoint’s maximum packet length. USBER USB Bus Error The USB error flag is set when the following conditions occurs during receiving a packet: A received packet has a wrong CRC field...
- Page 508 GD32VF103 User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value DTERIE Data toggle error interrupt enable 0: Disable data toggle error interrupt 1: Enable data toggle error interrupt REQOVRIE Request queue overrun interrupt enable 0: Disable request queue overrun interrupt...
- Page 509 GD32VF103 User Manual CHIE Channel halted interrupt enable 0: Disable channel halted interrupt 1: Enable channel halted interrupt TFIE Transfer finished interrupt enable 0: Disable transfer finished interrupt 1: Enable transfer finished interrupt Host channel-x transfer length register (USBFS_HCHxLEN) (x = 0..7, where x = channel number) Address offset: 0x0510 + (channel_number ×...
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Page 510: Device Control And Status Registers
GD32VF103 User Manual Software should program this field before the channel is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet transmission. 18:0 TLEN[18:0] Transfer length The total data bytes number of a transfer. - Page 511 GD32VF103 User Manual 10: 90% of the frame time 11: 95% of the frame time 10:4 DAR[6:0] Device address This field defines the USB device’s address. USBFS uses this field to match with the incoming token’s device address field. Software should program this field after receiving a Set Address command from USB host.
- Page 512 GD32VF103 User Manual Software should set this bit to notify USBFS that the registers are initialized after waking up from power down state. CGONAK Clear global OUT NAK Software sets this bit to clear GONS bit in this register. SGONAK Set global OUT NAK Software sets this bit to set GONS bit in this register.
- Page 513 GD32VF103 User Manual Device status register (USBFS_DSTAT) Address offset: 0x0808 Reset value: 0x0000 0000 This register contains status and information of the USBFS in device mode. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:22 Reserved...
- Page 514 GD32VF103 User Manual are set and cleared by software. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:7 Reserved Must be kept at reset value IEPNEEN IN endpoint NAK effective interrupt enable bit 0: Disable IN endpoint NAK effective interrupt...
- Page 515 GD32VF103 User Manual Reset value: 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_DOEPxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_DOEPxINTF register is able to trigger an endpoint interrupt in USBFS_DAEPINT register. The bits in this register are set and cleared by software.
- Page 516 GD32VF103 User Manual Device all endpoints interrupt register (USBFS_DAEPINT) Address offset: 0x0818 Reset value: 0x0000 0000 When an endpoint interrupt is triggered, USBFS sets corresponding bit in this register and software should read this register to know which endpoint is asserting an interrupt.
- Page 517 GD32VF103 User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value 19:16 OEPIE[3:0] Out endpoint interrupt enable 0: Disable OUT endpoint-n interrupt 1: Enable OUT endpoint-n interrupt Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.
- Page 518 GD32VF103 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DVBUSDT[15:0] Device V discharge time There is a discharge process after V pulsing in SRP protocol. This field defines the discharge time of V The true discharge time is 1024 * DVBUSDT[15:0] BUS.
- Page 519 GD32VF103 User Manual This register contains the enable bits for the Tx FIFO empty interrupts of IN endpoints. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:4 Reserved Must be kept at reset value IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register.
- Page 520 GD32VF103 User Manual Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should following the operation guide to disable or enable an endpoint.
- Page 521 GD32VF103 User Manual MPL[1:0] Maximum packet length This field defines the maximum packet length for a control data packet. As described in USB 2.0 protocol, there are 4 kinds of length for control transfers: 00: 64 bytes 01: 32 bytes...
- Page 522 GD32VF103 User Manual SEVENFRM Set even frame (For isochronous IN endpoints) Software sets this bit to clear EOFRM bit in this register. SD0PID Set DATA0 PID (For interrupt/bulk IN endpoints) Software sets this bit to clear DPID bit in this register.
- Page 523 GD32VF103 User Manual 0: Only sends data in even frames 1: Only sends data in odd frames DPID Endpoint data PID (For interrupt/bulk IN endpoints) There is a data PID toggle scheme in interrupt or bulk transfer. Set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers according to the data toggle scheme described in USB protocol.
- Page 524 GD32VF103 User Manual 29:28 Reserved Must be kept at reset value SNAK Set NAK Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register 25:22...
- Page 525 GD32VF103 User Manual Device OUT endpoint-x control register (USBFS_DOEPxCTL) (x = 1..3, where x = endpoint_number) Address offset: 0x0B00 + (endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the operations of each logical OUT endpoint other than OUT endpoint 0.
- Page 526 GD32VF103 User Manual Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register. 25:22 Reserved Must be kept at reset value STALL STALL handshake Software can set this bit to make USBFS sends STALL handshake during an OUT transaction.
- Page 527 GD32VF103 User Manual These is a data PID toggle scheme in interrupt or bulk transfer. Software should set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers following the data toggle scheme described in USB protocol.
- Page 528 GD32VF103 User Manual The setting of SNAK bit in USBFS_DIEPxCTL register takes effect. This bit can be cleared either by writing 1 to it or by setting CNAK bit in USBFS_DIEPxCTL register. Reserved Must be kept at reset value EPTXFUD...
- Page 529 GD32VF103 User Manual BTBSTP Back-to-back SETUP packets (Only for control OUT endpoint) This flag is triggered when a control out endpoint has received more than 3 back- to-back setup packets. Reserved Must be kept at reset value EPRXFOVR Endpoint Rx FIFO overrun This flag is triggered if the OUT endpoint’s Rx FIFO has no enough space for a...
- Page 530 GD32VF103 User Manual The number of data packets desired to be transmitted in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet transmission.
- Page 531 GD32VF103 User Manual 11: 3 packets 28:20 Reserved Must be kept at reset value PCNT Packet count The number of data packets desired to receive in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet reception on bus.
- Page 532 GD32VF103 User Manual 10: 2 packets 11: 3 packets 28:19 PCNT[9:0] Packet count The number of data packets desired to be transmitted in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet transmission.
- Page 533 GD32VF103 User Manual This field defines the maximum number of back-to-back SETUP packets this endpoint can accept. Program this field before setup transfers. Each time a back-to-back setup packet is received, USBFS decrease this field by one. When this field reaches zero, the BTBSTP flag in USBFS_DOEPxINTF register will be triggered.
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Page 534: Power And Clock Control Register (Usbfs_Pwrclkctl)
GD32VF103 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 IEPTFS[15:0] IN endpoint’s Tx FIFO space remaining N endpoint’s Tx FIFO space remaining in 32-bit words: 0: FIFO is full 1: 1 word available …... -
Page 535: Revision History
GD32VF103 User Manual Revision history Table 22-1. Revision history Revision No. Description Date Initial Release Jun.5, 2019... - Page 536 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.
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