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Fujitsu F2MC-8L Family series Hardware Manual

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FUJITSU SEMICONDUCTOR
CM25-10130-1E
CONTROLLER MANUAL
2
F
MC-8L FAMILY
MICROCONTROLLERS
MB89950 SERIES
HARDWARE MANUAL

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Summary of Contents for Fujitsu F2MC-8L Family series

  • Page 1 FUJITSU SEMICONDUCTOR CM25-10130-1E CONTROLLER MANUAL MC-8L FAMILY MICROCONTROLLERS MB89950 SERIES HARDWARE MANUAL...
  • Page 2 PREFACE The MB89950 series of microcontrollers are mid-range of microcontroller. They are general-purpose and high-speed products in the F MC-8L Family series of 8-bit single- chip microcontrollers operating at low voltages. It has UART, PWM, LCD controller and etc. This manual covers the functions and operations of the MB89950 series of microcontrollers. Refer to the F MC-8L Family Software Manual for instructions.

  • Page 3: Table Of Contents

    Table of Contents 1. GENERAL ........................1-1 1.1 Features ........................1-3 1.2 Product Series ......................1-4 1.3 Block Diagram ......................1-5 1.4 Pin Assignment ......................1-6 1.5 Pin Description ......................1-8 1.6 Handling Devices ....................1-12 2. HARDWARE CONFIGURATION ..................2-1 2.1 CPU .........................2-3 2.1.1 Memory Space ....................2-3 2.1.2 Arrangement of 16-bit Data in Memory Space ..........2-5 2.1.3 Internal Registers in CPU ................2-6 2.1.4 Clock Control Block ..................2-9...
  • Page 4 Tables Table 1–1 Types and Functions of MB89950 Series of Microcontrollers ......1-4 Table 1–2 Pin Description ....................1-8 Table 1–3 Pin Description for External ROM ..............1-9 Table 2–1 Table of Reset and Interrupt Vectors ..............2-4 Table 2–2 Operating Mode of Low-power Consumption Modes ........2-11 Table 2–3 Selection of Oscillation Stabilization Time ............
  • Page 5 Figures Fig. 1.1 Block Diagram (MB89953) .....................1-5 Fig. 1.2 Pin Assignment of MB89953 and MB89P955 (QFP-64, pitch: 0.65 mm) .......1-6 Fig. 1.3 Pin Assignment of MB89PV950 (MQFP-64, pitch: 0.8 mm) ...........1-7 Fig. 1.4 I/O Circuits ........................1-10 Fig. 2.1 Memory Space of MB89950 Series Microcontrollers .............2-3 Fig.
  • Page 6 1. GENERAL 1.1 Features ................1-3 1.2 Product Series ............... 1-4 1.3 Block Diagram ............... 1-5 1.4 Pin Assignment ..............1-6 1.5 Pin Description ..............1-8 1.6 Handling Devices ..............1-12...

  • Page 7: General

    GENERAL The MB89950 series of single-chip compact microcontroller using the F MC-8L core for which can operate at high-speeds and low voltages. They contain peripheral such as timers, UART, serial interfaces, and external interrupts, including a 168-pixel LCD controller/driver; they are best suited for use in LCD panels. 1.1 Features •...

  • Page 8: Product Series

    GENERAL 1.2 Product Series Table 1–1 lists the types and functions of the MB89950 series of microcontrollers. Table 1–1 Types and Functions of MB89950 Series of Microcontrollers Model name MB89951 MB89953 MB89P955 MB89PV950 Classification Mass-produced product One-time programmable Piggyback/Evaluation (Mask ROM product) and development product ROM capacity...

  • Page 9: Block Diagram

    GENERAL 1.3 Block Diagram Internal bus Main oscillator Time-base timer circuit 8-bit PWM timer P41/PWM Clock control External interrupt Reset circuit (WDT) 8-bit Noise P42/PWC/ pulse width clear Port count timer INT1 Port 2 P20 to P25/ SEG36 to N-ch open-drain I/O port SEG41 P45/SCK 8-bit serial...

  • Page 10: Pin Assignment

    GENERAL 1.4 Pin Assignment SEG4 P00/SEG20 SEG3 P01/SEG21 SEG2 P02/SEG22 SEG1 P03/SEG23 SEG0 P04/SEG24 COM3 P05/SEG25 Top view COM2 P06/SEG26 QFP-64 COM1 P07/SEG27 COM0 P10/SEG28 P11/SEG29 P33/V2 P12/SEG30 P32/V1 P13/SEG31 P14/SEG32 P15/SEG33 P16/SEG34 P41/PWM P17/SEG35 Fig. 1.2 Pin Assignment of MB89953 and MB89P955 (QFP-64, pitch: 0.65 mm) 1–...

  • Page 11: Fig. 1.3 Pin Assignment Of Mb89Pv950 (Mqfp-64, Pitch: 0.8 Mm)

    GENERAL SEG5 SEG18 SEG4 SEG19 SEG3 SEG20/P00 SEG2 SEG21/P01 SEG1 SEG22/P02 SEG0 SEG23/P03 COM3 SEG24/P04 COM2 SEG25/P05 COM1 SEG26/P06 COM0 SEG27/P07 SEG28/P10 V2/P33 SEG29/P11 V1/P32 SEG30/P12 SEG31/P13 SEG32/P14 SEG33/P15 PWM/P41 SEG34/P16 INT1/PWC/P42 SEG35/P17 SI/P43 SEG36/P20 (Top View) Fig. 1.3 Pin Assignment of MB89PV950 (MQFP-64, pitch: 0.8 mm) Pin assignment on package top (MB89PV950 only ) Pin No.

  • Page 12: Pin Description

    GENERAL 1.5 Pin Description Table 1–2 lists the pin functions and shows the Fig. 1.4 input/output circuits. Table 1–2 Pin Description Pin No Pin Name Circuit Function 0.65 Clock oscillator pins MODA Operation-mode select pins This pin is connected directly to V with pull down resistor.

  • Page 13: Table 1-3 Pin Description For External Rom

    GENERAL Table 1–2 Pin Description (Continued) Pin No Pin Name Circuit Function 0.65 P46/INT0 General-purpose input port Also serves as external-interrupt input (INT0). The input is hysteresis type. A pull-up resistor option is provided. 5 to 1 6 to 1 SEG0 to For LCDC controller segment ouput 64 to 57...

  • Page 14: Fig. 1.4 I/O Circuits

    GENERAL Table 1–3 Pin Description for External ROM (Continued) • External EPROM pins (for MB89PV950) Pins No. Pin Name Function For internal connection N.C. — Keep open. Fig. 1.4 I/O Circuits Classification Circuit Remarks • Crystal oscillator Ω • Feedback resistor: About 1 M 5 V (1 to 5 MHz) Standby control signal •...
  • Page 15 GENERAL Fig. 1.4 I/O Circuits (Continued) Classification Circuit Remarks • CMOS output • CMOS input • Hysteresis input (peripheral input) P-ch P-ch N-ch • The pull-up resistor is optional. • N-ch open-drain output • CMOS input N-ch • LCDC output 1–...

  • Page 16: Handling Devices

    GENERAL 1.6 Handling Devices (1) Preventing latch-up Latchup may occur on CMOS ICs if voltage higher than V or lower than V is applied to input and output pins other than medium to high-voltage pins or if higher than the voltage which shows on Absolute Maximum Ratings is applied between V and V When latch-up occurs, supply current increases rapidly and might thermally damage elements.

  • Page 17: Hardware Configuration

    2. HARDWARE CONFIGURATION 2.1 CPU ..................2-3 2.2 Peripherals ................2-18...

  • Page 18: Cpu

    HARDWARE CONFIGURATION This chapter describes each block of the CPU hardware. 2.1 CPU This section describes the memory space and register composing CPU hardware. 2.1.1 Memory Space MC-8L CPU has a memory space of 64 Kilobytes. All I/O, data, and program areas are located in this space.

  • Page 19: Table 2-1 Table Of Reset And Interrupt Vectors

    HARDWARE CONFIGURATION (1) I/O area This area is where various peripherals such as control and data registers are located. The memory map for the I/O area is given in APPENDIX A. (2) RAM area This area is where the static RAM is located. Addresses from 0100 (0100 to 013F in MB89951, 0100...

  • Page 20: Arrangement Of 16-Bit Data In Memory Space

    HARDWARE CONFIGURATION 2.1.2 Arrangement of 16-bit Data in Memory Space When the MB89950 series of microcontrollers handle 16-bit data, the data written at the lower address is treated as the upper 8-bit data and that written at the next address is treated as the lower 8-bit data as shown in Fig. 2.2. Memory Memory After execution...

  • Page 21: Internal Registers In Cpu

    HARDWARE CONFIGURATION 2.1.3 Internal Registers in CPU The MB89950 series of microcontrollers have dedicated registers in the CPU and general-purpose registers in memory. The types of dedicated registers are as follows. • Program counter (PC) 16-bit length register indicating the location where instructions are stored.

  • Page 22: Fig. 2.4 Structure Of Processor Status

    HARDWARE CONFIGURATION The 16 bits of the processor status (PS) can be divided into 8 upper bits for a register bank pointer (RP) and 8 lower bits for a condition code register (CCR). (See Fig. 2.4.) IL1, 0 Vacant Vacant Vacant Fig.

  • Page 23: Fig. 2.6 Register Bank Configuration

    HARDWARE CONFIGURATION - Z-flag Z-flag is set when zero is the result of operations; it is cleared in other cases. - V-flag V-flag is set when a two’s complement overflow occurs as a result of operations; it is reset when an overflow does not occur.

  • Page 24: Clock Control Block

    HARDWARE CONFIGURATION 2.1.4 Clock Control Block This block controls the standby operation and software reset. (1) Machine clock control block diagram (a) Machine clock control section Pin state Stop Clock CPU operation clock oscillator Clock control Peripheral operation clock Stop release signal From time-base timer Selector Option...
  • Page 25 HARDWARE CONFIGURATION (3) Description of registers The detail of each register is described below. (a) Standby control register (STBC) Address: 0008 STBC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — —...

  • Page 26: Table 2-2 Operating Mode Of Low-Power Consumption Modes

    HARDWARE CONFIGURATION (4) Description of operation (a) Low-power consumption mode This chip has three operation modes shown in the table below. The sleep mode and stop mode reduce the power consumption. The system clock can be selected out of three according to the system condition to minimize power consumption.

  • Page 27: Table 2-3 Selection Of Oscillation Stabilization Time

    HARDWARE CONFIGURATION b. STOP mode • Switching to STOP mode - Writing 1 at the STP (bit 7) of the STBC register switches the mode to STOP mode. - The STOP mode stops clock oscillation and the CPU and all peripherals stop.
  • Page 28 HARDWARE CONFIGURATION (b) State transition diagram SLEEP Clock oscillates. STOP Clock stops. Clock oscillates. Oscillation stabilization waiting Power-on (1) When power-on reset available selected (2) When power-on reset unavailable selected (3) After oscillation stabilizing (4) Set STP bit to 1. (5) Set SLP bit to 1.

  • Page 29: Table 2-4 Sources Of Reset

    HARDWARE CONFIGURATION (c) Reset There are four types of reset depending on the source shown in Table 2–4. Table 2–4 Sources of Reset Reset name Description External-pin reset When setting external-reset pin to Low Software reset When writing 0 at RST (bit 4) of STBC Watchdog reset When watchdog timer overflows Power-on reset...

  • Page 30: Interrupt Controller

    HARDWARE CONFIGURATION 2.1.5 Interrupt Controller The interrupt controller for the F MC-8L family is located between the CPU and each peripheral. This controller receives interrupt requests from the peripherals, assigns priority to them. When the interrupt controller transfers the priority to the CPU, it also decides the priority of same-level interrupts. (1) Block diagram MC-8L bus Address decoder...
  • Page 31 HARDWARE CONFIGURATION (3) Description of registers The details of each register is described below. (a) Interrupt level register 1 to 3 (ILRx: Interrupt Level Register x) Address: 007C ILR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 007D...

  • Page 32: Fig. 2.7 Interrupt-Processing Flowchart

    HARDWARE CONFIGURATION (4) Description of operation The functions of interrupt controllers are described below. (a) Interrupt functions The MB89950 series of microcontrollers have 7 inputs for interrupt requests from the peripherals. The interrupt level is set by 2-bit registers corresponding to each input. When an interrupt is requested from a peripheral, the interrupt controller receives it and transfers the contents of the corresponding level register to the CPU.

  • Page 33: Peripherals

    HARDWARE CONFIGURATION 2.2 Peripherals Peripherals 2.2.1 I/O Ports • The MB89950 series of microcontrollers have five parallel ports (33 pins). Ports 0 and 1 serve as 8-bit I/O ports; port 2 serves 6-bit I/O port; port 3 serves as 4-bit I/O ports; port 4 serves as 7-bit I/O port. •...
  • Page 34 HARDWARE CONFIGURATION (3) Description of functions Peripherals The function of each port is described below. P00 to P07: N-ch open-drain type input/output ports (also used as segment output) P10 to P17: N-ch open-drain type input/output ports (also used as segment output) P20 to P25: N-ch open-drain type input/output ports (also used as segment output)
  • Page 35 HARDWARE CONFIGURATION Peripherals Internal-data bus Segment output Mask option Segment output select register (Note) Stop, SPL = 1 PDR read PDR read (when Read Modify Write instruction executed) Output latch N-ch PDR write Stop, SPL = 1 Fig. 2.8 Ports 0, 1 and 2 Note: Selection of segment output using the mask option is available only for mass-produced products.
  • Page 36 HARDWARE CONFIGURATION Peripherals P30, P31: N-ch open-drain output, CMOS input P32, P33: N-ch open-drain type input/output ports (also used as LCD controller power supply V1,V2) • Operation for output port The value written at the PDR is output to the pin. When the PDR is read, usually, the value of the pin is read instead of the contents of the output latch.

  • Page 37: Fig. 2.9 Port

    HARDWARE CONFIGURATION Internal-data bus Only for P32 and P33 PSEL of LCDR V1/ V2 Stop PDR read PDR read (when Read Modify Write instruction executed) Output latch N-ch PDR write Stop, SPL = 1 Fig. 2.9 Port 3 2– 22...
  • Page 38 HARDWARE CONFIGURATION P40 to P46: CMOS type I/O ports Peripherals (also used as peripheral input and output) • Switching input and output This port has a data-direction register (DDR) and a port-data register (PDR) for each bit. Input and output can be set independently for each bit.

  • Page 39: Fig. 2.10 Port 4

    HARDWARE CONFIGURATION Peripherals External interrupt enable Stop, SPL = 1 To external interrupt Stop, SPL = 1 Peripheral input Internal-data bus Pull-up resistor Peripheral Peripheral (option) output output enable PDR read P-ch PDR read (when Read Modify Write instruction executed) Output latch P-ch PDR write...

  • Page 40: 8-Bit Pwm Timer (Timer 1)

    HARDWARE CONFIGURATION 2.2.2 8-bit PWM Timer (Timer 1) Peripherals • This timer can be used as an 8-bit timer or PWM control circuit with 8-bit resolution. • Four kinds of clock frequency can be selected. (1) Block diagram Internal-data bus CNTR COMR —...
  • Page 41 HARDWARE CONFIGURATION (3) Description of registers Peripherals (a) Control register (CNTR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 0012H CNTR — Address: 0012 Address: 0013H COMR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
  • Page 42 HARDWARE CONFIGURATION Values of counter and COMR do not match. Values of counter and COMR match. Note that 1 is always read when the Read Modify Write instruction is Peripherals executed. The meaning of each bit to be written is as follows: Clears this bit Does not change this bit nor affect other bits Note: In the PWM operation mode, neither the read nor write values of...

  • Page 43: Fig. 2.11 Timer Operation

    HARDWARE CONFIGURATION (4) Description of operation Peripherals (a) Timer function Setting the P/TX bit of the CNTR to 0 gives the timer-operation mode. When the TPE bit of the CNTR is set to 1, the counter starts incrementing from . When the value of the counter agrees with that of the COMR, the counter is cleared on the next count clock pulse and incrementing restarts.

  • Page 44: Fig. 2.12 Pwm Pulse Output

    HARDWARE CONFIGURATION (b) PWM operation Peripherals Setting the P/TX bit of the CNTR to 1 gives the PWM operation mode. The COMR specifies the duty of the output pulse. Pulses can be output with 1/256 resolution and a duty of 0% to 99.6%. When 0 (00 ) is written at the COMR, the duty of the PWM output pulse is 0%;...

  • Page 45: Pulse-Width Count Timer (Timer 2)

    HARDWARE CONFIGURATION 2.2.3 Pulse-width Count Timer (Timer 2) Peripherals • This timer has timer and pulse-width measurement functions. • The timer function has two modes: reload timer and one-shot. • In the reload timer mode, the set values are counted down repeatedly. •...
  • Page 46 HARDWARE CONFIGURATION (2) Register list Peripherals 8 bits Address: 0014 PCR1 R/W Pulse-width control register 1 PCR2 R/W Pulse-width control register 2 Address: 0015 Address: 0016 RLBR R/W Reload buffer register NCCR R/W Noise-clear control register Address: 0017 (3) Description of registers (a) Pulse-width control register 1 (PCR1) Address: 0014 PCR1...
  • Page 47 HARDWARE CONFIGURATION 1 is always read when the Read Modify Write instruction is executed. Peripherals The meaning of each bit to be written is as follows: Clears this bit Unchanges this bit and other bits unaffected [Bit 1] IR: Measurement-end interrupt request bit When the IE bit (bit 5) of the PCR1 is 1, an interrupt occurs at the end of pulse-width measurement.
  • Page 48 HARDWARE CONFIGURATION [Bit 6] RM: Timer mode select bit Peripherals In the timer function, bit 6 is used to select the timer mode. Reload timer mode One-shot timer mode The mode should be changed only when the operation is stopped (when the EN bit (bit 7) of the PCR1 is 0).
  • Page 49 HARDWARE CONFIGURATION (d) Noise-clear control register (NCCR) Peripherals Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — — — — NCS1 NCS0 Address: 0017 Address: 0014 PCR1 (R/W) (R/W) (Initial value) ------00 Address: 0015 PCR2...

  • Page 50: Fig. 2.13 Measurement Of High Pulse Width

    HARDWARE CONFIGURATION (b) Pulse-width measurement function Peripherals a. Measurement start Writing 1 at the EN bit (bit 7) and FC bit (bit 7) causes the counter to enter the operation-enabled state. In this condition, counting starts when the edge of the measured pulse input is detected. At the pulse-width measurement function, counting down is started from FF b.

  • Page 51: Fig. 2.14 Operation Of Noise Clearing Circuit

    HARDWARE CONFIGURATION (c) Noise-clearing circuit operation Peripherals Figure 2.15 shows the operation of the noise-clearing circuit. The PWC input is sampled by the clock pulse selected by the clock pulse select bits (NCS1 and NCS0) of the noise-clear control register. Integrating the sampled signal clears the noise.

  • Page 52: Uart

    HARDWARE CONFIGURATION 2.2.4 UART Peripherals • Full-duplex double buffers • CLK synchronous and asynchronous data transfer • 8 baud rates (for internal clock) The baud rate can also be freely selected by external clock input or input from the internal timer. •...
  • Page 53 HARDWARE CONFIGURATION (b) Data transmitter/receiver Peripherals Data bus Parity RD8/RP generator MC1, 0 P43/SI Shifter Start Shift clock Receiver Start bit byte count detection Reset Transfer clock SIDR RDRF ORFE PEM, TD8/TP Parity generator Shifter Timing Shift clock P44/SO Transmitter Transmitter byte count control...
  • Page 54 HARDWARE CONFIGURATION (2) Register list Peripherals 8 bits R/W Serial mode control register 1 Address: SMC1 0020 R/W Serial rate control register Address: 0021 R/W Serial status and data register Address: 0022 Address: Serial input data register 0023 SIDR Address: 0023 SODR Serial output data register...
  • Page 55 HARDWARE CONFIGURATION [Bits 5 and 4] MC1 and MC0: Mode control Peripherals Bits 5 and 4 are used to select the transfer mode (data length). Mode Data Length 5 (4) (Initial value) Values in parentheses 8 (7) indicate the data length reserved reserved with parity.
  • Page 56 HARDWARE CONFIGURATION (b) Serial rate control register (SRC) Peripherals This register is used to control the data transfer speed (baud rate) of the UART. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 0020 SMC1 —...
  • Page 57 HARDWARE CONFIGURATION (c) Serial status and data register (SSD) Peripherals This register is used to indicate the current status of the UART port. When the data communication length is 9 bits, the most significant data (bit 8) is included. Bit 7 Bit 6 Bit 5 Bit 4...
  • Page 58 HARDWARE CONFIGURATION [Bit 5] TDRE: Peripherals The TDRE flag is used to indicate the status of the serial output data register (SODR). Contains data Empty (Initial value) If SODR (Serial Output Data Register) is empty, and newly written data to SODR, SODR will be driven out of the serial output pin (P44/SO).
  • Page 59 HARDWARE CONFIGURATION (d) Serial input data register (SIDR) Peripherals Serial output data register (SODR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIDR Address: 0020 SMC1 Address: 0023 Address: 0021 The SIDR register is used for input of serial data (Initial value: undefined). Address: 0022 Bit 7 Bit 6...
  • Page 60 HARDWARE CONFIGURATION [Bits 1 and 0] PDS1 and PDS0: Bits 1 and 0 are used to select the division of the divider at the front of the baud rate generator. PDS1 PDS0 Select 4 dividing (Initial value) Select 6 dividing Select 13 dividing Select 65 dividing 2–...

  • Page 61: Table 2-6 Operation Modes Of Uart

    HARDWARE CONFIGURATION (4) Description of operation Peripherals (a) Operation modes The UART has the operation modes listed in Table 2–6; they can be switched by setting the value at the serial mode control register 1 (SMC1). Table 2–6 Operation Modes of UART Mode Parity Data Length...

  • Page 62: Fig. 2.16 Orfe Flag Set Timing

    HARDWARE CONFIGURATION Peripherals Data Data Stop Stop RDRF = 1 RDRF = 0 ORFE ORFE SIN interrupt SIN interrupt (Overrun error) (Framing error) Fig. 2.16 ORFE Flag Set Timing b. Transmission When the next data is ready to write after data written to the SODR (serial output data register) is transferred to the interrupt shift register, the TDRE (transmit data register empty) flag is set and an interrupt request is output to the CPU.

  • Page 63: Table 2-7 Clock Division Ratio

    HARDWARE CONFIGURATION As shown in the figure, data transfer starts from the start bit (Low-level data), the data bit length specified by the LSB first is transferred, and transfer ends Peripherals at the stop bit (High-level data). In asynchronous transfer, the relationship between SCK and SI is not as shown in the above figure.

  • Page 64: Table 2-9 Selection Of Baud Rate (When Dedicated Baud Rate Generate Used)

    HARDWARE CONFIGURATION Peripherals Table 2–9 Selection of Baud Rate (When Dedicated Baud Rate Generate Used) Division Baud rate (bps) Remarks ratio 4.9152 MHz 5 MHz Clock 1/65 PDS division 1/64 1/16 CS,CR division 9600 78125 2404 4800 39063 1202 2400 19531 1200 9766...

  • Page 65: 8-Bit Serial I/O

    HARDWARE CONFIGURATION 2.2.5 8-bit Serial I/O Peripherals • 8-bit serial data synchronous transfer. • LSB first or MSB first can be selected for data transfer. • The 4 shift-clock mode can be selected (three internal and one external). (1) Block diagram Internal-data bus D7 to D0 D0 to D7...
  • Page 66 HARDWARE CONFIGURATION (3) Description of registers The detail of each register is described below. Peripherals (a) Serial-mode register (SMR) Address: 001C The SMR is used to control serial I/O. Address: 001D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 67 HARDWARE CONFIGURATION [Bit 4] SOE: Serial-data output-enable bit This bit is used to control the output pin for serial I/O. Peripherals General-purpose port pin (P44) SO (serial data) output pin When using P43/SI pin as SI pin, always set the DDR4 to input (bit 3 of DDR4 = 0).
  • Page 68 HARDWARE CONFIGURATION (4) Description of operation The operation of 8-bit serial I/O is described below. Peripherals (a) Outline This module consists of the serial-mode register (SMR) and serial-data register (SDR). At serial output, data in the SDR is output in bit serial to the serial output pin (SO) in synchronization with the falling edge of a serial shift-clock pulse generated from the internal or external clock.
  • Page 69 HARDWARE CONFIGURATION (c) Interrupt functions Peripherals This module can output an interrupt request to the CPU. To output an interrupt request, set the SIOE bit (bit 6) of the SMR to 1 to enable an interrupt and then set the interrupt flag SIOF bit (bit 7) of the SMR after 8-bit data transfer is terminated.

  • Page 70: Fig. 2.19 Shift Start/Stop Timing

    HARDWARE CONFIGURATION Peripherals [When transfer suspended] SIOF Note: When data is written at the SDR, the output data changes at the falling edge of the external-clock pulse. Fig. 2.19 Shift Start/Stop Timing (e) Input/output shift timing Data is output from the serial output pin (SO) at the falling edge of the shift- clock pulse, and is input from the serial input pin (SI) to the SDR at the rising edge of the shift-clock pulse.

  • Page 71: External Interrupt

    HARDWARE CONFIGURATION 2.2.6 External Interrupt Peripherals • The edges of external-interrupt sources can be detected to set the corresponding flag. • An interrupt can be generated at the same time the flag is set. • The interrupts can release the STOP or SLEEP mode. (1) Block diagram P46/INT0 P42/PWC/INT1...
  • Page 72 HARDWARE CONFIGURATION [Bit 7] EIR1: External-interrupt request flag Peripherals When the edge specified by the SL11 and SL10 bits is input to the INT1 pin, bit 7 is set to 1. When the EIE1 bit is 1, an interrupt request (IRQ1) is output if this bit is set.
  • Page 73 HARDWARE CONFIGURATION [Bits 2 and 1] SL01 and SL00: Edge-polarity mode select bits Peripherals Bit 2 and bit 1 are used to control the input edge polarity mode of the INT0 pin. When internal pull-up resistors option is chosen for P42 or P46, only falling edge can wake up the CPU from stop mode or sleep mode.

  • Page 74: Lcd Controller/Driver

    HARDWARE CONFIGURATION 2.2.7 LCD Controller/driver Peripherals The LCD controller/driver consists of the display controller that generates segment and common signals according to the display data and memory data, and the segment and common drivers that can drive the LCD panel directly.
  • Page 75 HARDWARE CONFIGURATION (2) Registers Peripherals 8 bits Address: 0079 LCDR R/W LCD control register Address: 007A SEGR R/W Segment output select register (3) Description of registers The detail of LCD control register is described below. (a) LCD control register (LCDR) Address: 0079 LCDR Bit 7...
  • Page 76 HARDWARE CONFIGURATION [Bits 3 and 2] MS1 and MS0: Display mode select bit These bits are used to select display mode. The mode is set according to Peripherals the following table. Display mode Number of time divisions: N LCD stop —...
  • Page 77 HARDWARE CONFIGURATION (4) RAM for display Peripherals The LCD controller/driver contains the 21 × 8-bit RAM for generating a segment output signal. The data of this RAM is automatically read in synchronization with the common signal select timing and the waveform corresponding to this data is output from the segment output pin.
  • Page 78 HARDWARE CONFIGURATION (5) Operation Peripherals First, write the data to be displayed to display RAM. Then, set the value corresponding to the LCD panel to be used to LCDR (LCD control register). The LCD drive waveform is output according to the data in the display RAM, when the clock pulse is supplied.

  • Page 79: Fig. 2.22 Example Of Waveform At Pin Corresponding To The Ram Data For Display

    HARDWARE CONFIGURATION (6) LCD drive output waveform Peripherals (a) Waveform at 1/2 bias and 1/2 duty COM3 COM2 COM1 COM0 — — — — COM0 COM1 COM2 COM3 n + 1 1 frame Fig. 2.22 Example of Waveform at Pin Corresponding to the RAM Data for Display 2–...

  • Page 80: Fig. 2.23 Example Of Waveform At Pin Corresponding To The Ram Data For Display

    HARDWARE CONFIGURATION (b) Waveform at 1/3 bias and 1/3 duty Peripherals COM3 COM2 COM1 COM0 — — COM0 COM1 COM2 COM3 n + 1 1 frame Fig. 2.23 Example of Waveform at Pin Corresponding to the RAM Data for Display 2–...

  • Page 81: Fig. 2.24 Example Of Waveform At Pin Corresponding To The Ram Data For Display

    HARDWARE CONFIGURATION (c) Waveform at 1/3 bias and 1/4 duty Peripherals COM3 COM2 COM1 COM0 COM0 COM1 COM2 COM3 n + 1 1 frame Fig. 2.24 Example of Waveform at Pin Corresponding to the RAM Data for Display 2– 66...

  • Page 82: Fig. 2.25 Connection Examples For Supply Power For Driving Lcd

    HARDWARE CONFIGURATION (7) Voltage setting at power pins (V3, V2 and V1) for driving LCD Peripherals Set the voltages at the LCD power pins (V3, V2 and V1) as shown below. 1/2 bias 1/2 V 1/2 V 1/3 bias 2/3 V 1/3 V : LCD operating voltage A connection example for supply power to drive the LCD is shown in...

  • Page 83: Fig. 2.26 Built-In Voltage Dividing Resistors

    HARDWARE CONFIGURATION Peripherals VSEL Internal-equivalent circuit Fig. 2.26 Built-in Voltage Dividing resistors 2– 68...

  • Page 84: Time-Base Timer

    HARDWARE CONFIGURATION 2.2.8 Time-base Timer Peripherals • This timer has a 20-bit binary counter and uses a clock pulse with 1/2 oscillation of the main clock. • Can be selected from four interval times • This function cannot be used when the main clock is stopped. (1) Block diagram TBTC* 20-bit counter...
  • Page 85 HARDWARE CONFIGURATION (3) Description of registers Peripherals The detail of time-base timer control register (TBCR) is described below. (a) Time-base timer control register (TBCR) Address: 000A TBCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 —...

  • Page 86: Watchdog Timer Reset

    HARDWARE CONFIGURATION 2.2.9 Watchdog Timer Reset Peripherals A watchdog reset is generated using the output of the time-based timer as a clock pulse. (1) Block diagram WTE3 to WTE0 Start Time-base timer 2-bit counter Reset control (2) Registers The watchdog timer reset has one watchdog timer control register (WDTE). 8 bits Address: 0009 WDTE...
  • Page 87 HARDWARE CONFIGURATION (4) Description of operation Peripherals The watchdog timer enables the detection of program malfunction. (a) Starting watchdog timer The watchdog timer starts when 0101 is written at the watchdog timer control bits. (b) Clearing watchdog timer When 0101 is written at the watchdog timer control bits after start, the watchdog timer is cleared.

  • Page 88: Operation

    3. OPERATION 3.1 Clock Pulse Generator ............3-3 3.2 Reset ..................3-4 3.3 Interrupt ..................3-6 3.4 Low-power Consumption Modes ...........3-8 3.5 Pin States For Sleep, Stop, and Reset ........3-9...

  • Page 89: Clock Pulse Generator

    OPERATION The operation of MB89950 is described below. 3.1 Clock Pulse Generator The MB89950 series of microcontrollers contain the system clock pulse generator. The crystal oscillator is connected to the X0 and X1 pins to generate clock pulses. Clock pulses can also be supplied internally by inputting externally-generated clock pulses to the X0 pin.

  • Page 90: Reset

    OPERATION 3.2 Reset The detail of reset operation and reset sources are described below. 3.2.1 Reset Operation When reset conditions occur, the MB89950 series of microcontrollers suspend the currently-executing instruction to enter the reset state. The contents written at the RAM do not change before and after reset. However, if a reset occurs during writing of 16-bit long data, data is written to the upper bytes and may not be written to lower bytes.

  • Page 91: Reset Sources

    OPERATION 3.2.2 Reset Sources The MB89950 series of microcontrollers have the following reset sources. (1) External pin When a Low level is input to the RST pin (2) Specification by software When 0 is written at the RST bit of the standby-control register (3) Power-on Power on when the power-on reset option is selected (4) Watchdog function...

  • Page 92: Interrupt

    OPERATION 3.3 Interrupt If the interrupt controller and CPU are ready to accept interrupts when an interrupt request is received from the internal peripherals or an external-interrupt, the CPU finished the currently-executing instruction and executes the interrupt-processing program. Fig. 3.4 shows the interrupt-processing flowchart. Internal bus Interrupt Main program...

  • Page 93: Table 3-1 Interrupt Sources And Interrupt Vectors

    OPERATION Table 3–1 lists the relationships between each interrupt source and interrupt vector. Table 3–1 Interrupt Sources and Interrupt Vectors Upper vector Lower vector Interrupt Source address address IRQ0 (External interrupt 0) FFFA FFFB IRQ1 (External interrupt 1 FFF8 FFF9 IRQ2 (8-bit PWM timer) FFF6 FFF7...

  • Page 94: Low-Power Consumption Modes

    OPERATION 3.4 Low-power Consumption Modes The MB89950 series of microcontrollers have two standby modes: sleep and stop to reduce the power consumption. Writing to the standby control register (STBC) gives a transition to these two standby modes. See section 2.1.4 for setting and releasing each mode. Whether or not an oscillation stabilization period is required at release from each low-power consumption mode depends on the mask option of the power-on reset (See page 2-9).

  • Page 95: Pin States For Sleep, Stop And Reset

    OPERATION 3.5 Pin States For Sleep, Stop, and Reset The state of each pin of the MB89950 series of microcontrollers at sleep, stop and reset is as follows: (1) Sleep The pin state immediately before the sleep state is held. (2) Stop The pin state immediately before the stop state is held when the stop mode is started and bit 5 of the standby-control register (STBC) is set to...

  • Page 96: Instructions

    4. INSTRUCTIONS 4.1 Legend .................. 4-3 4.2 Transfer Instructions .............. 4-4 4.3 Operation Instructions ............4-5 4.4 Branch Instructions ..............4-6 4.5 Other Instructions ..............4-7 4.6 F MC-8L Family Instruction Map ........... 4-8...

  • Page 97: Legend

    INSTRUCTIONS 4.1 Legend Symbol Meaning Extended addressing (addresses 0000 to FFFF) Direct addressing (addresses 0000 to 00FF) dir : n Direct bit addressing (bit position: n = 0 to 7) Relative addressing (8 bits) Immediate addressing, vector addressing Upper byte of A Lower byte of A Lower byte of T Register indirect addressing...

  • Page 98: Transfer Instructions

    INSTRUCTIONS 4.2 Transfer Instructions OP Code Mnemonic Operation N Z V C (dir) ← (A) MOV dir,A - - - - ((IX)+off) ← (A) MOV @IX+off,A - - - - (ext) ← (A) MOV ext,A - - - - ((EP)) ← (A) MOV @EP,A - - - - (Ri) ←...

  • Page 99: Operation Instructions

    INSTRUCTIONS 4.3 Operation Instructions OP Code Mnemonic Operation N Z V C (A) ← (A)+(Ri)+C ADDC A,Ri + + + + 28 to 2F (A) ← (A)+d8+C ADDC A,#d8 + + + + (A) ← (A)+(dir)+C ADDC A,dir + + + + (A) ←...

  • Page 100: Branch Instructions

    INSTRUCTIONS 4.4 Branch Instructions OP Code Mnemonic Operation N Z V C BZ/BEQ rel if Z=1 then PC←PC+rel - - - - BNZ/BNE rel if Z=0 then PC←PC+rel - - - - BC/BLO rel if C=1 then PC←PC+rel - - - - BNC/BHS rel if C=0 then PC←PC+rel - - - -...

  • Page 101: Other Instructions

    INSTRUCTIONS 4.5 Other Instructions OP Code Mnemonic Operation N Z V C SP ← SP-2(SP) ← A PUSHW A - - - - ← (SP) SP ← SP + 2 POPW - - - - SP ← SP-2(SP) ← IX PUSHW IX - - - - IX ←...

  • Page 102: F 2 Mc-8L Family Instruction Map

    INSTRUCTIONS 4.6 F MC-8L Family Instruction Map 4– 8...

  • Page 103: Mask Options

    5. MASK OPTIONS...

  • Page 104: Table 5-1 Mask Options

    O = Mask option is selected for port outputs *1 This column of numbers assume that all the multiplexed peripherals are disabled. If any customer want to choose the mask option combination which is not shown in Table 5–2, please inform Fujitsu for special testing arrangement. 5– 3...

  • Page 105: Appendix

    APPENDIX...

  • Page 106: Appendix A I/O Map

    APPENDIX Appendix A I/O Map Addresses Address Read/Write Register Description of register (R/W) PDR0 Port-0 data register (R/W) PDR1 Port-1 data register (R/W) PDR2 Port-2 data register (R/W) STBC Standby control register (R/W) WDTC Watchdog timer control register (R/W) TBCR Time-base timer control register (R/W) PDR3...
  • Page 107 APPENDIX (continued) Address Read/Write Register Description of register (R/W) SIDR/SODR UART serial data register (R/W) SMC2 UART serial mode control register 2 (R/W) EIC1 External interrupt 1 control register 1 to 63 (R/W) VRAM Display data RAM to 78 (R/W) LCDR LCD control register (R/W)

  • Page 108: Appendix B Writing Eprom

    APPENDIX Appendix B Writing EPROM Functions equivalent to the MBM27C256A can be used in the MB89P955 EPROM mode. Accordingly, the user can write data with a general-purpose EPROM writer by using a dedicated adapter. Note that the electrical signature mode is not supported. •...
  • Page 109 APPENDIX • Bit Map for PROM Option Power-on 3FF0 Vacant Vacant Vacant Oscillation Reset pin Output Vacant Vacant Reset stabilization time Readable/ Readable/ Readable/ 1: 2 1:Available Readable/ Readable/ 1:Available Writable Writable Writable 0: 2 0:Unavailable Writable Writable 0:Unavailable Vacant Pull-up Pull-up Pull-up...
  • Page 110 FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel:(06103)690-0 Fax:(06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel:336-1600 Fax:336-1609 F9603 © FUJITSU LIMITED Printed in Japan...

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