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Fujitsu MB89140 Series Hardware Manual

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FUJITSU SEMICONDUCTOR
CM25–10113–1E
MICROCONTROLLER MANUAL
2
F
MC-8L FAMILY
MICROCONTROLLERS
MB89140 SERIES
HARDWARE MANUAL

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Summary of Contents for Fujitsu MB89140 Series

  • Page 1 FUJITSU SEMICONDUCTOR CM25–10113–1E MICROCONTROLLER MANUAL MC-8L FAMILY MICROCONTROLLERS MB89140 SERIES HARDWARE MANUAL...
  • Page 2 Edition 1.0 February 1995 1995 FUJITSU DEVICES Inc. All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable.
  • Page 3 PREFACE The terms in this manual are defined as follows: (1) A clock cycle is one clock cycle of the oscillation frequency. (2) A system clock cycle is the clock frequency divided by the gear function (see 2.2). One cycle time of the system clock varies with the settings of the CS1 and CS0 bits of the SYCC register.

  • Page 4: Table Of Contents

    Table of Contents 1. GENERAL ............1.1 FEATURES .
  • Page 5 ......Table 1-1 Types and Functions of MB89140 Series of Microcontrollers (Continued) ....
  • Page 6 Fig. 2.1 Memory Space of MB89140 Series of Microcontrollers ....... .

  • Page 7: General

    1. GENERAL 1.1 FEATURES ........1.2 PRODUCT SERIES .

  • Page 8: Features

    GENERAL The MB89140 series of single-chip microcontrollers use the F MC-8L CPU core to enable high-speed proces- sing at low voltages, and features a 25 segment VFD (Vacuum Fluorescent Display) driver. They contain re- sources such as timers, a serial interface, an A/D converter and an external interrupt input to provide a wide variety of applications for commercial and industrial equipment, including portable equipment.

  • Page 9: Fig. 1.1 Mb89140 Series

    GENERAL (Under development) (Planned) (Under development) MB89147 (Planned) MB89146 MB89145 ROM 24K ROM 32K MB89144 RAM 768 RAM 1K ROM 16K RAM 512 Memory capacity ROM 12K Small Large RAM 256 Fig. 1.1 MB89140 series...

  • Page 10: Product Series

    GENERAL 1.2 PRODUCT SERIES Table 1-1 lists the types and functions of the MB89140 series of microcontrollers. Table 1-1 Types and Functions of MB89140 Series of Microcontrollers MB89P147 Model Name MB89144 MB89145 MB89146 MB89147 MB89PV140 MB89W147 Piggyback/evaluation Mass-produced product OTPROM/...

  • Page 11: Table 1-1 Types And Functions Of Mb89140 Series Of Microcontrollers (Continued)

    GENERAL Table 1-1 Types and Functions of MB89140 Series of Microcontrollers (Continued) MB89P147 Model Name MB89144 MB89145 MB89146 MB89147 MB89PV140 MB89W147 8-bit length 1 channel Serial I/O Transfer clock (external, 4, 8 or 16 system clock cycles) 10-bit resolution, 12 channels A/D conversion mode (conversion time: 16.5 µs at 8 MHz and maximum gear speed)

  • Page 12: Fig. 1.2 Block Diagram

    GENERAL 1.3 BLOCK DIAGRAM Internal bus Main clock oscillator Time-base timer (Max. 8 MHz) Clock control Buzzer P70, P71 Sub clock oscillator High-withstand-voltage P60 to P67 (32.768 kHz) port 6 Port CMOS input port High-withstand-voltage P50 to P57 port 5 P23/WDG CMOS output port High-withstand-voltage...

  • Page 13: Fig. 1.3 Pin Assignment (Dip-64P-M01, Mdp-64C-P02)

    GENERAL 1.4 PIN ASSIGNMENT TOP VIEW A15/VAA P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/AN8 P11/AN9 P12/ANA P13/ANB Items in dotted lines are only available for the MB89PV140. P17/ADST P30/INT0/TRG P31/INT1 P32/SCK P33/SO P34/SI P35/EC P36/PWO1 P23/WDG P37/DTTI P21/PWO0 MODA P70/X0A P71/X1A...

  • Page 14: Fig. 1.4 Pin Assignment (Fpt-64P-M06, Mdp-64C-P01)

    GENERAL /AN1 P00/ P02/ 64 63 62 61 60 59 58 57 56 55 54 53 52 TOP VIEW P03/AN3 P04/AN4 P05/AN5 P06/AN6 84 83 82 81 80 79 78 P07/AN7 P10/AN8 P11/AN9 P12/ANA P13/ANB P17/ADST P30/INT0/TRG P31/INT1 94 95 96 65 66 67 68 P32/SCK P33/SO Items in dotted lines are only...

  • Page 15: Pin Function Description

    GENERAL 1.5 PIN FUNCTION DESCRIPTION Table 1-2 and NO TAG lists the pin function and Figure 1.3 shows the input/output circuit configurations. Table 1-2 Pin Function Description Pin No. Circuit Pin Name Function type SDIP Used for main clock oscillation A crystal resonator should be used.
  • Page 16 GENERAL Table 1-2 Pin Function Description (Continued) Pin No. Circuit Pin Name Function type SDIP General-purpose I/O port Input is hysteresis type containing a noise filter. When overcurrent is P37/DTTI detected, the external rising or falling edge can be input to inactivate the 12-bit MPG output.
  • Page 17 GENERAL Table 1-2 Pin Function Description (Continued) Pin No. Circuit Pin Name Function type SDIP SDIP — Used for power supply — Used for power supply (GND) — Used for power supply for A/D converter Used for power supply for A/D converter —...

  • Page 18: Table 1-3 Pin For External-Rom

    GENERAL Table 1-3 Pin for External-ROM Pin No. Circuit Pin Name Function type SDIP Output High-level output pin Output Address-output pins Input Data-input pins Output Power (GND) pin Input Data-input pins Output Chip-enable pin for ROM A High level is output in the standby mode. Output Address-output pin Output...

  • Page 19: Fig. 1.5 Input/Output Circuit Configurations

    GENERAL Classification Circuit Remarks Feedback resistor: About 2 MΩ Standby control signal CMOS input Output pull-up resistor (Pch): About 50 kΩ (5 V) CMOS hysteresis input (with noise filter) Hysteresis input (with noise filter) CMOS output N-ch open drain output CMOS hysteresis input (with noise filter) Hysteresis input (with noise filter) CMOS output...
  • Page 20 GENERAL Classification Circuit Remarks P-channel high-withstand-voltage open-drain output Microcontrollers with and without pull-down resis tor provided (excluding MB89V140 microcontroller) P-channel high-withstand-voltage open-drain output CMOS output CMOS hysteresis input (with noise filter) The pull-up resistor is optional. Port Hysteresis input (with noise filter) Port CMOS hysteresis input (with noise filter) Hysteresis input (with noise filter)

  • Page 21: Handling Devices

    GENERAL 1.6 HANDLING DEVICES (1) Preventing latch-up Latch-up may occur if a voltage higher than V or lower than V is applied to the input or output pins other than port 40 to 47, or if voltage exceeding the rated value is applied between V and V .

  • Page 22: Hardware Configuration

    2. HARDWARE CONFIGURATION ......... . MAIN/SUB CLOCK CONTROL BLOCK .

  • Page 23: Fig. 2.1 Memory Space Of Mb89140 Series Of Microcontrollers

    Memory Space The MB89140 series of microcontrollers have a memory area of 64K bytes. All I/O, data, and program areas are located in this space. The I/O area is near the lowest address and the data area is immediately above it. The data area may be divided into register, stack, and direct-address areas according to the applications.

  • Page 24: Table 2-1 Table Of Reset And Interrupt Vectors

    HARDWARE CONFIGURATION I/O area This area is where various resources such as control and data registers are located. The memory map for the I/O area is given in APPENDIX A. RAM area This area is where the static RAM is located. Addresses from 0100 are also used as the general-purpose register area.

  • Page 25: Fig. 2.2 Arrangement Of 16-Bit Data In Memory

    HARDWARE CONFIGURATION Arrangement of 16-bit Data in Memory When the MB89140 series of microcontrollers handle 16-bit data, the data written at the lower address is treated as the upper data and that written at the next address is treated as the lower data as shown in Figure 2.2.

  • Page 26: Fig. 2.4 Structure Of Processor Status

    HARDWARE CONFIGURATION Internal Registers in CPU The MB89140 series of microcontrollers have dedicated registers in the CPU and general-purpose registers in memory. Program counter (PC) 16-bit long register indicating location where instructions stored Accumulator (A) 16-bit long register where results of opera- tions stored temporarily;...

  • Page 27: Fig. 2.5 Rule For Translating Real Addresses At General-Purpose Register Area

    HARDWARE CONFIGURATION The RP indicates the address of the current register bank and the contents of the RP; the real addresses are translated as shown in Figure 2.5. Lower bits of OP code ’0’ ’0’ ’0’ ’0’ ’0’ ’0’ ’0’ ’1’...

  • Page 28: Fig. 2.6 Register Bank Configuration

    The 8-bit long general-purpose registers are in the register banks in memory. One bank has eight registers and up to 32 banks are available for the MB89140 series of microcontrollers, respectively. The register bank pointer (RP) indicates the currently-used bank.

  • Page 29: Fig. 2.7 Memory Map In Various Modes

    HARDWARE CONFIGURATION Operation Modes The MB89140 series of microcontrollers is used in the single-chip mode. The memory map for each mode is as follows: Address MB89PV140 Address MB89146 Address MB89145 0000 0000 0000 Internal I/O Internal I/O Internal I/O 0080...
  • Page 30 HARDWARE CONFIGURATION As shown in the flowchart below, the single-chip mode is set according to the status of the device mode pins and the mode data fetched during the reset sequence. Setting Mode selected Mode pin Mode data procedure (1) (2) Single-chip mode XXXXX000 Power-on...

  • Page 31: Fig. 2.8 Machine Clock Control Block Diagram

    HARDWARE CONFIGURATION 2.2 MAIN/SUB CLOCK CONTROL BLOCK MAIN/SUBCLOCK CONTROL BLOCK This block controls the standby operation, oscillation stabilization time, software reset, and clock switching. Block Diagram Pin state Prescaler Main clock Clock pulse generator specification Watch Selector Sleep Stop 1/32 CPU operation clock Subclock Selector...
  • Page 32 HARDWARE CONFIGURATION Description of Registers MAIN/SUBCLOCK CONTROL BLOCK The detail of each register is described below. (1) Standby-control register (STBC) Address: 0007 SYCC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — —...
  • Page 33 HARDWARE CONFIGURATION [Bit 3] TMD: Watch bit MAIN/SUBCLOCK This bit is used to specify switching to the watch mode. CONTROL BLOCK No operation Watch mode Writing at this bit is possible only in the submode (SCS = 0). 0 is always read when this bit is read.
  • Page 34 HARDWARE CONFIGURATION [Bit 2] SCS: System clock select bit MAIN/SUBCLOCK This bit is used to select the system clock mode. CONTROL BLOCK Selects subclock (32.768 kHz) mode Selects main clock (8 MHz) mode [Bits 1 and 0] CS1 and CS0: System clock select bits (Gear function) If the main mode is specified by the system clock select bit (SCS), the sys- tem clock is as given in the table below.

  • Page 35: Table 2-2 Operating State Of Low-Power Consumption Modes

    HARDWARE CONFIGURATION Description of Operation MAIN/SUBCLOCK CONTROL BLOCK Main/sub clock block has normal and low-power consumption mode. The low-power consumption mode are described below. (1) Low-power consumption mode This chip has three operation modes. The sleep mode, and stop mode in the table below reduce the power consumption.
  • Page 36 HARDWARE CONFIGURATION (a) WATCH mode MAIN/SUBCLOCK CONTROL BLOCK Switching to WATCH mode – Writing 1 at the TMD bit of the STBC register switches the mode to WATCH mode. Writing is invalid if 1 is set at the SCS bit (bit 2) of the SYCC register.
  • Page 37 HARDWARE CONFIGURATION Canceling SLEEP mode MAIN/SUBCLOCK – The SLEEP mode is canceled by inputting the reset signal and re- CONTROL BLOCK questing an interrupt. – When the reset signal is input during the SLEEP mode, the CPU is switched to the reset state and the SLEEP mode is canceled. –...
  • Page 38 HARDWARE CONFIGURATION – If the STOP mode is canceled by inputting the reset signal, the CPU is MAIN/SUBCLOCK switched to the oscillation stabilization wait state. Therefore, the reset CONTROL BLOCK sequence is not executed unless the oscillation stabilization time is elapsed.
  • Page 39 HARDWARE CONFIGURATION (3) State transition diagram at low power consumption mode MAIN/SUBCLOCK CONTROL BLOCK (24) (27) Main SLEEP Sub SLEEP WATCH Main oscillate Main stop Main stop Sub oscillate Sub oscillate Sub oscillate (28) (25) Main STOP (26) (29) Main stop Sub oscillate (16) (15)

  • Page 40: Table 2-3 Sources Of Reset

    HARDWARE CONFIGURATION Reset Control Section MAIN/SUBCLOCK CONTROL BLOCK Power-on reset Watchdog timer reset Reset control Internal reset signal External reset Software reset Reset There are four types of resets as shown in Table 2-3. Table 2-3 Sources of Reset Reset name Description Power-on reset Turns power on...
  • Page 41 HARDWARE CONFIGURATION Single Clock MAIN/SUBCLOCK CONTROL BLOCK The single clock can be selected by the mask option. In the single clock op- eration, the functions are the same as those of the double clock module ex- cept that the subclock mode cannot be set. In the single-circuit clock opera- tion, the P71/X1A and P70/X0A function as input ports.

  • Page 42: Fig. 2.9 Interrupt Controller Block Diagram

    HARDWARE CONFIGURATION 2.3 INTERRUPT CONTROLLER INTERRUPT CONTROLLER The interrupt controller for the F MC-8L family is located between the MC-8L CPU and each resource. This controller receives interrupt re- quests from the resources, assigns priority to them, and transfers the priority to the CPU;...
  • Page 43 HARDWARE CONFIGURATION Description of Registers INTERRUPT CONTROLLER The detail of each register is described below. Interrupt level register (ILRX: Interrupt Level Register X) Address: 007C ILR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address: 007C Address: 007D...

  • Page 44: Fig. 2.10 Interrupt-Processing Flowchart

    (g)When an interrupt source is cleared by software in the user’s interrupt processing routine, the CPU terminates the interrupt processing. Figure 2.10 outlines the interrupt operation for the MB89140 series of micro- controllers. Internal bus...

  • Page 45: Table 2-4 List Of Port Functions

    2.4 I/O PORTS I/O PORTS The MB89140 series of microcontrollers have eight parallel ports (55 pins, including a buzzer pin). Ports 0, 1 and 3 serve as CMOS I/O ports; port 2 serves as a CMOS output-only port; ports 4, 5 and 6 serve as P- channel open-drain high-withstand-voltage ports;...

  • Page 46: Table 2-5 Port Register

    HARDWARE CONFIGURATION Register list I/O PORTS I/O port consists of the following registers. Table 2-5 Port register read/ Initial val- Register name Address write Ports 00 to 07 data register (PDR0) 0000 XXXXXXXX Ports 00 to 07 data direction register (DDR0) 0001 00000000 Ports 10 to 17 data register...
  • Page 47 HARDWARE CONFIGURATION These registers enable P07 to P00 and P13 to P10 to be used as general- I/O PORTS purpose port inputs after resetting. Write 1 at bits corresponding to each pin. Register value Status Used as analog input port. Inhibited for use as general- purpose port input.

  • Page 48: Fig. 2.11 Ports 00 To 07 And 10 To 13

    HARDWARE CONFIGURATION Analog input I/O PORTS When using as an analog input, set 0 at the DDR to turn off the output tran- sistor. If the bits of the PCR0 and PCR1 registers corresponding to the ports to be used as analog inputs are 1, write 0 at these registers to inhibit use as general-purpose input ports.

  • Page 49: Fig. 2.12 Ports 14 To 16

    HARDWARE CONFIGURATION State in stop modes I/O PORTS With the SPL bit of the standby-control register set to 1, in the stop mode, the output impedance goes High irrespective of the value of the DDR. Internal data bus Pull-up resistor (option) PDR read Input buffer (hysteresis)

  • Page 50: Fig. 2.14 Ports 70 And 71

    HARDWARE CONFIGURATION (4) P70 and P71: CMOS-type input ports I/O PORTS Input port operation The PDR can only be read and the value of the pin is always read. Note: When the dual-circuit clock option is selected, P71 and P70 serve as X1A and X0A pins.

  • Page 51: Fig. 2.15 Ports 35 To 32, 30 And 17

    HARDWARE CONFIGURATION Resource input operation I/O PORTS The pin value at a port with the resource input function is always input for the resource input irrespective of the setting of the DDR and resource. Set the DDR to input when using an external signal for the resource input. State when reset When reset, the DDR is initialized to 0 and the output impedance goes High at all bits.

  • Page 52: Fig. 2.16 Port 31

    HARDWARE CONFIGURATION Operation for input port (DDR = 0) I/O PORTS When used as the input port, the output impedance goes High. There- fore, when the PDR is read, the value of the pin is read. Resource input operation This pin is used both as a resource input and as a port. The value of the pin is always input to the port serving as the resource input (irrespective of the setting conditions of the PDR and resource).

  • Page 53: Fig. 2.17 Ports 40 To 47, 50 To 57 And 60 To 67

    HARDWARE CONFIGURATION State in watch mode I/O PORTS When the SPL bit of the standby-control register is set to 1, in the stop mode, the output impedance goes High irrespective of the value of the PDR. Internal data bus PDR read Output latch Pull-down resistor PDR write...

  • Page 54: Fig. 2.19 Watch Prescaler Block Diagram

    HARDWARE CONFIGURATION 2.5 WATCH PRESCALER WATCH PRESCALER This prescaler has a 15-bit binary counter Four interval times and three clock pulses can be selected. This function cannot be used when the single clock module is selected by the mask option. Block Diagram Subclock (L0) 31.25 ms...
  • Page 55 HARDWARE CONFIGURATION [Bit 7] WIF: Watch interrupt flag WATCH When writing, this bit is used to clear the watch interrupt flag. PRESCALER Clears watch interrupt flag No operation When reading, this bit indicates that the watch interrupt has occurred. Watch interrupt not occurred Watch interrupt occurred 1 is read when the Read Modify Write instruction is read.

  • Page 56: Fig. 2.20 Watchdog Timer Reset Block Diagram

    HARDWARE CONFIGURATION 2.6 WATCHDOG TIMER RESET WATCHDOG TIMER RESET Either of a signal output from the time-base timer for counting with the main clock or a signal output from the watch prescaler for counting with the subclock can be selected as a clock. It is possible to select whether or not a watchdog time-out detect signal is output (only when power-on reset available option selected).
  • Page 57 HARDWARE CONFIGURATION [Bit 7] CS: Clock source switching bit WATCHDOG TIMER This bit is used to select a count clock from either the watch prescaler or RESET time-base timer. Time-base timer cycle = 1/2 Watch prescaler cycle = 1/2 : Main clock frequency : Subclock frequency Note: Set this bit as soon as the watchdog timer is started.
  • Page 58 HARDWARE CONFIGURATION [Bits 3 to 0] WTE3 to WTE0: Watchdog timer control bit WATCHDOG TIMER These bits are used to control the watchdog timer. RESET First write only after reset Watchdog timer started 0101 No operation Other than the above Second and later write Watchdog timer counter cleared 0101...
  • Page 59 HARDWARE CONFIGURATION The relationship between the 2-bit counter of the watchdog timer and the WATCHDOG TIMER time-base timer (clock prescaler) is as follows: RESET 524.3 (512) ms CASE 1 Time-base timer output (Clock prescaler) Watchdog clear Watchdog counter Watchdog reset 1049 (1024) ms CASE 2 Time-base timer output...
  • Page 60 HARDWARE CONFIGURATION Set the WDTE register as follows: WATCHDOG TIMER RESET First, set the WDOS bit. (Set WTE3 to WTE0 to a value other than 0101. Do not set the CS bit.) Do not perform this operation at a time-out. Set the CS bit concurrently with starting the watchdog timer.

  • Page 61: Fig. 2.21 Time-Base Timer Block Diagram

    HARDWARE CONFIGURATION 2.7 TIME-BASE TIMER TIME-BASE TIMER This timer has a 21-bit binary counter and uses a clock pulse with 1/2 os- cillation of the main clock. Four interval times can be selected. This function cannot be used when the main clock is stopped. The clock source of this timer does not change even with a gear change (1/2 oscillation frequency).
  • Page 62 HARDWARE CONFIGURATION Description of Registers TIME-BASE TIMER The detail of time-base timer control register (TBCR) is described below. (1) Time-base timer control register (TBCR) Address: 000A TBCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBOF TBIE...

  • Page 63: Fig. 2.22 8-Bit Pwm Timer (Timer 1) Block Diagram

    HARDWARE CONFIGURATION 2.8 8-BIT PWM TIMER (TIMER 1) 8-Bit PWM TIMER (TIMER 1) This timer can be used as an 8-bit timer or PWM controller with 8-bit reso- lution. Four clock pulses can be selected. Block Diagram Internal data bus CNTR P/TX —...
  • Page 64 HARDWARE CONFIGURATION Description of Register 8-Bit PWM TIMER (TIMER 1) The detail of watch prescaler is described below. (1) Control register (CNTR) Address: 0016 COMR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P/TX —...
  • Page 65 HARDWARE CONFIGURATION 1 is always read when the Read Modify Write instruction is read. 8-Bit PWM TIMER (TIMER 1) The meaning of each bit to be written is as follows: This bit is cleared. This bit does not change or affect other bits. Note: In the PWM operation mode, neither the read nor write values of this bit have any meaning.

  • Page 66: Fig. 2.23 Timer Operation

    HARDWARE CONFIGURATION Operation description 8-Bit PWM TIMER (TIMER 1) (1) Timer operation Setting the P/TX bit of the CNTR to 1, gives the timer operation mode is per- formed. When the TPE bit of the CNTR is set to 1, the counter starts incre- menting from 00H.

  • Page 67: Fig. 2.24 Pwm Pulse Output

    HARDWARE CONFIGURATION When COMR 8-Bit PWM TIMER (TIMER 1) Counter value PWM pulse output When COMR Counter value PWM pulse output When COMR Counter value PWM pulse output Fig. 2.24 PWM Pulse Output The TIR bit of the CNTR in the PWM operation mode has no meaning. No interrupt occurs irrespective of TIE bit.

  • Page 68: Fig. 2.25 8/16-Bit Timer Block Diagram

    HARDWARE CONFIGURATION 2.9 8/16-BIT TIMER (TIMER 2 AND TIMER 3) 8/16-BIT TIMER (TIMER 2 AND TIMER 3) Three internal clock pulses and one external clock pulse can be selected. External input can be selected from the rising edge, falling edge, or both edges.
  • Page 69 HARDWARE CONFIGURATION Register List 8/16-BIT TIMER 8 bit (TIMER 2 AND TIMER 3) T3CR Address: 0018 R/W Timer-3 control register T2CR Address: 0019 R/W Timer-2 control register T3DR Address: 001A R/W Timer-3 data register T2DR Address: 001B R/W Timer-2 data register Description of Register Details The detail of each register is described below.
  • Page 70 HARDWARE CONFIGURATION [Bit 1] T2STP: Timer-stop bit 8/16-BIT TIMER (TIMER 2 AND TIMER 3) Counting continued without clearing counter Counting suspended [Bit 0] T2STR: Timer-start bit Terminates operation Clears counter and starts operation (2) Timer 3 control register (T3CR) Address: 0018 T3CR Bit 7 Bit 6...
  • Page 71 HARDWARE CONFIGURATION [bit 1] T3STP: Timer stop bit 8/16-BIT TIMER (TIMER 2 AND TIMER 3) Operation continued without clearing counter Count operation suspended [Bit 0] T3STR: Timer start bit Operation stopped Operation started after clearing counter (3) Timer 1 and 2 data registers (T2DR and T2DR) Address: 0018 T3CR Bit 7...

  • Page 72: Fig. 2.26 Description Diagram For Internal Clock Mode Operation

    HARDWARE CONFIGURATION Description of Operation 8/16-BIT TIMER (TIMER 2 AND TIMER 3) (1) 8-bit internal clock mode In the 8-bit internal clock mode, three internal clock inputs can be selected by setting the clock source select bits (T2CS1 and T2CS0, T3CS1 and T3CS0) of the timer control registers (T2CR and T3CR).

  • Page 73: Fig. 2.28 External Cock Mode Operation Description Diagram

    HARDWARE CONFIGURATION (2) 8-bit external clock mode 8/16-BIT TIMER (TIMER 2 AND TIMER 3) In the 8-bit external clock mode, the eternal clock input can be selected three various external clock inputs by setting the clock source select bits (T2CS1 and T2CS0) of the timer 2 control register (T2CR). The external- clock input pin of the timer corresponds to P33/EC.
  • Page 74 HARDWARE CONFIGURATION (3) 16-bit mode 8/16-BIT TIMER (TIMER 2 AND TIMER 3) In the 16-bit mode, each bit of the timer control registers is as shown below. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T2IF T2IE...
  • Page 75 HARDWARE CONFIGURATION 2.10 12-BIT MULTIPUL GENERATOR (MPG, TIMER 4) 12-BIT MULTIPUL GENERATOR A 12-bit-long up timer is provided with one compare clear register for (MPG, TIMER 4) cycle setting and one compare register for output pin control to control one real-time waveform output pin. Four count clock sources can be selected.

  • Page 76: Fig. 2.30 Mpg Block Diagram

    HARDWARE CONFIGURATION Block diagram 12-BIT MULTIPUL GENERATOR (MPG, TIMER 4) MC-8L internal data bus DTTI input: Rising edge Falling edge Control register TSL1 TSL0 CKS1 CKS0 SPOL STRG PCN1 PCN0 Output compare buffer register OUTCBR Output compare register OUTCR Comparator 12-bit 4-bit counter...
  • Page 77 HARDWARE CONFIGURATION Description of registers 12-BIT MULTIPUL GENERATOR (1) Control register (MCNT) (MPG, TIMER 4) This register is used to select the count clock pulse of the timer and the PWM/PPG function, and to control setting of the software trigger. (1) Interrupt level register (ILRX: Interrupt Level Register X) MCNT Address: 0024...
  • Page 78 HARDWARE CONFIGURATION [Bits 5 and 4] CKS1 and CKS0: Count clock pulse select bits 12-BIT MULTIPUL GENERATOR Bits 5 and 4 are used to select the count clock pulse (minimum resolution) in (MPG, TIMER 4) the PWM or PPG operation mode. Clock pulse to be selected Maximum cycle at maximum CKS1 CKS0...

  • Page 79: Fig. 2.31 Transition Of Dtti Input

    HARDWARE CONFIGURATION 12-BIT MULTIPUL GENERATOR (MPG, TIMER 4) PCN1 PCN0 Operation mode (P36/PW01) general-purpose pin state DTTI input ineffective MPG pulse output Effective at rising edge of DTTI input Effective at falling edge of DTTI input PWM operation PPG operation In operation In operation DTTI input...
  • Page 80 HARDWARE CONFIGURATION [Bit 5] CLIE: Compare clear match interrupt enable bit 12-BIT MULTIPUL GENERATOR Bit 5 is used to enable the compare clear match interrupt request. (MPG, TIMER 4) Compare clear match interrupt request disabled Compare clear match interrupt request enabled [Bit 4] CLIR: Compare clear match interrupt request flag Bit 4 is set to 1 when the compare clear match occurs.
  • Page 81 HARDWARE CONFIGURATION (3) Compare clear register (CMCLR) 12-BIT MULTIPUL GENERATOR This register is used to store the compare value of compare clear. (MPG, TIMER 4) When the values of this register and timer agree, the timer is cleared. The Address: 0024 MCNT value is transferred from the buffer register to the compare register.
  • Page 82 HARDWARE CONFIGURATION (5) Output compare register (OUTCR) 12-BIT MULTIPUL GENERATOR This register is used to store the compare value of output compare. (MPG, TIMER 4) When the values of this register and timer agree, the output is set. Address: 0024 MCNT Bit 15 Bit 14...

  • Page 83: Fig. 2.32 Outline Of Pwm Output

    HARDWARE CONFIGURATION Operation description 12-BIT MULTIPUL GENERATOR (1) PWM operation (counting) (MPG, TIMER 4) Timer value Set value to CMCLR + 1 Set value to OUTCR MPG output Output compare match Compare clear timer match Fig. 2.32 Outline of PWM Output As shown in Figure 2.32, the MPG can generate a PWM waveform.

  • Page 84: Fig. 2.34 Flowchart Of Pwm Operation

    HARDWARE CONFIGURATION Select output polarity (SPOL = 1 or 0). 12-BIT MULTIPUL Write data to compare clear buffer register or output buffer register. GENERATOR Setup Select effective edge for external trigger input (ESL1, ESL0). (MPG, TIMER 4) Select trigger source (TSL1, TSL0) % Set/reset MPG output. Enable output to pin (PCN1, PCN0 (0, 0).

  • Page 85: Table 2-6 Relationship Between Value Set At Outcr And Duty

    HARDWARE CONFIGURATION For example, the relationship between the value set at the OUTCR and the 12-BIT MULTIPUL duty with 7F set at the CMCLR is given in Table 2-6 (the output polarity is GENERATOR assumed to be positive (SPOL = 0)). (MPG, TIMER 4) Table 2-6 Relationship between value Set at OUTCR and Duty Value set at OUTCR...
  • Page 86 HARDWARE CONFIGURATION The DTTI input pin makes the PWM output inactive at hardware in the event 12-BIT MULTIPUL of an external error. With the DTTI input enabled, when an error is detected, GENERATOR the DTIR flag is set to inactivate the PWM output. The time required for this (MPG, TIMER 4) operation is 6 to 8 clock cycles.

  • Page 87: Fig. 2.35 Outline Of Mpg Output

    HARDWARE CONFIGURATION (2) PPG operation 12-BIT MULTIPUL GENERATOR (MPG, TIMER 4) (Software or external) trigger input Timer value Set value to CMCLR + 1 Set value to OUTCR MPG output Output compare match Compare clear timer match Fig. 2.35 Outline of MPG Output As shown in Figure 2.35, the MPG can generate a PPG waveform.

  • Page 88: Fig. 2.37 Flowchart Of Ppg Operation

    HARDWARE CONFIGURATION Select output polarity (SPOL = 1 or 0). 12-BIT MULTIPUL Write data to compare clear buffer register or output buffer register. GENERATOR Setup Select effective edge for external trigger input (ESL1, ESL0). (MPG, TIMER 4) Select trigger source (TSL1, TSL0) % Set/reset MPG output. Enable output to pin (PCN1, PCN0 (0, 0).
  • Page 89 HARDWARE CONFIGURATION Value set at OUTCBR count clock cycle + 1.5 to 2 system clock cycles 12-BIT MULTIPUL GENERATOR The time from external trigger input to MPG reset is as follows: (MPG, TIMER 4) (Value set at CMCLR +1) count clock cycle + 1.5 to 2 system clock cycles For CMCLR OUTCR, the MPG output is in the set state and the pulse is not output.

  • Page 90: 8-Bit Serial I/O

    HARDWARE CONFIGURATION 2.11 8-BIT SERIAL I/O 8-BIT SERIAL I/O 8-bit serial data transfer is possible by the clock synchronous method. LSB first or MSB first can be selected for data transfer. Four shift-clock modes (three internal and one external) can be selected. Block Diagram Internal data bus D0 to D7...
  • Page 91 HARDWARE CONFIGURATION Description of Registers 8-BIT SERIAL I/O The detail of each register is described below. (1) Serial-mode register (SMR) Address: 001C The SMR is used to control serial I/O. Address: 001D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
  • Page 92 HARDWARE CONFIGURATION [Bit 4] SOE: Serial-data output-enable bit 8-BIT SERIAL I/O This bit is used to control the output pin for serial I/O. General-purpose port pin (P33) SO (serial data) output pin When using P34/SI pin as SI pin, always set the DDR to input (bit 0 of DDR4 = 0).
  • Page 93 HARDWARE CONFIGURATION Description of Operation 8-BIT SERIAL I/O The operation of 8-bit serial I/O is described below. (1) Outline This module consists of the serial-mode register (SMR) and serial-data reg- ister (SDR). At serial output, data in the SDR is output in bit serial to the seri- al output pin (SO) in synchronization with the falling edge of a serial shift- clock pulse generated from the internal or external clock.

  • Page 94: Fig. 2.39 Shift Start/Stop Timing

    HARDWARE CONFIGURATION (3) Interrupt functions 8-BIT SERIAL I/O This module can output an interrupt request to the CPU. To output an inter- rupt request, set the SIOE bit of the SMR to 1 to enable an interrupt and then set the interrupt flag SIOF bit of the SMR after 8-bit data transfer is termi- nated.

  • Page 95: Fig. 2.40 Input/Output Shift Timing

    HARDWARE CONFIGURATION (5) Input/output shift timing 8-BIT SERIAL I/O Data is output from the serial output pin (SO) at the falling edge of the shift- clock pulse, and is input from the serial input pin (SI) to the SDR at the rising edge of the shift-clock pulse.

  • Page 96: A/D Converter

    HARDWARE CONFIGURATION 2.12 A/D CONVERTER A/D CONVERTER 16.5 µs conversion time (at 8 MHz and maximum gear speed) 10-bit resolution RC sequential comparison A/D converter with sample and hold circuit Analog input can be selected from 12 channels by the program. End detection by interrupt or software polling Starting by software, by external pin trigger, or by timer unit can be se- lected by the program.
  • Page 97 HARDWARE CONFIGURATION Description of Register A/D CONVERTER The detail of each register is described below. (1) ADC1 (A/D Converter control register) Address: 001E ADC1 This register is used to control the A/D converter and display its status. Address: 001F ADC2 Bit 7 Bit 6 Bit 5...
  • Page 98 HARDWARE CONFIGURATION When reading this bit with the Read Modify Write instructions, 1 is always read. [Bit 2] ADMV: Processing progress flag A/D CONVERTER Bit 2 indicates the progress of conversion or comparison processing. Converting and processing not progressing Converting and processing progressing [Bit 1] SIFM: Interrupt source setting bit This bit is used to set the conditions for setting interrupt source conversion in the sense mode.
  • Page 99 HARDWARE CONFIGURATION [Bit 4] ADCK: External input clock pulse select bit A/D CONVERTER Bit 4 is used to select the clock pulse for starting by the external input clock pulse. No change Operation started (when EXT bit (bit 1) of ADC2 is 1) [Bit 3] ADIE: Interrupt specification bit This bit is used to specify interrupt enable/disable.
  • Page 100 HARDWARE CONFIGURATION When A/D mode A/D CONVERTER In the A/D mode, the result of the A/D conversion is stored as soon as con- version is terminated. After the completion of conversion, the value of the register is held until conversion is restarted. As soon as conversion is started, the value of the register becomes unde- fined.
  • Page 101 HARDWARE CONFIGURATION Continuous start by external clock pulse A/D CONVERTER Providing a clock pulse based on the conversion time and result reading time permits continuous starting of conversion. (2) Sense mode Comparison/recomparison by software The set value to be compared is written beforehand to the data register. Writing 1 at the ADMD bit (bit 2) of the ADC2 and selects the Sense mode.
  • Page 102 HARDWARE CONFIGURATION Precautions for A/D converter A/D CONVERTER (1) In the Reset mode, conversion and comparison stop to initialize each register. In the Stop mode, conversion and comparison stop to clear the flag bit (ADMV bit (bit 2) of the ADC1) in operation. The settings of other bits remain unchanged.

  • Page 103: Buzzer Output Circuit

    HARDWARE CONFIGURATION 2.13 BUZZER OUTPUT CIRCUIT BUZZER OUTPUT CIRCUIT The buzzer output sound for checking key input can be output. Two frequencies can be output by setting the registers. Block Diagram Internal bus TBCR BUZR BUZ1 BUZ0 Select 10.0 MHz P-ch high-withstand-voltage port frequency Time-base timer...

  • Page 104: Table 2-7 Buzzer Output Frequencies (At 8.0 Mhz Of Oscillation Frequency)

    HARDWARE CONFIGURATION Description of Registers BUZZER OUTPUT CIRCUIT The detail of buzzer register is described below. Buzzer register (BUZR) Address: 000E BUZR This 2-bit register enables buzzer output and selects the frequency. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

  • Page 105: External Interrupt Circuit

    HARDWARE CONFIGURATION 2.14 EXTERNAL INTERRUPT CIRCUIT EXTERNAL INTERRUPT CIRCUIT The edges of two external-interrupt sources (INT0 and INT1) can be de- tected to set the corresponding flag. An interrupt can be generated at the same time the flag is set. Both interrupt can release the STOP or SLEEP mode.
  • Page 106 HARDWARE CONFIGURATION [Bit 7] EIR1: External-interrupt request flag EXTERNAL INTERRUPT When the edge specified by the SL10 and SL11 bits is input to the INT1 pin, CIRCUIT bit 7 is set to 1. When the EIE1 bit is 1, an interrupt request (IRQ1) is output if this bit is set.
  • Page 107 HARDWARE CONFIGURATION The meaning of each bit to be written is as follows: EXTERNAL INTERRUPT CIRCUIT This bit is cleared. This bit does not change nor affect other bits. [Bit 2 and Bit 1] SL01, SL00: Edge-polarity mode select bit These bits are used to control the input edge polarity mode of the INT0 pin.

  • Page 108: Operation

    3. OPERATION 3.1 CLOCK PULSE GENERATOR ....3.2 RESET ........3.3 INTERRUPT .

  • Page 109: Clock Pulse Generator

    The operation of MB89140 is described below. 3.1 CLOCK PULSE GENERATOR The MB89140 series of microcontrollers incorporate the system clock pulse generator. The crystal oscillator is connected to the X0 and X1 pins to generate clock pulses. Clock pulses can also be supplied internally by inputting externally-generated clock pulses to the X0 pin.

  • Page 110: Reset

    If a reset occurs around write timing, the contents of the addresses being written are not assured. When the reset conditions are cleared, the MB89140 series of microcontrollers are released from the reset state and start operation after fetching the mode data from address FFFD...

  • Page 111: Reset Sources

    OPERATION 3.2.2 Reset Sources The MB89140 series of microcontrollers have the following reset sources. (1) External pin A Low level is input to the RST pin. (2) Specification by software 0 is written at the RST bit of the standby-control register.

  • Page 112: Interrupt

    OPERATION 3.3 INTERRUPT If the interrupt controller and CPU are ready to accept interrupts when an interrupt request is output from the internal resources or by an external-interrupt input, the CPU temporarily suspends the currently-executing instruction and executes the interrupt-processing program. Figure 3.4 shows the interrupt-processing flow- chart.

  • Page 113: Table 3-1 Interrupt Sources And Interrupt Vectors

    OPERATION Table 3-1 lists the relationships between each interrupt source and interrupt vector. Table 3-1 Interrupt Sources and Interrupt Vectors Upper vector Lower vector Interrupt source address address IRQ0 (External interrupt 0) FFFA FFFB IRQ1 (External interrupt 1) FFF8 FFF9 IRQ2 (8-bit PWM timer: Timer 1) FFF6 FFF7...

  • Page 114: Low-Power Consumption Modes

    2.2). If the single clock module is specified with the mask option, the MB89140 series of microcontrollers can be used as single clocks. If the microcontrollers are used as single clocks without specifying the single clock module with the mask option, once the subclock mode is entered, it cannot be released.

  • Page 115: Pin States For Sleep, Stop And Reset

    OPERATION 3.5 PIN STATES FOR SLEEP, STOP AND RESET The state of each pin of the MB89140 series of microcontrollers at sleep, stop and reset is as follows: (1) Sleep The pin state immediately before the sleep state is held.

  • Page 116: Instructions

    4. INSTRUCTIONS 4.1 TRANSFER INSTRUCTIONS ..... 4.2 OPERATION INSTRUCTIONS ....4.3 BRANCH INSTRUCTIONS .

  • Page 117: Transfer Instructions

    INSTRUCTIONS 4.1 TRANSFER INSTRUCTIONS MNEMONIC OPERATION TH AH N Z V C OP CODE — — — — — — — MOV dir,A (dir) — — — — — MOV @IX+off,A ((IX)+off) — — (ext) — — — — — — — MOV ext,A ((EP)) —...

  • Page 118: Operation Instructions

    INSTRUCTIONS 4.2 OPERATION INSTRUCTIONS MNEMONIC OPERATION TH AH N Z V C OP CODE 28 to 2F (A)+(Ri)+C — — — + + + + ADDC A,Ri (A)+d8+C — — + + + + ADDC A,#d8 — (A)+(dir)+C — — —...

  • Page 119: Branch Instructions

    INSTRUCTIONS 4.3 BRANCH INSTRUCTIONS MNEMONIC OPERATION TH AH N Z V C OP CODE BZ/BEQ rel if Z=1 then PC PC+rel — — — — — — — if Z=0 then PC PC+rel — — — — — BNZ/BNE rel —...

  • Page 120: Other Instructions

    INSTRUCTIONS 4.4 OTHER INSTRUCTIONS MNEMONIC OPERATION TH AH N Z V C OP CODE PUSHW A — — — — — — — SP–2 (SP) POPW (SP) SP+2 — — — — — — PUSHW IX SP–2 (SP) — — —...

  • Page 121: F 2 Mc-8L Family Instruction Map

    INSTRUCTIONS 4.5 F MC-8L FAMILY INSTRUCTION MAP...

  • Page 123: Mask Options

    5. MASK OPTIONS...

  • Page 124: Table 5-1 Mask Options

    MASK OPTIONS Table 5-1 Mask Options MB89144V1 MB89144V2 Model MB89PV140 MB89PV140 MB89145V1 MB89145V2 MB89P147V1 MB89P147V2 –101 –102 MB89146V1 MB89146V2 MB89W147V1 MB89W147V2 Item MB89147V1 MB89147V2 Power-on reset Available Available Select when ordering mask Select by EPROM writer Unavailable Reset pin output Available Available Select when ordering mask...

  • Page 125: Appendix

    APPENDIX...

  • Page 126: Appendix A I/O Map

    APPENDIX APPENDIX A I/O MAP Addresses 00 to17 Initial value Address Read/Write Register Description of register (R/W) PDR0 XXXX XXXX Port 0 data register DDR0 0000 0000 Port 0 data direction register (R/W) PDR1 XXXX XXXX Port 1 data register DDR1 0000 0000 Port 1 data direction register...
  • Page 127 APPENDIX Address 18 to 7F Initial value Address Read/Write Register Description of register (R/W) T3CR X000 XXX0 Timer 3 control register (R/W) T2CR X000 XXX0 Timer 2 control register (R/W) T3DR XXXX XXXX Timer 3 data register (R/W) T2DR XXXX XXXX Timer 2 data register (R/W) 0000 0000 Serial mode register...

  • Page 128: Appendix B Eprom Setting For Mb89P147

    APPENDIX APPENDIX B EPROM SETTING FOR MB89P147 MB89P147 is provided with the function corresponding to MBM27C256A by EPROM setting. The setting can be performed by writing program data with general-purpose EPROM writer through adaptor for exclusive use . Setting (1) Set the EPROM writer to MBM27C256A. (2) Load the program data from address 0007 to address 7FFF of EPROM writer.
  • Page 129 APPENDIX Bit Map for PROM Option 0000 <OP 4> <OP 3> <OP 2> (8000 Empty Empty Empty Clock Reset pin Power-on Reserved Reserved specification output reset Read/write Read/write Read/write 1: Double 1:Available 1:Available (Write 1.) (Write 1.) possible possible possible 0: Single 0:Unavailable 0:Unavailable 0001...
  • Page 130 APPENDIX APPENDIX C LIST OF SYSTEM CLOCK CYCLE TIMES WHEN GEAR CHANGED (Source clock: 8 MHz, 4 MHz) Setting of CS1 and CSO bits (system clock select bit) of SYCC register Number of CS1 = 1, CSO = 1 CS1 = 1, CSO = 0 CS1 = 0, CSO = 1 CS1 = 0, CSO = 0 system...
  • Page 131 FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6–10 63303 Dreieich–Buchschlag, Germany Tel: (06103) 690–0 FAX: (06103) 690–122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06–04 to #06–07 Singapore 0718 Tel: 336–1600 FAX: 336–1609...

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