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Agilent Technologies 93000 SOC Series Training Manual

Agilent Technologies 93000 SOC Series Training Manual

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Agilent 93000 SOC Series

Mixed-Signal Training

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Page 1 Agilent 93000 SOC Series Mixed-Signal Training Training Manual...
Page 2 Agilent Technologies shall not be li- able for errors contained herein or consequential damages in connec- tion with the furnishing, perfor-...
Page 3: Table Of Contents
Contents Unit 1 Introduction Lesson 1 Training Overview About This Training ...............15 The Study Material .................19 Lesson 2 Introduction to the Test System Components of SOC Devices ............23 SOC Series Mixed-Signal System Overview ........25 Questions ..................33 Summary and Discussion ..............34 Lesson 3 Introduction to the Software SmarTest Software Concept Overview ........37...
Page 4 Contents Lesson 2 Addressing the Analog Modules Locations of Analog Boards in the Testhead ......131 Analog Pins of the Board ............134 Identification of Analog Channels in the Software ....139 Lesson 3 Synchronization of Analog Modules Synchronization + Triggering ............. 146 Adjusting the Synchronization Timing ........
Page 5 Contents Lesson 3 Setting up the Digitizers in the Digital Clock Domain What is a Clock Domain.............. 199 Clock Sources and Clock Distribution Overview ....200 Digital Clock Domain Setup for the Digitizer ......203 Summary and Discussion ............208 Lesson 4 Defining the Signal Routing Analog Routing Basics ..............
Page 6 Contents Lesson 6 Executing the DAC Linearity Test DAC Linearity Measurements............ 255 DAC Linearity Test Parameters..........261 Uploading Result Waveforms with the Mixed-Signal Tool..263 Displaying Logged Waveforms with the Mixed-Signal Tool... 266 Related Topics ................270 Summary and Discussion ............271 Lesson 7 Executing the DAC Distortion Test DAC Distortion Measurements ..........
Page 7 Contents Lesson 3 Setting Up the Digital Capturing Introduction to Digital Capture ..........325 Setup for Digital Capture............328 Summary and Discussion ............340 Lesson 4 Executing the ADC Linearity Test ADC Linearity Measurements............ 343 ADC Linearity Test Parameters..........347 Uploading Result Waveforms with the Mixed-Signal Tool ..
Page 8 Contents Unit 6 Using Test Methods Lesson 1 Test Method Structure Test Method Overview..............399 Data Types ..................403 Input/Output Data of Test Method Program ......405 Programming Style of Test Method API ........409 Test Method APIs ................. 414 Test Method Program for DC Tests ...........
Page 9 Contents Lesson 2 TIA Setup Overview ..................479 Pin Configuration for the TIA ............ 480 Front-End and TIA Setup ............481 Defining the Routing ..............493 Summary and Discussion ............495 Lesson 3 TIA Test Method Programming and Test Execution Test Method Flow ................
Page 10 Contents Lesson 3 Special Synchronization Options Master/Slave Trigger Function ..........543 Appendix...
Page 11: Unit
Introduction Unit 1...
Page 12 Unit 1 – Introduction In this Unit ... Overview This Unit comprises: • An introduction to the training. An introduction to the test system with a focus on the system • components for mixed-signal test. A quick overview of the SmarTest software and an introduction to •...
Page 13: Lesson
Lesson 1 Training Overview...
Page 14 Lesson 1 – Training Overview In this Lesson ... Overview This lesson gives an overview of the training. It contains the training agenda, the training objective statement and a summary of the prerequisites the student must fulfil for this training. This lesson also familiarizes you with the training material and the general training structure.
Page 15: About This Training
Lesson 1 – Training Overview About This Training Welcome to the Agilent 93000 SOC Series Mixed Signal Training! Training Agenda The Training Agenda NOTE The individual training course may vary from this agenda due to a prioritization of topics in order to adapt the training to the individual...
Page 16 Lesson 1 – Training Overview Training Objective The Training Objective You will be prepared to plan appropriate tests by utilizing the capabilities and • performance of the analog modules use the available software tools for developing and debugging • mixed-signal tests •...
Page 17 Lesson 1 – Training Overview A brief refresher of Mixed-Signal Testing Fundamentals can be NOTE found in the Appendix. However, mixed-signal test knowledge is required and should have been refreshed in advance to the training course.
Page 18 Lesson 1 – Training Overview Training Outline The training is built up on units. The units consist of lessons. Structure of the Training In each lesson, the learning objectives are defined at the beginning, then, the actual contents of the lesson are discussed, and finally questions and/or lab exercises will be given to ensure that you have achieved the learning objectives.
Page 19: The Study Material
Each lesson starts with an overview, the definition of the – learning objectives, and references to related topics in the Agilent 93000 SOC Series user manuals and other documents. – Each lesson is divided into sections. The sections contain descriptions, step-by-step instructions, –...
Page 20 Lesson 1 – Training Overview Layout Conventions Most of the layout and typographical conventions used in the study material are self explanatory. Let us just point out the following: Elements shown on the screen (for example buttons, edit boxes, • menu items) are printed in small capitals: “the S menu”...
Page 21: Lesson 2
Lesson 2 Introduction to the Test System...
Page 22: Introduction To The Test System
In this Lesson ... Overview This lesson gives you an overview of the mixed-signal test solution of the Agilent 93000 SOC Series. You will learn about the general system requirements to perform mixed-signal tests, what the mixed-signal hardware components of the SOC Series are, and how they fulfil these test requirements.
Page 23: Components Of Soc Devices
Digital to analog converters (DACs), analog to digital converters (ADCs) and analog buffers are typical mixed-signal components of an SOC device. With its digital and mixed-signal test capabilities, the Agilent 93000 SOC Series addresses the test requirements of today’s and tomorrow’s SOC devices.
Page 24 Lesson 2 – Introduction to the Test System Requirements for Testing Mixed-Signal Components of an SOC Device Testing a buffer To measure the characteristics of a buffer (such as an impedance converter, amplifier, or attenuator), one needs to apply an analog signal and analyze the analog response.
Page 25: Soc Series Mixed-Signal System Overview
Lesson 2 – Introduction to the Test System SOC Series Mixed-Signal System Overview All models of the Agilent 93000 SOC Series have the capability to perform mixed-signal tests. They are structured alike, and basically use the same components for mixed-signal tests.
Page 26 Lesson 2 – Introduction to the Test System Digital Capture pins If the DUT responds with a stream of digital data, that response is captured by digital pins and stored in the capture memory. or Waveform Digitizers acquire the If the DUT responds with an analog waveform, a Waveform response Digitizer (WD) converts the response signal into numbers and stores it.
Page 27 Lesson 2 – Introduction to the Test System Testhead Contents The testhead of an SOC Series system contains digital channel boards and analog modules, and also internal power supplies (DC/ DC converters), device power supplies (DPS), and clock boards. Testhead Contents for Mixed-Signal Test Architecture of Analog Module Integration...
Page 28 Lesson 2 – Introduction to the Test System Digital Channel Boards Pin PMU – one per pin A digital board provides 16 digital input or output pins (also called channels). Each pin has a Parametric Measurement Unit (pin PMU), programmable load, digital memory, a driver and a comparator unit.
Page 29 Lesson 2 – Introduction to the Test System boards, some require external instruments that are installed in the analog support rack. Use of Analog Modules There are three types of analog modules: Types of Analog Modules...
Page 30 Max input frequency 960MHz Analyzers Besides, the Multi-site Baseband Analog Measure is available, Page 19 Agilent 93000 SOC Series which contains the Audio Digitizer and Video Digitizer. Mixed Signal Training Summary of Analog Modules for the SOC Series All analog modules will be discussed in detail in Unit 2 of this training.
Page 31 Lesson 2 – Introduction to the Test System Each analog module has at least one trigger input pin, a clock input, a built-in sequencer, sequencer memory, and waveform data memory. The sequencer memory contains the sequencer program. This program defines the sequence of waveforms to be generated or captured.
Page 32 Lesson 2 – Introduction to the Test System Where to See Which Analog Modules are Installed in the Test System When starting up the SmarTest software, the Report Window displays a list of all analog modules that are installed in the test system.
Page 33: Questions
Lesson 2 – Introduction to the Test System Questions Time 5 minutes SOC Series Structure for Mixed-Signal Testing Task 1 Fill in the blank fields SOC Series Structure for Mixed-Signal Testing...
Page 34: Summary And Discussion
Lesson 2 – Introduction to the Test System Summary and Discussion In this lesson, you have learned about the mixed-signal components of the Agilent 93000 SOC-Series. You now know the general structure of mixed-signal test solution and understand the function of the mixed-signal hardware components in a mixed-signal test.
Page 35: Lesson
Lesson 3 Introduction to the Software...
Page 36 Related documents More detailed information can be found in the manuals Agilent 93000 SOC Series “Test Setup” • Agilent 93000 SOC Series “Standard Test Function Reference” • • Agilent 93000 SOC Series “System Reference”...
Page 37: Smartest Software Concept Overview
All SmarTest tools, except for the special tools for mixed-signal test, have been covered in the basic Agilent 93000 SOC Series User Training, Part 1 and Part 2. Many of the not mixed-signal specific SmarTest tools will also be used to set up parts of a mixed-signal test, and to run the test.
Page 38 Lesson 3 – Introduction to the Software SmarTest Structure Overview...
Page 39: Tools For Mixed-Signal Testing
Lesson 3 – Introduction to the Software Tools for Mixed-Signal Testing Before a test can be executed, all test setup data must be defined. For the test execution, the test flow must be created and, if a user specific test method is used instead of a standard testfunction, this test method must be written and compiled.
Page 40: Analog Modules
Lesson 3 – Introduction to the Software timing, and vector setups have to be defined. Only pins to be used for digital capture, need additional settings. The analog modules require special parameters which define the settings of impedance, filters, amplifiers, attenuators, and so on, and instruct the sequencer how to perform the test.
Page 41: Analog Modules
Lesson 3 – Introduction to the Software The following figure shows the main windows of the tools for mixed-signal testing. Main Windows of the Tools for Mixed-Signal Testing Analog Setup Tool The Analog Setup Tool is used for setting up the analog modules. The setup data is saved in the Analog Setup File.
Page 42 Lesson 3 – Introduction to the Software The Four Setup Pages of the Analog Setup Tool Even though four setup pages are shown above, the tool has only one window. You can switch between the four setup pages (Hardware Settings, Sequencer Memory, Waveform Memory and Clock Domain Setup).
Page 43 Lesson 3 – Introduction to the Software For debugging, the Analog Setup Tool can also be used to monitor the routing (relay settings) and the parameters of the analog mod- ules at run-time. Monitoring the Routing and Setup Parameters with the Analog Setup Tool Mixed-Signal Tool The Mixed-Signal Tool is used for waveform generation and result waveform analysis.
Page 44 Lesson 3 – Introduction to the Software Waveform modifications for special applications are supported, • for example, jitter modulation and simulation of the effect of a cable on the signal. Mixed-Signal Tool - Waveform Generation The generated waveform can be downloaded to the waveform memory of an AWG, or to the vector memory of digital pins.
Page 45: Analog Modules
Lesson 3 – Introduction to the Software Upload from digitizer, digital capture or data log. • The tool can read the waveforms to be analyzed either from analog modules, digital capture or logged data. Mixed-Signal Tool - Waveform Analysis Routing Setup Tool The Routing Setup Tool is used to define the routing of pins to analog modules.
Page 46 Lesson 3 – Introduction to the Software Routing Setup Tool Test Method Tool The Test Method Tool supports easy creation, compilation and debugging of test methods. Test methods are customized tests (written in C or C++) that use pre-defined functions. These functions are provided by several function libraries, called Application Programming Interfaces (APIs).
Page 47 Lesson 3 – Introduction to the Software Test Method Tool - Test Method Creation Also compiling and debugging of test methods are made easy with the Test Method Tool. One-click compilation and linking of test methods. • Test method debugging with integrated debugger. •...
Page 48 Test Method Tool - Test Method Debugging Digital Capture Setup With the Agilent 93000 SOC Series, capturing of digital output data of SOC devices, such as the output of an (embedded) ADC, is done with normal digital pins. The captured data is stored in the vector memory of the capture pins.
Page 49 Lesson 3 – Introduction to the Software Digital Capture Setup Test Execution Setup Once the setup data is entered, the test execution can be defined. The central element in the test execution is the test suite. A test suite typically performs on specific device test. The test suite is an element of the test flow.
Page 50 Lesson 3 – Introduction to the Software Test Suite Setup Test Functions A testfunction is a ready-to-use test provided by SmarTest. You only need to enter the test parameters in the test control window. SmarTest provides a number of standard mixed-signal testfunctions, for example, DAC Linearity test and DAC Distortion test.
Page 51 Lesson 3 – Introduction to the Software Testfunction in Test Suite Test Methods A test method is a customized test written in C or C++. SmarTest provides various libraries (APIs) with ready-to-use functions for test execution, result analysis, signal processing and for various further calculations to be performed on test data.
Page 52 Lesson 3 – Introduction to the Software With these functions, you can easily program your own test methods that perform device specific tests. Test Method in Test Suite User Procedures Like a test method, a user procedure is a customized test written in C.
Page 53 Lesson 3 – Introduction to the Software With the new Test Method Tool, test methods are also easier to generate, debug and maintain than user procedures. Test methods are the “next generation user procedures”. User Procedures in Test Suite This training focuses on the use of testfunctions and test methods. NOTE...
Page 54: Questions
Lesson 3 – Introduction to the Software Questions Time 10 minutes Check Your Knowledge Task 1 Name the five tools of the SmarTest software for mixed-signal testing. Mark: What kind of data is required to set up an analog module? ❑...
Page 55: Analog Modules
Lesson 3 – Introduction to the Software The settings of a mixed-signal testfunction ❑ are automatically downloaded to the analog modules ❑ determine the processing of the device output data A test method ❑ is written and compiled with the Test Method Tool ❑...
Page 56: Summary And Discussion
Lesson 3 – Introduction to the Software Summary and Discussion This lesson summarized the general structure of SmarTest and made you familiar with the main software tools for setup, debugging and execution of mixed-signal tests.
Page 57: Unit 2
Analog Hardware Unit 2...
Page 58 Unit 2 – Analog Hardware In this Unit ... Overview This Unit comprises: An overview of the analog modules. • • Block diagrams and feature descriptions of the analog modules. An overview of the testhead configurations. • Information about how to address the analog modules. •...
Page 59: Lesson 1
Lesson 1 Analog Modules...
Page 60: Analog Modules
Lesson 1 – Analog Modules In this Lesson ... Overview Testing of mixed signal devices requires analog resources for applying highly accurate analog signals to devices and capturing analog output from devices. This lesson makes you familiar with the structure and the characteristics of the analog modules.
Page 61: Summary Of Analog Modules
Lesson 1 – Analog Modules Summary of Analog Modules The analog modules of the Agilent 93000 SOC Series can be divided into two groups: Analog modules that source signals to the DUT • Analog modules that measure signals coming from the DUT.
Page 62: Arbitrary Waveform Generators (Awg)
Lesson 1 – Analog Modules Arbitrary Waveform Generators (AWG) Arbitrary Waveform Generators (AWG) can source various waveforms to DUTs. An AWG uses waveform data that is stored in its waveform memory to generate analog waveforms. You create arbitrary waveform data with the software interface, Mixed-Signal Tool.
Page 63 Lesson 1 – Analog Modules Table 1 High Resolution AWG (WGA) Key Specifications Specification Value Sampling rate 8 ksps to 1.024 Msps Resolution 18-bit Pin counts per module 8 single-ended (4 parallel test) or 4 differential (2 parallel test) Waveform Memory Max sinewave fre- 250 kHz quency...
Page 64 Lesson 1 – Analog Modules Table 3 High Speed AWG (WGB) Key Specifications Specification Value Sampling rate 8 ksps to 128 Msps Resolution 12-bit Pin counts per module 8 single-ended (4 parallel test) or 4 differential (2 parallel test) Waveform Memory Output Range 2.5 Vpp @50 ohm load DC offset Range...
Page 65 Lesson 1 – Analog Modules Table 5 Ultra High Speed AWG (WGC) Key Specifications Specification Value Sampling rate 50 ksps to 2.6 Gsps Resolution 8-bit Pin counts per module 4 single-ended or 2 differential Waveform Memory Output Mode Differential (characteristic data) 300 MHz @-3 dB Max sinewave fre- quency Output Range...
Page 66 Lesson 1 – Analog Modules High Resolution / High Speed / 500M AWG The following figure shows the block diagram of the High Resolution AWG (WGA), High Speed AWG (WGB) and 500M AWG (WGD): Block Diagram of WGA, WGB and WGD All the components of these AWGs are placed on a single board which is installed in the testhead.
Page 67 Lesson 1 – Analog Modules Loop back routes from one AWG pin to another. • The SYNC CLK pin is also called the trigger pin. SYNC_DATA is N OT E currently not used. For details about these routes, see “Pin Connections with an Analog Module’s Multiplexer”...
Page 68 Lesson 1 – Analog Modules 30M AWG The following figure shows the block diagram of the 30M AWG (WGE); the bold lines show the single-ended output routes of the WGE. The WGE is a single-slot analog module installed in the testhead, and has two identical AWGs that share the trigger/timing system.
Page 69 Lesson 1 – Analog Modules Mode Possible Pin Combinations of Output Routes (WGE) Single-ended 8 outputs (4 outputs simultaneously): (A+ or B+), (A- or B-), (C+ or D+), and/or (C- or D-) Differential 4 outputs (2 outputs simultaneously): (A+&A- pair or B+&B- pair) and/or (C+&C- pair or D+&D- pair) Mix of single-ended and Single-ended mode in one AWG core, and differential mode in differential...
Page 70 Lesson 1 – Analog Modules Ultra High Speed AWG The following figure shows the block diagram of the Ultra High Speed AWG (WGC): Ultra High Speed AWG Block Diagram The Ultra High Speed AWG consists of a front-end module which resides in the testhead, and the instrument itself installed in the analog support rack.
Page 71 Lesson 1 – Analog Modules For details about these routes, see “Pin Connections with an Analog Module’s Multiplexer” on page 99. AWG Instrument The AWG instrument is installed in the analog support rack. The Ultra High Speed AWG is a dual-core instrument. This means that it contains two AWG cores that are both connected to the same front-end card.
Page 72 Lesson 1 – Analog Modules 4.1G AWG The following figure shows the block diagram of the 4.1G AWG (WGF); the bold lines show the differential output routes of the WGF. The WGF is a single-slot analog module installed in the testhead. Output Multiplexer Pogo Pin Non-inverse...
Page 73: Waveform Digitizer
Lesson 1 – Analog Modules Waveform Digitizer The waveform digitizer can digitize the analog signal output from the DUT, then store the digitized waveform data in the waveform memory in real time. The waveform sequencer controls the waveform memory area where data is stored, and the number of sample points that are taken.
Page 74 Lesson 1 – Analog Modules Table 7 High Resolution Digitizer (WDB) Key Specifications Specification Value Sampling rate 8 ksps to 2.048 Msps Resolution 16-bit (up to 24-bit with hardware averaging) Bandwidth @-3 dB 3 MHz @±6 V range, filter through Pin counts per module 8 single-ended or 4 differential Waveform Capture...
Page 75 Lesson 1 – Analog Modules Table 8 20MHz Digitizer (WDE) Key Specifications Specification Value Sampling rate 125 ksps to 5 Msps Resolution 16-bit Bandwidth @-3 dB 20 MHz @filter through Pin counts per module 8 single-ended or 4 differential (2-parallel test) Number of digitizer cores per module Waveform capture memo-...
Page 76 Lesson 1 – Analog Modules Table 9 High Speed Digitizer (WDA) Key Specifications Specification Value Sampling rate 1 Msps to 41 Msps Resolution 12-bit Bandwidth @-3 dB 100 MHz @±0.5 V range, filter through Pin counts per module 8 single-ended or 4 differential Waveform Capture 512 k Memory...
Page 77 Lesson 1 – Analog Modules Table 10 100MHz Digitizer (WDG) DC Coupling Mode DC Coupling Mode Key Specification Value Sampling rate 30 Msps to 105 Msps Resolution 14-bit Bandwidth @ -3 dB DC to 100 MHz @ filter through (characteristic data) Pin counts per module 8 single-ended or 4 differential Waveform capture memory...
Page 78 Lesson 1 – Analog Modules Table 12 1GHz Digitizer (WDD) Digitizer Mode Digitizer Mode Key Specification Value Sampling rate 1 Msps to 320 Msps Resolution 12-bit Bandwidth @ -3 dB 160 MHz @ filter through (characteristic data) Pin counts per module 8 single-ended or 4 differential Waveform capture memory 4 M samples...
Page 79 Lesson 1 – Analog Modules High Resolution / High Speed Digitizer The following figure shows the block diagram of the high resolution digitizer and high speed digitizer: Block Diagram of WDA/WDB The waveform digitizer consists of the following blocks: Input Multiplexer For A+, A-, B+, B-, C+, C-, D+, and D- input pins, the input multiplexer is used to specify one of 8 single-ended inputs or one of 4 differential inputs.
Page 80 Lesson 1 – Analog Modules Input Amplifier The input amplifier determines the input voltage range. Any input voltage ranges are normalized to a certain voltage range at the output of the input amplifier. If the signal to be measured includes a DC component and you want to measure only AC components, you can eliminate the DC component by setting a DC offset voltage.
Page 81 Lesson 1 – Analog Modules 20MHz Digitizer The following figure shows the block diagram of the 20MHz Digitizer (WDE); the bold lines show the single-ended input routes of the WDE. Bandwidth Resolution Sampling Rate Waveform Memory 20 MHz 16 bits 125 ksps to 5 Msps 1 M samples (per digitizer core) The WDE is a single-slot analog module installed in the testhead,...
Page 82 Lesson 1 – Analog Modules The single-ended signal and differential route can be made from the pins shown in the following table. Input Possible Input Pin in Input Route of WDE In core 1 1 input only of 4 inputs: 8 inputs per module.
Page 83 Lesson 1 – Analog Modules 100MHz Digitizer The 100MHz Digitizer (software identifier: WDG) is a 105 Msps 14- bit digitizer. This module has two signal paths with different A/D converters. The respective signal paths are called the DC coupling mode and AC coupling mode. The DC coupling mode is for standard analog measurements and the AC coupling mode is for high dynamic range analog measurements such as set-top-box application.
Page 84 Lesson 1 – Analog Modules In addition to the single-ended/differential input routes, the DC routes and loop-back routes are available in the WDG. All routing is switched by the input multiplexer. For other components in the digitizer (input amplifier, filter, ADC, timing generator, sequencer, waveform memory, and SYNC_DATA pin), see the description in “High Resolution / High Speed Digitizer”...
Page 85 Lesson 1 – Analog Modules 1GHz Digitizer (1 GHz Sampler 320 Msps Digitizer) The 1GHz Digitizer module (software identifier: WDD) is the instru- ment that contains a 1 GHz-BW 50 Msps 12-bit sampler and a 320 Msps 160 MHz-BW12-bit digitizer. These sampler and digitizer are used alternatively;...
Page 86 Lesson 1 – Analog Modules In digitizer mode or sampler mode, the single-ended signal or differential signal can be captured from the pins shown in the following table. Possible Input Pin in Input Route of WDD Input (for Digitizer Mode or Sampler Mode) Single-ended input 1 input only of 8 inputs: A+, B+, C+, D+, A-, B-, C-, or D-...
Page 87: Sampler
Lesson 1 – Analog Modules Sampler The sampler can sample high frequency periodic signals, that cannot be measured by general waveform digitizers, by using the undersampling technique. The following samplers are available: E9687A Dual High Speed Sampler (1 GHz input frequency 12-bit) •...
Page 88 Lesson 1 – Analog Modules Table 14 Dual High Speed Sampler (SPA) Key Specifications Specification Value Sampling rate 8 ksps to 1 Msps Max. input frequency 1 GHz Resolution 12-bit Pin counts per module 4 single-ended (2-parallel test) Number of sampler cores per module Waveform capture memory 1M (512 K samples per sampler core)
Page 89 Lesson 1 – Analog Modules Sampling Technique The following figure shows the undersampling technique of the sampler: Clock Master Clock Digital I/O Channels (Digital clock domain) Data Phase Lock Trigger Master Clock Sampler (Analog clock domain) Analog Out Ts_e Ts_e Ts_e Sample Ts = K x Tin + Ts_e...
Page 90 Lesson 1 – Analog Modules Dual High Speed Sampler The Dual High Speed Sampler (software identifier: SPA) can be used to capture repetitive waveforms up to 1 GHz with 12-bit resolution. Max. Input Frequency Resolution Sampling Rate Waveform Memory 1 GHz 12 bits 8 ksps to 1 Msps 0.5 M samples (per sampler core)
Page 91 Lesson 1 – Analog Modules In the Sampler, the single-ended signal can be captured from the pins shown in the following table. Only the single-ended input is available. Input Possible Input Pin in Input Route of SPA In core 1 1 input only of 2 inputs: 4 inputs per module.
Page 92 Lesson 1 – Analog Modules 3GHz Sampler The 3GHz Sampler (software identifier: SPB) can be used to capture single-ended or differential repetitive waveforms up to 3 GHz with 12-bit resolution. Max. Input Frequency Resolution Sampling Rate Waveform Memory 3 GHz 12 bits 100 ksps to 10 Msps 1 M samples (per sampler core)
Page 93 Lesson 1 – Analog Modules Input Possible Input Pin in Input Route of SPB In core 1 1 input only of 2 inputs: 4 inputs per module. A+ or B+ 2 single-ended inputs Single-ended input simultaneously by us- In core 2 1 input only of 2 inputs: ing core 1 and core 2 C+ or D+...
Page 94: Time Interval Analyzer
Lesson 1 – Analog Modules Time Interval Analyzer Two types of Time Interval Analyzers are available for the Agilent 93000 SOC Series: E9691A High Performance TIA •  Software Identifier: TIA E9705A General Purpose TIA •  Software Identifier: TIA Both TIAs are identical in design and in the way they are set up and used.
Page 95 Lesson 1 – Analog Modules Front-End Module The front-end module consists of two main blocks which fulfil the tasks of conditioning the signals for the TIA instrument and of routing the signals to the TIA instruments: Input Block • - signal conditioning - routing to the center block - loop-back routing and routing for dc measurements (For details about these routing types, see “Pin Connections with an Analog...
Page 96 Lesson 1 – Analog Modules TIA Instrument The Time Interval Analyzer (TIA) performs time measurements for the input signals CH1 and/or CH2, stores the results and performs calculations on the stored values. Besides the two signal inputs, the TIA instrument has one trigger input.
Page 97 Lesson 1 – Analog Modules For details of the TIA measurement functions, see the Unit “Time Interval Analyzer” on page 467. The following table shows the key specifications of the High Performance TIA: Table 16 Specifications of High Performance TIA Specification Value Pin counts per front-end mod-...
Page 98 Lesson 1 – Analog Modules The following table shows the key specifications of the General Purpose TIA. Table 17 Specifications of General Purpose TIA Specification Value Pin counts per front-end module 7 input pins (with signal loop-back) 2 trigger pins Number of triggers input 1 input to each TIA instrument Number of channels per TIA instru-...
Page 99: Pin Connections With An Analog Module's Multiplexer
Lesson 1 – Analog Modules Pin Connections with an Analog Module’s Multiplexer All the analog modules have a multiplexer to make various connections for pogo pins. Depending on what is connected to the pogo pins, the allowable connections are grouped as follows: Connections to the Main Circuit of the Analog Module Output Routes (for AWGs only)
Page 100 Lesson 1 – Analog Modules Output Routes (Differential in WGA/WGB/WGD) Input Routes (For digitizers, samplers, and TIA) This connection type is used to measure an analog waveform. Input Routes (Single-Ended in WDB/WDA)
Page 101 Lesson 1 – Analog Modules Input Routes (Differential in WDB/WDA) Connections to the Other Pogo Pins DC Routes By connecting the pin PMU to the SYNC CLK (Trigger) pin, this connection type can be used to perform DC measurements at an analog pin.
Page 102 Lesson 1 – Analog Modules DC Routes (WGA/WGB/WGD) Loop-back Routes If you need to connect a single DUT pin to multiple analog modules or to analog module and digital pin, this connection type is used. The multiplexer of an analog module can make the route between the desired signal pins.
Page 103 Lesson 1 – Analog Modules The following figure shows how to use one DUT pin for multiple digitizers (high speed digitizer and high resolution digitizer) by means of a loop back route: Example of a Loop-back Route In the above example, when K1 and K3 are closed and K2 is open, the signal from the DUT can be measured by using the High Speed Digitizer.
Page 104: Multi-Site Baseband Analog Source&Measure / Analog Measure (Mca)
Lesson 1 – Analog Modules Multi-site Baseband Analog Source&Measure / Analog Measure (MCA) The multi-site baseband analog source & measure and the multi- site baseband analog measure are single-slot analog modules installed in the test head, and contain eight units in one module. Each of the eight units has multiple types of AWGs or digitizers.
Page 105 Lesson 1 – Analog Modules Two Models of Multi-site Baseband Analog Modules Multi-site baseband analog source & measure • (software identifier for the module: MCA) – Contains four Source Units (software identifier for the unit: SRCA) and four Measure Units (software identifier for the unit: MESA).
Page 106 Lesson 1 – Analog Modules Maximum Number of Inputs and Outputs in Each Function per Source Unit or Measure Unit The following table shows the maximum number of inputs and outputs in each function per source unit or measure unit. Each of the maximum numbers shown in the table and the following two tables are available when only the one core function is used.
Page 107 Lesson 1 – Analog Modules These numbers are eight times those shown in two previous table for per measure unit. Core Function Max number of Inputs/Outputs (or Sites) (For Measure Module) For Single-ended For Differential Serial test Parallel test Serial test Parallel test 32 * PMU (DC)
Page 108 Lesson 1 – Analog Modules source&measure module, and sites 5 through 8 can use the digitizer in the measure module. Specifications of MCA The following tables show the specifications and characteristics of the MCA. The Multi-site Baseband Analog Source & Measure (E9714A) consists of four source units and four measure units.
Page 109 Lesson 1 – Analog Modules Audio AWG in Source Unit Table 18 Audio AWG Key Specifications Specification Value Sampling rate 32 ksps to 1.024 Msps Resolution 24-bit Pin counts 2 single-ended (one at a time) or 1 differential per source unit. 4 source units in module.
Page 110 Lesson 1 – Analog Modules Audio Digitizer in Measure Unit Table 20 Audio Digitizer Key Specifications Specification Value Sampling rate 32 ksps to 200 ksps Resolution 24-bit Bandwidth @-3 dB 50 kHz (characteristic data) Pin counts 4 single-ended (2 at a time) or 2 differential (2 at a time) per measure unit.
Page 111 Lesson 1 – Analog Modules Video Digitizer - Normal Mode in Measure Unit Table 21 Video Digitizer Normal Mode Key Specifications Specification Value Sampling rate 500 ksps to 65 Msps Resolution 14-bit Bandwidth @-3 dB 15 MHz (characteristic data) Pin counts 2 single-ended (one at a time) or 1 differential per measure unit.
Page 112 Lesson 1 – Analog Modules Video Digitizer - Direct Mode in Measure Unit Table 22 Video Digitizer Direct Mode Key Specifications Specification Value Sampling rate Same as for normal mode Resolution Same as for normal mode Bandwidth @-3 dB 100 MHz (characteristic data) Pin counts 2 single-ended (one at a time) or 1 differential per measure unit.
Page 113 Lesson 1 – Analog Modules PMU in Source Unit or Measure Unit Table 23 MCA-PMU Specifications Specification Value Pin counts 4 (one at a time) per source unit or measure unit. 8 source or measure units in module Voltage Force or Measure: Range Source Unit (SRCA): -2.0 V to +3.5 V...
Page 114 Lesson 1 – Analog Modules V Source in Source Unit or Measure Unit Table 24 MCA V Source Key Specifications Specification Value Pin counts 4 (one at a time) per source unit or measure unit. 8 source or measure units in module Voltage Force: Range For Source Unit (SRCA):...
Page 115 Lesson 1 – Analog Modules Source Unit (SRCA) The source unit (software identifier: SRCA) in the multi-site baseband analog source & measure provides AWG function and PMU function. SRCA Pogo Output Amp Audio AWG Non-inverse LPF 1.5k, DAC 24-bit Unit 30k, Thru 1024 ksps Inverse...
Page 116 Lesson 1 – Analog Modules Audio AWG (1.024 Msps 24-bit) • Single-ended: 2 outputs (one at a time): X+ or X- – Differential: 1 output: X+&X- pair – • Video AWG (100 Msps 14-bit) Video AWG and Audio AWG functions share the pogo pins. –...
Page 117 Lesson 1 – Analog Modules Simultaneously Available Core Functions in Source Unit In the core functions of a source unit, the following combination can be used simultaneously: V source and any AWG, in any one of the following combinations: • –...
Page 118 Lesson 1 – Analog Modules Signal Routing in Source Unit Function Pins in MCA Module Single-ended Per source unit: output of 1 output at a time of 2 outputs: X+ or X- Audio AWG or Per Source&Measure module (per four source units): Video AWG Max.
Page 119 Common Trigger To each other unit (seven units) Module base section Master Clock Page 50 Agilent 93000 SOC Series Mi d Si l T i i Measure Unit (MESA) Functional Diagram (single-ended input and CT2 trigger pin) Pogo Pins Each unit (measure unit or source unit) in the MCA has four signal pogo pins (X+, X-, XX+, XX-).
Page 120 Lesson 1 – Analog Modules Audio digitizer (200 ksps 50 kHz-BW 24-bit) which contains two • digitizer cores — Abbreviation: ADGT or MCA-ADGT Audio digitizer core 1: Single-ended: 2 inputs (one at a time): X+ or X- – Differential: 1 input: X+&X- pair –...
Page 121 Lesson 1 – Analog Modules Simultaneously Available Core Functions in Measure Unit In the core functions of a measure unit, any one of the following three combinations can be used simultaneously in the unit: Audio digitizer Core 1 on X+/X- and •...
Page 122 Lesson 1 – Analog Modules Local DSP Each measure unit has DSP hardware (called local DSP), which can be used for processing data captured by the digitizer of the measure unit, instead of the processing by the system controller. As the local DSP processes the captured data and judges the pass/ fail results, uploading bulky capture data to the system controller is not needed, and thus, the upload time can be reduced.
Page 123 Lesson 1 – Analog Modules Function Pins in MCA Source&Measure Module Video DGT Per measure unit: normal 1 input: X+&X- pair mode Per Source&Measure module (per four measure units): Differential Max. 4 inputs simultaneously of 4 inputs: input (Unit5 E+&E- pair), (Unit6 F+&F- pair), (Unit7 G+&G- pair), and (Unit8 H+&H- pair) Direct Per measure unit: Mode...
Page 124 Lesson 1 – Analog Modules Function Pins in MCA Measure Module Audio DGT Per Measure module (per eight measure units): Single-ended Max. 16 inputs simultaneously of 32 inputs: input (Unit1 A+ or A-), (Unit2 B+ or B-), (Unit3 C+ or C-), (Unit4 D+ or D-), (Unit1 AA+ or AA-), (Unit2 BB+ or BB-), (Unit3 CC+ or CC-), (Unit4 DD+ or DD-), (Unit5 E+ or E-), (Unit6 F+ or F-), (Unit7 G+ or G-), (Unit8 H+ or H-), (Unit5 EE+ or EE-), (Unit6 FF+ or FF-), (Unit7 GG+ or GG-), and (Unit8 HH+ or HH-)
Page 125 Lesson 1 – Analog Modules Master Clock Distribution in MCA One master clock source can be selected for one MCA module, and the selected master clock is distributed to all the units, and is used by AWGs and digitizers. Each unit has its own timing generator, so a different sampling rate (Fs) can be set for each unit.
Page 126 Lesson 1 – Analog Modules Trigger Input in MCA An AWG or digitizer in each unit is triggered by a trigger signal from the trigger input pin. For each unit, one of the following pins can be configured as the trigger input pin of the unit. CT1 pin (common trigger) •...
Page 127 Lesson 1 – Analog Modules trigger delay, even if one common trigger pin is used in all units. For digitizers, the initial discard parameter can also be used to shift the capture start timing. The units that are never used simultaneously in any test in the •...
Page 128 Lesson 1 – Analog Modules Unit Trigger The XX+ pin in each unit can be the unit trigger pin. This example is shown in “Trigger System in MCA Module (the setup is an example)” on page 126. The unit trigger can trigger its own unit only.
Page 129: Addressing The Analog Modules
Lesson 2 Addressing the Analog Modules...
Page 130: Addressing The Analog Modules
Lesson 2 – Addressing the Analog Modules In this Lesson ... Overview This lesson informs you about how to address the analog modules and their pins. What you will learn After this lesson you will know the location of the analog boards plugged into the testhead, the associated pogo pin blocks on the DUT interface, and the pin configuration of each analog board.
Page 131: Locations Of Analog Boards In The Testhead
Locations of Analog Boards in the Testhead In the 93000 SOC Series test system, the analog modules, or their front-end components (for the Ultra High Speed AWG and the TIAs), are installed in designated slots of the testhead. There are two types of testheads: 512 pin type and 1024 pin type.
Page 132 Lesson 2 – Addressing the Analog Modules Slot Assignments Fill Order of Analog Board Each filling algorithm determines a certain order in which pogo pin groups will be filled with analog modules or digital channels. The following code names are used to represent analog modules in the following figure: SOURCE: Groups for AWGs WGA: High Resolution AWG (1 Msps 18-bit)
Page 133 The fill order of analog modules (in the Agilent 93000 SOC Series Configuration Guidelines) is as follows. In the figure, for example, “WGB/D -n” indicates either the High Speed AWG (WGB) or 500M AWG (WGD), and n is the fill order.
Page 134: Analog Pins Of The Board
Lesson 2 – Addressing the Analog Modules Analog Pins of the Board On the DUT board, each pogo pin group consists of 17 channels, and each channel consists of one signal contact and two related ground contacts as follows: Signal Pin Ground Pins Orientation Marker...
Page 135 Lesson 2 – Addressing the Analog Modules Arbitrary Waveform Generator (AWG) The High Resolution AWG (WGA), High Speed AWG (WGB) and 500M AWG (WGD) can generate a waveform at one of 8 single- ended or 4 differential channels. The 30M AWG (WGE) has two AWG cores. A WGE AWG core can generate a waveform at one of 4 single-ended or 2 differential channels.
Page 136 Lesson 2 – Addressing the Analog Modules Waveform Digitizers The High Resolution Digitizer (WDB), High Speed Digitizer (WDA), 100MHz Digitizer (WDG), and 1GHz Digitizer (WDD) can measure an analog waveform at one of 8 single-ended or 4 differential channels. The 20MHz Digitizer (WDE) has two digitizer cores. A WDE digitizer core can measure an analog waveform at one of 4 single- ended or 2 differential channels.
Page 137 Lesson 2 – Addressing the Analog Modules Time Interval Analyzer The Time Interval Analyzer (TIA) can measure a time interval for 7 input channels. In addition, two lines TRIG1 and TRIG2 are available to provide external arming signals to the TIA: Pin No DGND TRIG2...
Page 138 Lesson 2 – Addressing the Analog Modules Multi-site Baseband Analog Source&Measure / Multi-site Baseband Analog Measure The Multi-site Baseband Analog (MCA) modules contain eight units. For the E9714A MCA Source&Measure module, units 1 to 4 are the source units and units 5 to 8 are the measure units. For the E9715A MCA Measure module, all units are the measure units.
Page 139: Identification Of Analog Channels In The Software
Lesson 2 – Addressing the Analog Modules Identification of Analog Channels in the Software In the Pin Configuration Editor, a pin of an analog module is specified by the software identifier of the module + slot number and channel number: The analog module’s channel number is entered in the Mode column of the pin configuration editor, the software identifier and slot number in the Tester Channel column.
Page 140 Lesson 2 – Addressing the Analog Modules The following table shows the channel number assignments for single-ended connections. The numbers in the Ch column must be specified in the Pin Configuration Editor’s “MODE” column. Channel WDB, WDA, WDD, WDG, WGE, WGA, WGB, A+ (i/o/io) A+(core1)
Page 141 Lesson 2 – Addressing the Analog Modules Channel WDB, WDA, WDD, WDG, WGE, WDE SPA, TIA WGA, WGB, WGD A+, A- (i/o/io) A+, A-(B+) (o) A+, A-(core1) A+, A-(core1) A+, A- (i) N.A. (i/o/io) (i/o/io) B+, B- (i/o/io) N.A. B+, B-(core1) B+, B-(core1) B+, B- (i) N.A.
Page 142 Lesson 2 – Addressing the Analog Modules...
Page 143: Lesson 3
Lesson 3 Synchronization of Analog Modules...
Page 144: Synchronization Of Analog Modules
Lesson 3 – Synchronization of Analog Modules...
Page 145 Lesson 3 – Synchronization of Analog Modules In this Lesson ... Overview When testing mixed-signal devices with analog modules, the operation of the analog modules should be synchronized. This lesson explains important aspects of the synchronization of analog modules for mixed-signal testing. What you will learn After this lesson you will be familiar with important points to consider for synchronizing analog modules.
Page 146: Synchronization + Triggering
Lesson 3 – Synchronization of Analog Modules Synchronization + Triggering An analog module starts the operation when it receives a trigger signal. Normally the trigger signal for the analog module is provided by a digital channel. To send the trigger signal, you must connect the digital pin that provides the trigger signal and the trigger input pin of the analog module via a DUT board connection.
Page 147 Lesson 3 – Synchronization of Analog Modules Analog modules start measurement or waveform generation after a certain delay from the time the trigger signal is received. This delay time is called trigger-to-signal delay. Each analog module has a dedicated value of delay time. The following table shows the fixed trigger-to-signal delay and the accuracy in “( )”.
Page 148 Lesson 3 – Synchronization of Analog Modules Table 25 Parameters of 4.1G AWG Trigger-to-Signal Delay Sampling Frequency (Fs) X [s] Y [s] 4.00 GHz < Fs ≤ 4.10 GHz + 1/(32 × Fmclk) 14.34 x 10 + 223.5/Fs 0.6 x 10 3.15 GHz <...
Page 149 Lesson 3 – Synchronization of Analog Modules Example of signal-to-trigger delay and its effects for sampling the output of DAC: Trigger-to-Signal Delay Example for DAC Testing In addition, there are two kinds of signal delays that are caused by the electrical length of signal lines on the DUT board: Delay caused by the electrical length of the trigger line on the DUT •...
Page 150 Lesson 3 – Synchronization of Analog Modules Trigger line length Analog signal line length DUT Board Digital Trigger Analog input pogo pin Trigger-to-signal delay Digital Channel Analog Module Test Head Board Board (Side View) Delay Factors Trigger-to-signal delay in the analog module •...
Page 151: Adjusting The Synchronization Timing
Lesson 3 – Synchronization of Analog Modules Adjusting the Synchronization Timing Considering Trigger-to-Signal Delay Only If the trigger line delay and the signal line delay are much smaller than the trigger-to-signal delay, you can ignore trigger line length and signal line length. For example, if a digitizer is used to measure an analog signal from a DUT, you have to shift the rising edge location of the trigger signal to start the measurement at the desired timing by...
Page 152 Lesson 3 – Synchronization of Analog Modules Trigger Signal @digital pin Propagation delay of trigger line Trigger Signal @trigger input pin of analog module Trigger-to-signal delay Analog signal from AWG @signal pin of analog module Propagation delay of Analog signal from AWG signal line @DUT pin Delay to be reduced...
Page 153: Unit 3
DAC Test Setup and Execution Unit 3...
Page 154 Unit 3 – DAC Test Setup and Execution In this Unit ... Overview In this Unit you will learn how to use the tools of SmarTest to create and run a DAC test. With the DAC test serving as an example, you will be made familiar with many of the main capabilities of the tools.
Page 155: Lesson 1
Lesson 1 The Training DAC...
Page 156: The Training Dac
Related documents The general setup procedure and the tools for setting up the pins, levels, timing, and vectors have been discussed in the Agilent 93000 SOC Series User Training, Part 1. • Detailed information is available in the manual Agilent 93000 SOC Series “Test Setup”.
Page 157: Dac Basics
Lesson 1 – The Training DAC DAC Basics A DAC converts a digital value, which is applied via n data lines, into an analog voltage. DAC Block Diagram Example of a 3-bit DAC Vref digital code Vo = Vref DAC Block Diagram DAC Transfer Curve Linear DACs have a transfer characteristic as shown below: Discrete Analog...
Page 158 Lesson 1 – The Training DAC DAC Performance Specifications The parameters which describe the performance of a DAC are divided into: Static performance parameters • The static performance parameters describe non-linearity, gain and offset error. They are usually measured by sourcing a quasi- static (slow) digital ramp.
Page 159: Characteristics Of The Training Dac
Lesson 1 – The Training DAC Characteristics of the Training The DUT board for the mixed-signal training includes two mutually independent components – a DAC and an ADC. These devices have been chosen because they are not part of an ASIC (Application-Specific Integrated •...
Page 160 Lesson 1 – The Training DAC The digitizer needs a trigger pulse to start capturing. This trigger pulse is provided by a digital pin of the tester. DAC Connections The training DAC has 28 pins: DAC Pinout For the test, the DUT input and output signals are connected as shown below: DAC Signal Connections The analog output signal is terminated via a 50 Ω...
Page 161: Mixed-Signal Test Setup Procedure
In this training, steps 5 to 9 will be covered in detail. The other steps are performed with the standard setup tools, as taught in the Agilent 93000 SOC Series User Training, Part 1 and Part 2. These steps will only be described very shortly.
Page 162 Lesson 1 – The Training DAC Timing Step 3 You may wish to use individual device cycles for starting the analog module and while doing measurements. Vectors Step 4 At least one vector setup is always required—the setup of the digital pin that provides the start trigger.
Page 163 Lesson 1 – The Training DAC Examine the Results Step 9 Use the Mixed-Signal Tool to display the captured waveform • the processed waveform • the computed data (such as DNL, INL, FFT) • The Mixed-Signal Tool provides markers and tools for analyzing the graphical displays precisely.
Page 164: Summary And Discussion
Lesson 1 – The Training DAC Summary and Discussion You should now have a basic understaning of the training DAC and how it is connected to the digital pin electronics and the digitizer. Further, you know what the main steps are to set up and run a DAC test.
Page 165: Lesson 2
Lesson 2 Waveform Digitizer Setup with the Analog Setup Tool...
Page 166: Waveform Digitizer Setup With The Analog Setup Tool
After this lesson you will know the main capabilities of the Analog Setup Tool, and how to use it to set up a waveform digitizer. Related documents Detailed information about the Analog Setup Tool can be found in the manual Agilent 93000 SOC Series “Test Setup”. •...
Page 167: Functions Of The Analog Setup Tool
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Functions of the Analog Setup Tool The Analog Setup Tool is used for configuring the analog modules. The Analog Setup Tool works on a per-core basis. This means that you NO TE first select an analog module core.
Page 168 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Sequencer Programming The following figure shows the main building blocks of an analog module: General Block Diagram of Analog Modules Every analog module has its own independent sequencer which gets its instructions from a sequencer program in the sequencer memory.
Page 169 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Contents of an Analog Set Analog Signal Routing This is a read-only display provided by the Analog Setup Tool, based on the current routing setup. It shows the setting of the module’s relay multiplexer switches.
Page 170 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Operating Principles The following figure will help you to understand the underlying principles: Analog Setup Tool Operating Principles Analog Set An analog set defines for each analog module core that is used for the test: The hardware setup, including impedance, voltage range, and •...
Page 171 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool With the Analog Setup Tool, you create analog sets that contain all • setup information for the analog modules. An analog set includes the complete hardware sequencer and • clock domain setup for all cores, but not the routing of the signal lines.
Page 172 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Tools and Terms The Analog Setup Tool has four pages for setting up an analog module: Analog Setup Tool – Setup Pages The following slide illustrates the use of the Hardware Settings, Sequencer Memory, and Waveform Memory setup pages.
Page 173 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Analog Setup Tool – Using the Setup Pages Explanation: A trigger from a digital channel activates the analog module. This • trigger must be set up with the Vector Editor. Start delay and sample/sampling frequency can be specified on •...
Page 174 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool When editing a sequencer program, suitable waveform labels can • be chosen from a list, or can be created. The Waveform Memory page provides the option to change the size •...
Page 175: Starting The Analog Setup Tool
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Starting the Analog Setup Tool If the Pin Configuration File of the device contains analog pins, then the Analog Setup Tool can be started from the Analog tab of the SmarTest main tool bar.
Page 176 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool The Analog Setup Tool starts in Hardware Settings mode: Analog Setup Tool (Hardware Settings Page) For switching to other setup modes, use the S browser. ETUP...
Page 177: Core Selection And Global Functions
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Core Selection and Global Functions The first step after starting the Analog Setup Tool is always to check the current analog module core indicated in the B OARD and change it, if desired. How to Choose a Core When a core is selected, an identifier string is displayed in the field.
Page 178 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool or Data Manager: Analog setup icon Active analog set Saving the Analog Setup...
Page 179 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool How to Delete an Analog Set An Analog Setup File can hold up to 256 sets. The sets are identified by integer numbers from 1 to 256. Sets which are no longer needed can be deleted, using the Undefine Set button.
Page 180 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool How to Choose Your Favorite Editor A sequencer program consists of a series of sequencer commands which can be edited. You may wish to choose your favorite editor to be started from the Analog Setup Tool. This can be done with the C function.
Page 181: Setting Up The Analog Hardware
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Setting Up the Analog Hardware On the Hardware Settings page, the Analog Setup Tool shows for a waveform digitizer the defined analog pin connections at the left- hand side and a block diagram of the chosen core at the right- hand side.
Page 182 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Activate S to remove the empty sets HOW ONLY EDITED NALOG from the display. Highlight a set and click the EDIT button to edit this set. Overview of Edited Sets How to Enter the Hardware Setting The block diagrams provide browsers and entry fields that make it easy to set up the hardware-related parameters.
Page 183 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool How to Set Up the Timing Generator In the lower right-hand corner of the Hardware Settings page you find a box labeled S EQUENCER IMING ENERATOR Sequencer / Timing Generator Setup Box For a High Speed Digitizer, you can specify: The S to be executed.
Page 184: Setting Up Sequencer Program And Waveform Memory Labels
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Setting Up Sequencer Program and Waveform Memory Labels As long as the chosen analog set does not contain a sequencer program, the S box shows the EQUENCER IMING ENERATOR : __NOT_DEFINED__.
Page 185 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool If you enter a character string with the Analog Setup Tool, use only NO TE the characters A to Z, a to z, 0 to 9, and underscore. All other characters, including spaces, will be rejected.
Page 186 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool How to Edit the Command Line Proceed as follows: 1 Select Instruction. 2 Select Trigger reaction (if supported by module). 3 Set Initial hardware Discard. 4 Set No. Of Averages (if supported by module). 5 Select Waveform Label.
Page 187 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Example: Example of a sequencer program: 1 NOP POST Ramp_A_1 100 2 HALT POST Ramp_A_2 100 3 HALT POST Sine_B Trigger #1 Trigger #2 Trigger #3 ignored HALT pause HALT pause Acquire...
Page 188 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool How to Create a New Waveform Label If you have chosen __DEFINE_NEW_LABEL__ and clicked OK, the Allocate New Waveform Label window appears. Proceed as follows: 1 Type the name. Use only characters A to Z, a to z, 0 to 9, and underscore (no spaces).
Page 189 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Calculate Required Number of Samples is the number of samples that shall UMBER OF SAMPLES TO PROCESS be finally used for calculating the test results. Enter the types and number of software discards (SW disc.) or averaging you are planning to run before the result calculation.
Page 190 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool The actual processing of the waveform (averaging and discarding, per point or per waveform) on the workstation has to be specified in the yellow Test Control window, or in the test method used. The settings used for the calculation of sample points and those for the processing of the waveform must be consistent.
Page 191 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool The program list section provides the following options: The program list is sorted in alphabetical order. •Add: Inserts a new empty program. •Delete: Deletes the current program. •Copy: Copies the current program and stores it under a new name or a different analog module core.
Page 192: Reviewing And Changing The Waveform Memory
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Reviewing and Changing the Waveform Memory You may wish to review how the waveform memory of the current analog module core has been set up. You may also wish to modify the size of a Waveform Label, or to delete a label.
Page 193 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Choose __ALL_WAVEFORMS__. How to Change the Size of a Waveform Label This may be necessary, for example, if you decide that the captured waveform should be averaged at the workstation before further calculations are performed.
Page 194: Viewing The Relay Multiplexer Switches
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Viewing the Relay Multiplexer Switches The Hardware Settings page displays the relay multiplexer of the current analog module core as a blank box between the module connectors and the module block diagram. This display can be changed to view the relay switches by choosing from the A pull-down menu.
Page 195 Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool In the Analog Setup Tool you can only view the relay switches. To NO TE change their state you must define an appropriate routing set with the Routing Setup Tool and apply this set, for example, by running a testfunction or a test method.
Page 196: Summary And Discussion
Lesson 2 – Waveform Digitizer Setup with the Analog Setup Tool Summary and Discussion This lesson has made you familiar with the main capabilities of the Analog Setup Tool. You have seen how to use the Analog Setup Tool to set up the High Speed Digitizer.
Page 197: Lesson 3
Lesson 3 Setting up the Digitizers in the Digital Clock Domain...
Page 198: Setting Up The Digitizers In The Digital Clock Domain
Related documents The digital and analog clock domain, and how to set up analog modules in each, is described in detail in the manual Agilent 93000 SOC Series “Test Setup”. •...
Page 199: What Is A Clock Domain
Lesson 3 – Setting up the Digitizers in the Digital Clock Domain What is a Clock Domain A clock domain is a region in the testhead that can have its own, proprietary clock setting, independent of other regions. Each board (digital channel or analog module) in the testhead belongs to one or more clock domains.
Page 200: Clock Sources And Clock Distribution Overview
Lesson 3 – Setting up the Digitizers in the Digital Clock Domain Clock Sources and Clock Distribution Overview There are various options for the clock source that provides the master clock signal (MCLK) to a clock domain. The availability of these options depends on the test system configuration.
Page 201 Lesson 3 – Setting up the Digitizers in the Digital Clock Domain distribute the clock signal to the boards installed in the eight slots of the card cage. Clock Board Input and Output Lines There are three modes of operation for a clock board in a card cage which determine how to send the output clock signal to the eight boards installed in the slots of the card cage, and to the next card cage’s clock board via the Ring A and Ring B lines:...
Page 202 Lesson 3 – Setting up the Digitizers in the Digital Clock Domain The following figure shows the clock signal path to the WDB in the digital clock domain, with the internal master clock board as the clock signal source. Clock Signal Path to the WDB in the Digital Clock Domain...
Page 203: Digital Clock Domain Setup For The Digitizer
Lesson 3 – Setting up the Digitizers in the Digital Clock Domain Digital Clock Domain Setup for the Digitizer The Analog Setup Tool provides the Clock Domain Setup page to make the clock domain settings for all analog modules. The clock domain settings are part of an analog set, like, for example, the hardware settings.
Page 204 Lesson 3 – Setting up the Digitizers in the Digital Clock Domain The digital clock domain is selected as default when you open up the Clock Domain Setup page. Clock Domain Setup Page Defaults In the A field at the top of the page, the clock NALOG LOCK OURCE...
Page 205 Lesson 3 – Setting up the Digitizers in the Digital Clock Domain With the following procedure, you set up the WDB for the DAC test. All steps and setup options are explained, so that you will be able to also set up other analog modules using this procedure. Digital Clock Domain Setup for the WDB (1) Digital Clock Domain Setup for the WDB (2)
Page 206 Lesson 3 – Setting up the Digitizers in the Digital Clock Domain Final Digital Clock Domain Setup for the WDB (3) The calculation of the Fs value is performed according to the selected rule. The following example of a desired Fs of 36MHz for the WDA shows how the required divider N is calculated for the Auto (Fs) rule The range of valid N values depends on the physical...
Page 207 Lesson 3 – Setting up the Digitizers in the Digital Clock Domain Calculation of Fs and N These are the valid N values for all analog modules which divide the master clock to generate the sampling frequency Fs. Analog Module Nmin - Nmax * 98 –...
Page 208: Summary And Discussion
Lesson 3 – Setting up the Digitizers in the Digital Clock Domain Summary and Discussion This lesson has made you familiar with the concept of clock domains, and how to set up the clocking for the digitizers in the digital clock domain. You have learned how to use the Analog Setup Tool to choose a clock domain for an analog module and how to specify the settings for the module in the chosen digital clock domain.
Page 209: Lesson 4
Lesson 4 Defining the Signal Routing...
Page 210: Defining The Signal Routing
Routing Setup Tool to define the input/output routing for different analog modules and different measurement tasks. Related documents The Routing Setup Tool is described in detail in the manual Agilent 93000 SOC Series “Test Setup”. •...
Page 211: Analog Routing Basics
Lesson 4 – Defining the Signal Routing Analog Routing Basics All analog modules have a relay multiplexer which allows you to set the signal routes between input/output pins of the module and the module itself. This lets you select the input pin(s) to provide the input signal to a measurement module (digitizer, sampler, or TIA), or the output pin(s) to carry the output signal from a signal generating module (AWG).
Page 212 Lesson 4 – Defining the Signal Routing Routing for DC Measurements Routes from one input/output pin to another one are typically used to set up a loop-back (via designated DUT board lines) to another analog module. When testing the DAC, such a loop-back, will be used to perform measurements with the High Resolution Digitizer (WDB).
Page 213: Overview Of The Routing Setup Tool
Lesson 4 – Defining the Signal Routing Overview of the Routing Setup Tool The Routing Setup Tool can be started in several ways: from the Analog tab of the main Application Toolbar of SmarTest • from the Data Manager • from the Setup Dialog window of the Testflow Editor •...
Page 214 Lesson 4 – Defining the Signal Routing The Routing Setup Tool The window contains several sets of buttons for tool operation and a display area to show the routing commands that already exist in the currently selected routing set. Routing Set Handling Lets you select the routing set you want to edit, and allows you to copy and delete sets.
Page 215 Lesson 4 – Defining the Signal Routing directory. The following figure illustrates the contents of the routing setup file. Contents of the Routing Setup File Command Line Handling The Routing Setup tool lets you copy, paste and delete existing routing commands, and insert new ones. Just select a command line and click the appropriate button at the right hand side of the command line display area.
Page 216: Setting Up The Dac Routing
Lesson 4 – Defining the Signal Routing Setting up the DAC Routing The following figure shows the routing command construction area of the Routing Setup Tool. This area gets displayed, when you click the Edit button in the Routing Setup Tool window. Routing Command Construction Area A routing command consists of the routing task and the parameters which define the pins on which the routing task will...
Page 217 Lesson 4 – Defining the Signal Routing For details of the routing tasks, see the manual “Test Setup”, Chapter “Using the Routing Setup Tool”. For the DAC routing, you will need two routing sets. One for the DAC Linearity test and the other for the DAC Distortion test. The routing tasks Connect, Loop-back, Disconnect, and Flush will be used.
Page 218 Lesson 4 – Defining the Signal Routing The following steps define the routing set 1.
Page 219 Lesson 4 – Defining the Signal Routing When selecting the differential mode (DIFF), both the pins which will NO TE carry the non-inverted and the inverted signal (such as A+ and A–) get connected. However, only the pin for the non-inverted signal must be specified in the Resource field.
Page 220 Lesson 4 – Defining the Signal Routing first. The following figure shows the final routing set 2 definition. Routing Set 2 for DAC Distortion Test...
Page 221: Activating A Routing Set
Lesson 4 – Defining the Signal Routing Activating a Routing Set Once the Routing File has been downloaded to the tester, each routing set in the file can be chosen and activated. A routing set can be chosen in the Test Control window of the testfunction to be executed, as shown below, or in a test method by using the Routing.primary(set_number) function.
Page 222: Viewing The Active Routing
Lesson 4 – Defining the Signal Routing Viewing the Active Routing Once a routing set has been activated, for example, by executing a testfunction, you can display the current switch settings of the analog module’s relay multiplexer with the Analog Setup Tool. This may help debugging the test setup.
Page 223: Summary And Discussion
Lesson 4 – Defining the Signal Routing Summary and Discussion This lesson has made you familiar with the Routing Setup Tool. You have learnt how to use the tool to create routing commands and routing sets, and how to save these sets in the routing setup file.
Page 224 Lesson 4 – Defining the Signal Routing...
Page 225: Lesson 5
Lesson 5 Waveform Generation with the Mixed-Signal Tool...
Page 226 After this lesson you will know how to adapt the Mixed-Signal Tool to your needs and how to generate and download a stimulus waveform. Related documents More details can be found in the manual Agilent 93000 SOC Series “Test Setup”. •...
Page 227: Functions Of The Mixed-Signal Tool
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Functions of the Mixed-Signal Tool The Mixed-Signal Tool comprises tools for generating and downloading waveforms to be used as device • stimulus displaying and analyzing result waveforms • saving and restoring waveforms •...
Page 228 Lesson 5 – Waveform Generation with the Mixed-Signal Tool • NJECT ITTER • ABLE IMULATION These functions will not be discussed in this training. Detailed information can be found in the Test Setup manual. Waveform Download Generated waveforms can be downloaded either to a vector label as a pattern for digital pins (e.g.
Page 229: Starting The Mixed-Signal Tool
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Starting the Mixed-Signal Tool The Mixed-Signal Tool can be started from the Analog tab of the SmarTest main tool bar. Mixed-Signal Tool Starting the Mixed-Signal Tool from the SmarTest Main Tool Bar...
Page 230 Lesson 5 – Waveform Generation with the Mixed-Signal Tool The Mixed-Signal Tool main window is displayed: Mixed-Signal Tool Main Window The Mixed-Signal Tool window is comprised of three sections: General section • Waveform setup section • Waveform result section • Each of these sections has a menu bar.
Page 231: Customizing The Mixed-Signal Tool
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Customizing the Mixed-Signal Tool How to Customize the Main Window Displays To change the main window displays: In the general section menu bar, click the V button. This brings up the SelectView window. Choose Your View Check the waveform display areas you wish to show or hide.
Page 232 Lesson 5 – Waveform Generation with the Mixed-Signal Tool From the SelectView window, you can also change the color, line type, or interpolation mode of each waveform display area individually. How to Adjust the Waveform Displays Scaling and markers Every waveform display area has a title bar, vertical and horizontal scroll bars, context information at the left-hand side and below the waveform, one or two markers, and one or two marker indication rows.
Page 233 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Waveform Context Menu Choose A X to adjust the horizontal axis to the length of CALE the waveform. Choose A Y to adjust the vertical axis to the height of the CALE waveform.
Page 234: Saving And Restoring Waveforms
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Saving and Restoring Waveforms The contents of each waveform display area can be saved in a file and restored from that file. How to Save Waveforms To save the contents of a waveform display area in a file: In the general section menu, click the F I/O button.
Page 235 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Click OK. Enter the file name and click OK. How to Restore Saved Waveforms To load a saved waveform into one of the display areas: In the general section menu, click the F I/O button.
Page 236: Generating Waveforms
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Generating Waveforms This chapter deals with the waveform generation functions provided by the waveform setup section of the Mixed-Signal Tool. Waveform Setup Section with Menu Bar To generate a waveform: Click G ENERATE Choose the tool you wish to use.
Page 237 Lesson 5 – Waveform Generation with the Mixed-Signal Tool There are four tools for generating a waveform, as shown above. The Binary option is a special for testing of LAN devices. With the Marker option you can define a two level signal. Such a signal can be generated by the WGC in addition to the waveform output.
Page 238 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Waveform Description Parameters To describe the waveform: Choose the desired S from the list. HAPE Enter the number of P to be generated. ERIODS You can enter integer or decimal values (for example 0.5). Check or change the P .
Page 239 Lesson 5 – Waveform Generation with the Mixed-Signal Tool In floating point format, the sum of amplitude, offset, and noise should neither exceed 0.5 nor remain under –0.5. Otherwise the waveform will be clipped. Integer format Integer format can be used for DAC tests. In integer format, you take the DAC characteristics into account and enter numbers.
Page 240 Lesson 5 – Waveform Generation with the Mixed-Signal Tool How to Set the Operation and Output Values Parameters Whichever waveform generation tool you have chosen, each of them will ask you how to interpret and what to do with the new waveform: Operation and Output Value Settings To specify the use of the new waveform:...
Page 241 Lesson 5 – Waveform Generation with the Mixed-Signal Tool How to Use the Multitone Setup Tool The Multitone Setup Tool consists of three windows that allow you define the individual tones of the waveform in the frequency • domain, choose an algorithm to determine the phase offsets for the •...
Page 242 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Alternatively, you can load tone definitions you have created and saved before. Tone 0 Tone Tone 1 Display General Waveform Settings Tone 0 Tone 1 Tone Definition Multitone Definition in the Frequency Domain Click the >>...
Page 243 Lesson 5 – Waveform Generation with the Mixed-Signal Tool a set of random phase offsets is found, that produces a PRR within the given limits. Tone 0 Tone 1 Phase Algorithm Setup Window Click the >> button to perform the calculation of the multitone waveform in the time domain.
Page 244 Lesson 5 – Waveform Generation with the Mixed-Signal Tool How to Use the Waveform Equation Tool The Waveform Equation tool requires that you enter a mathematical formula which describes the desired waveform. Waveform Equation Input Window and Result To set up a waveform: Fill in T:= number to start from Fill in T<= running through Fill in T+= in steps of (increment)
Page 245 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Separate the numbers by spaces or returns. Waveform editor: Example: Point-by-Point Waveform Editor and Result Exit the editor via the F menu. A window is brought up that lets you make the O PERATION settings for the waveform generation, as explained UTPUT VALUE...
Page 246 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Tone 0 Tone 1 Marker Signal Setup To set up the marker signal: Fill in the sample at which the signal shall start. Enter the level (low or high) the signal shall start with Define the period (in number of samples of the waveform) the marker signal shall remain at high and a low level.
Page 247 Lesson 5 – Waveform Generation with the Mixed-Signal Tool How to Transform a Generated Waveform The Mixed-Signal Tool offers you manifold ways to transform (manipulate) the generated waveform. To transform (or translate) the generated waveform: Click T RANSLATE Waveform Translation Window Enter the desired function and click OK.
Page 248: Downloading A Generated Waveform
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Downloading a Generated Waveform This section deals with the waveform download functions provided by the waveform setup section of the Mixed-Signal Tool. How to Download a Generated Waveform to the Vector Memory If you wish to use the generated waveform for stimulating a DAC, you will download the waveform into the vector memory reserved for the respective pin group.
Page 249 Lesson 5 – Waveform Generation with the Mixed-Signal Tool Choose the R ANGE : The amplitude is adjusted to the size of the pin – CALE group. Binary code would yield 0 to FS (full scale), 2’s complement would yield –FS/2 to +FS/2 – 1. : The amplitude is not adjusted.
Page 250: Related Topics
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Related Topics How to download a generated waveform to an AWG will be discussed in Unit 4 which deals with ADC tests. The Mixed-Signal Tool supports not only generation and downloading of waveforms. Uploading and analyzing waveform data with the Mixed-Signal Tool will be demonstrated in the next lessons.
Page 251: Summary And Discussion
Lesson 5 – Waveform Generation with the Mixed-Signal Tool Summary and Discussion Now you know many of the functions of the Mixed-Signal Tool and how to use them. You learned how to: Customize the Mixed-Signal Tool window displays. • Generate all kinds of stimulating waveforms, using four different •...
Page 252 Lesson 5 – Waveform Generation with the Mixed-Signal Tool...
Page 253: Lesson 6
Lesson 6 Executing the DAC Linearity Test...
Page 254: Executing The Dac Linearity Test
DAC Linearity test, and how to display and interpret waveform results. Related documents The testfunctions are documented in the manual Agilent 93000 SOC Series “Standard Test Function Reference”. • The Mixed-Signal Tool is described in Agilent 93000 SOC Series “Test Setup”...
Page 255: Dac Linearity Measurements
Lesson 6 – Executing the DAC Linearity Test DAC Linearity Measurements DAC linearity is measured by applying a quasi-static digital ramp signal which covers the full code range. DAC linearity measurements include: • Differential Non-Linearity (DNL) • Integral Non-Linearity (INL) •...
Page 256 Lesson 6 – Executing the DAC Linearity Test Differential Non-Linearity can be calculated using the end point method, zero- point method, or minimum root mean square method. All three methods use the same formula. Only the definition of the DeviceLSB varies from method to method.
Page 257 Lesson 6 – Executing the DAC Linearity Test The other two methods consider all the measured values and derive the DeviceLSB from two sorts of linear regression calculations. For more information about the calculation of the DeviceLSB, see the Appendix “Definition of DAC and ADC Characteristics” on page 567.
Page 258 Lesson 6 – Executing the DAC Linearity Test Integral Non-Linearity can be calculated using the end-point method, zero- point method, or minimum root mean square method. All three methods use the same formula. Only the definition of the DeviceLSB and Vref varies from method to method.
Page 259 Lesson 6 – Executing the DAC Linearity Test Full Scale Gain Error (FS Gain) The full scale gain error measurement determines the difference between the expected and the real output voltage at maximal code. The gain error is also called proportional displacement. You can choose between several measurement units.
Page 260 Lesson 6 – Executing the DAC Linearity Test DAC LSB Gain Error in % of LSB For more information about the calculation of the LSB gain error, see the Appendix “Definition of DAC and ADC Characteristics” on page 567. DAC Gain Mismatch Gain mismatch measures the difference in full scale output values ) between two DACs.
Page 261: Dac Linearity Test Parameters
Lesson 6 – Executing the DAC Linearity Test DAC Linearity Test Parameters In the Test Control window you enter the parameters for the execution of the DAC Linearity testfunction. SOC DAC Linearity Test Control Window : The analog output pin or pins to be tested. •...
Page 262 Lesson 6 – Executing the DAC Linearity Test Test Methodology This section specifies further processing of the retrieved data before the actual calculation of results. You can specify averaging per point, per waveform, or both. • You can also specify certain data points and/or whole waveform •...
Page 263: Uploading Result Waveforms With The Mixed-Signal Tool
Lesson 6 – Executing the DAC Linearity Test Uploading Result Waveforms with the Mixed-Signal Tool This section deals with the waveform upload functions provided by the waveform result section of the Mixed-Signal Tool panel. Waveform Result Section with Menu Bar Depending on the selected view, the waveform result section shows 1, 2, or 3 waveform display areas.
Page 264 Lesson 6 – Executing the DAC Linearity Test Before you attempt to upload waveform data, ensure that the test NOTE flow flag “Debug Analog” has been enabled. Only if this flag is set, the waveform data gets stored in a temporary file which will then be read by the Mixed-Signal Tool.
Page 265 Lesson 6 – Executing the DAC Linearity Test Enable R to always update EFRESH ELECTED DATA AUTOMATICALLY the displays of the Mixed-Signal Tool as soon as new test data is available. Enable A . This ensures that uploaded UTOSCALE WHILE PLOAD waveforms are completely visible on the display.
Page 266: Displaying Logged Waveforms With The Mixed-Signal Tool
Lesson 6 – Executing the DAC Linearity Test Displaying Logged Waveforms with the Mixed-Signal Tool You may wish to use the Event Datalog capabilities for mixed- signal tests. Event Datalogging can store captured, processed, as well as computed waveforms in a file. To log waveforms that are captured or calculated during a mixed- NOTE signal test with Event Datalogging you must activate the test suite flag...
Page 267 Lesson 6 – Executing the DAC Linearity Test Datalog Waveform Selection Window If you see the message “No Waveform” as shown in the figure above, the file does not contain any waveforms that can be displayed. Possible reasons are: The loaded file is not a Datalog file. •...
Page 268 Lesson 6 – Executing the DAC Linearity Test As the Datalog file can contain multiple waveforms of the same type (for example, DAC Distortion FFT, calculated for several pins), the waveforms are simply numbered in the order as they appear in the log file. Datalog Waveform Selection Example Context Information Once you have chosen a waveform to be displayed, the context...
Page 269 Lesson 6 – Executing the DAC Linearity Test The logged data of a DAC distortion test may look as shown below: Display of Logged Waveforms If the waveform is not fully displayed, use the A button. CALE...
Page 270: Related Topics
Lesson 6 – Executing the DAC Linearity Test Related Topics With the Mixed-Signal Tool, it is also possible to analyze spectral data. These functions of the Mixed-Signal Tool which include the calculation of harmonics or the coherent reconstruction of captured data will be discussed in the next lesson. They are most useful for debugging distortion tests.
Page 271: Summary And Discussion
Lesson 6 – Executing the DAC Linearity Test Summary and Discussion This lesson provided an overview of the DAC linearity parameters and their calculation. You have learned how to set up the testfunction for the DAC Linearity test. You now know how to use the Mixed-Signal Tool for uploading and displaying result waveforms of a mixed-signal test.
Page 272 Lesson 6 – Executing the DAC Linearity Test...
Page 273: Lesson 7
Lesson 7 Executing the DAC Distortion Test...
Page 274: Executing The Dac Distortion Test
Related documents More details about the testfunction can be found in the manual Agilent 93000 SOC Series “Standard Test Function Reference”. • The Mixed-Signal Tool is described in Agilent 93000 SOC Series “Test Setup”...
Page 275: Dac Distortion Measurements
Lesson 7 – Executing the DAC Distortion Test DAC Distortion Measurements DAC distortion is usually measured by sourcing a digital sine wave. The analog response is first captured and then analyzed in the frequency domain. This means, the processed waveform is converted into its spectrum using the FFT algorithm, and the calculations are based on the frequency components.
Page 276 Lesson 7 – Executing the DAC Distortion Test Coherent Sampling In order to obtain a pure spectrum, coherent sampling has to be established. Fundamental Unit Test Period (UTP) Frequency cycles Harmonic Nyquist 1/UTP Frequency = 16 points sample sample cycles cycles points sample...
Page 277 Lesson 7 – Executing the DAC Distortion Test Total Harmonic Distortion The total harmonic distortion (THD) compares the combined power of the first N harmonics with the power of the input signal. The THD is calculated as the ratio of the rms sum of the first N harmonic components (typically up to the 5th harmonic) to the rms value of a full-scale input signal.
Page 278 Lesson 7 – Executing the DAC Distortion Test Signal-to-Noise plus Distortion The SND compares the power of the input signal with the combined power of the harmonics and noise. SND is calculated as the ratio of the rms value of the input signal to the rms sum of all other spectral components below Nyquist frequency, including everything but DC.
Page 279 Lesson 7 – Executing the DAC Distortion Test Calculation of Signal Resolution...
Page 280: Dac Distortion Test Parameters
Lesson 7 – Executing the DAC Distortion Test DAC Distortion Test Parameters In the DAC Distortion Test Control window you can specify the tests to be performed, and the test parameters. SOC DAC Distortion Test Control Window , and R are filled in as for the DAC IN LIST OG LIST...
Page 281 Lesson 7 – Executing the DAC Distortion Test Test Methodology This section specifies the processing of the captured data after uploading and before performing any calculations. You can specify averaging per waveform. This requires that you source the same sine wave several times. Calculation Parameter : This is the frequency range of the FFT results that •...
Page 282: Analyzing Spectral Data With The Mixed-Signal Tool
Lesson 7 – Executing the DAC Distortion Test Analyzing Spectral Data with the Mixed-Signal Tool The Mixed-Signal Tool supports the analysis of data in the frequency domain by Coherent reconstruction • Harmonics calculation • These are general processes for analyzing spectral data. The data NOTE does not need to downloaded using coherent reconstruction, when retrieving the results of the DAC Distortion test.
Page 283 Lesson 7 – Executing the DAC Distortion Test If this checkbox is enabled, the uploaded data will be reconstructed as coherent data, that means the data will be compressed into one signal cycle. This requires: You upload only data of one UTP (unit test period). One UTP is the •...
Page 284 Lesson 7 – Executing the DAC Distortion Test Coherent Reconstruction of a Captured Sinewave When the Mixed-Signal Tool panel has been set up to display only one NOTE waveform, two markers are available which can be used to perform precise measurements. Calculation of Harmonics The H function can be used to calculate the harmonic...
Page 285 Lesson 7 – Executing the DAC Distortion Test Harmonics Window You can enter the fundamental frequencies to be used for the calculation, and you can specify the amount of data to be calculated. : Five checkboxes to specify the kind of results to be •...
Page 286 Lesson 7 – Executing the DAC Distortion Test The I column shows the type and origin of the resulting harmonic frequencies. The harmonics for two fundamentals are calculated according to: Abbrev. Meaning Formula for 2 Fundamentals Fundamentals (generated F1 , F2 signal frequencies) 2nd order distortion 2 * F1 , 2 * F2...
Page 287: Summary And Discussion
Lesson 7 – Executing the DAC Distortion Test Summary and Discussion This lesson has started with an overview of the DAC distortion parameters and their calculation. You have learned how to set up the DAC Distortion testfunction to perform the distortion tests according to your test requirements. You now know how to use the functions of the Mixed-Signal Tool for analyzing spectral data.
Page 288 Lesson 7 – Executing the DAC Distortion Test...
Page 289: Unit 4
ADC Test Setup and Execution Unit 4...
Page 290: The Training Adc
Unit 4 – ADC Test Setup and Execution In this Unit ... Overview This Unit comprises: Description of the training ADC and its characteristics. • ADC Test Setup procedure • ADC linearity test control and execution. • ADC distortion test control and execution. •...
Page 291: Lesson 1
Lesson 1 The Training ADC...
Page 292 After this lesson you will know the operation principles of ADCs, the general test setup for ADC tests, and the main characteristics for the training ADC. Related documents Detailed information about all Setup Tools is available in the manual Agilent 93000 SOC Series “Test Setup”. •...
Page 293: Adc Basics
Lesson 1 – The Training ADC ADC Basics A/D vs. D/A Converters An ADC is not the mathematical inverse of a DAC. This means that ADC testing requires different test procedures than DAC testing. Common parameters like integral non-linearity (INL) and differential non-linearity (DNL) are defined differently for the two types and hence measured differently.
Page 294 Lesson 1 – The Training ADC If ADCs are tested this way, many will pass, even with rather different transfer curves. This is illustrated in the following figure, where both ADCs return the same code: Output of ADC #1 Input voltage Output of ADC #2 Input voltage Rudimentary ADC Testing...
Page 295 Lesson 1 – The Training ADC Linear vs. Non-Linear Converters This training concentrates on linear DACs and ADCs. Of course, there are also non-linear DACs and ADCs. Discrete digital Discrete digital output values output values – – Analog input Analog input voltage voltage Linear ADC...
Page 296 Lesson 1 – The Training ADC +Vref 2 -1 comparators Analog input n lines –Vref Sampling clock Flash ADC Block Diagram ADC Input-Output Chart Linear ADCs have a transfer characteristic as shown below: Binary Output Code code width code code transition center 1 LSB 3/4 7/8...
Page 297 Lesson 1 – The Training ADC The first code transition (from zero to one) of an ideal ADC occurs at the analog equivalent of 0.5 LSB. The last code transition (from 2 – 2 to 2 – 1, where n = number of bits) of an ideal ADC occurs at the analog equivalent of FS –...
Page 298 Lesson 1 – The Training ADC ADC Performance Specifications The parameters which describe the performance of an ADC are divided into: Static performance parameters ADC Static Performance Parameters Dynamic performance parameters ADC Dynamic Performance Parameters...
Page 299: Test Setup Overview For Adc Tests
Lesson 1 – The Training ADC Test Setup Overview for ADC Tests ADC tests are generally set up as shown below: Setup for Testing an ADC The ADC is stimulated by an arbitrary waveform generator. The digital analog response is captured by the digital pins. The generator needs a trigger pulse to start generating the analog signal, and the DUT needs a conversion clock signal.
Page 300 In this training, steps 5 to 10 will be explained in detail. The other steps are performed with the standard setup tools, as taught in the Agilent 93000 SOC Series User Training, Part 1 and Part 2. These steps will only described shortly, and carried out by you in...
Page 301: Characteristics Of The Training Adc
Lesson 1 – The Training ADC Characteristics of the Training The ADC on the DUT board for the mixed-signal training is the 8- bit A/D converter TLC5510 from Texas Instruments. The data sheet of the ADC is included in the Appendix. NO TE ADC Description The 8-bit A/D converter TLC5510 is a variation of flash converter...
Page 302: Summary And Discussion
Lesson 1 – The Training ADC Summary and Discussion This lesson has started with a short summary of the ADC basics. Next, you learned about the general test system setup for and ADC test, and the test setup procedure. We have also introduced the ADC used in the training.
Page 303: Lesson 2
Lesson 2 Setting Up the Waveform Generator...
Page 304: Setting Up The Waveform Generator
Tool and the Routing Setup Tool has been given in Unit 3. Detailed information on the Analog Setup Tool, the Mixed-Signal Tool and the Routing Setup Tool can be found in the manual Agilent 93000 SOC Series “Test Setup” •...
Page 305: Waveform Generator Setup With Analog Setup Tool
Lesson 2 – Setting Up the Waveform Generator Waveform Generator Setup with Analog Setup Tool The following diagram illustrates the necessary components of the AWG setup (sequencer program, waveform labels, waveforms and hardware settings), with which tools of SmarTest they are created, and how all these components are used by the AWG to generate the final signal output.: Overview of AWG Setup Components and AWG Operation...
Page 306 Lesson 2 – Setting Up the Waveform Generator Analog Setup Tool (WGA Setup for ADC Test) In Hardware Settings mode, the Analog Setup Tool shows for a waveform generator the defined analog pin connections at the right-hand side and a block diagram of the chosen core at the left- hand side.
Page 307 Lesson 2 – Setting Up the Waveform Generator levels by entering the AC and DC voltages. For this, select the AC/ DC from the O pull-down menu. UTPUT OLTAGE Calculation of Attenuation and Offset Voltage is the impedance (the load) at the output pin of the AWG module. NO TE depends on the DUT and on the DUT board design.
Page 308 Lesson 2 – Setting Up the Waveform Generator execute the sequencer program from this Sub Label on, instead from the beginning. The S or S (these fields are AMPLE REQUENCY AMPLE ERIOD mutually dependent) will be filled in automatically when the sample frequency for the WGA has been defined in the clock domain setup.
Page 309 Lesson 2 – Setting Up the Waveform Generator Editing a New, Empty Sequencer Program...
Page 310 Lesson 2 – Setting Up the Waveform Generator The AWG supports the following instructions: The sequencer executes the next instruction as soon as it has finished • NOP generating the waveform specified in the NOP command line. The sequencer repeats the generation of the waveform specified in the RPT •...
Page 311 Lesson 2 – Setting Up the Waveform Generator Example: Sequencer Programming Examples for an AWG Explanation: In the upper example, the generation of waveform B gets repeated • for five times. In the lower example, the generation of the waveforms A, B, and C •...
Page 312 Lesson 2 – Setting Up the Waveform Generator Creating Sequencer Program Lines To define the sequencer program lines: Edit the default sequencer command line. Editing a Sequencer Command Line Define a waveform label: Defining a Waveform Label The button SW AVG/DSC is only useful for waveform digitizers. Add sub-labels (branch addresses) as needed.
Page 313 Lesson 2 – Setting Up the Waveform Generator Viewing the Contents of a Waveform Label This is a useful feature to check a waveform after the waveform data has been downloaded with the Mixed-Signal Tool. Highlight a command line. Click the W button.
Page 314 Lesson 2 – Setting Up the Waveform Generator To start the sequence program from the desired sequence line by using the trigger signal, you must do the following actions: Prepare a sequence program in the Sequencer Memory setup page of the Analog Setup Tool: Set the dummy data at the first line of the sequence program.
Page 315 Lesson 2 – Setting Up the Waveform Generator Hardware Settings page Sequencer Memory setup page Sequencer Instructions Sub Label Sequencer / Timing Generator 0 HALT DC_0V_512pts Sine_Waveform Sequencer Program Test1_Waveform Sine_512pts Sub Program Sine_Waveform HALT Sine_512pts Analog Setup Tool Sequence for dummy waveform When the hardware module settings Dummy waveform are downloaded and activated...
Page 316 Lesson 2 – Setting Up the Waveform Generator Clock Domain Setup for the WGA...
Page 317: Defining And Downloading A Waveform To The Awg
Lesson 2 – Setting Up the Waveform Generator Defining and Downloading a Waveform to the AWG The waveforms to be sourced to a mixed-signal device can be conveniently created, stored, and reloaded with the Mixed-Signal Tool. Generating a Waveform To generate a waveform: Click the G button of the Mixed-Signal Tool.
Page 318 Lesson 2 – Setting Up the Waveform Generator Downloading the Generated Waveform to the AWG To use the generated waveform for stimulating the ADC, you need to download the waveform into the waveform memory of the respective arbitrary waveform generator. The number of data points to be downloaded is defined by the length NOTE of the generated waveform.
Page 319 Lesson 2 – Setting Up the Waveform Generator When downloading, you may get a message like this: Insufficient Waveform Label Size Message If you click OK, your waveform will be truncated to fit into the array defined by the waveform label size you specified in the Analog Setup Tool.
Page 320: Signal Routing
Lesson 2 – Setting Up the Waveform Generator Signal Routing You need to specify a routing set for the ADC test with the Routing Setup Tool. The usage of the tool was described in “Defining the Signal Routing” on page 209. The following figure shows the routing command you need to define to connect the WGA to the output pin ADC_WGA that is connected to the analog input pin of the ADC.
Page 321: Summary And Discussion
Lesson 2 – Setting Up the Waveform Generator Summary and Discussion In this lesson, you have learnt about the set up of the arbitrary waveform generator for the execution of the ADC tests. You now know what each mixed-signal tool is used for when setting up the AWG: The Analog Setup Tool for hardware settings, sequencer program •...
Page 322 Lesson 2 – Setting Up the Waveform Generator...
Page 323: Lesson 3
Lesson 3 Setting Up the Digital Capturing...
Page 324: Setting Up The Digital Capturing
Lesson 3 – Setting Up the Digital Capturing In this Lesson ... Overview In this lesson deals with the Digital Capture capabilities of the Agilent 93000 SOC Series, and how to use it for ADC testing. The lesson covers the topics: Introduction to Digital Capture •...
Page 325: Introduction To Digital Capture
This is called digital capturing. The Digital Capture feature of the Agilent 93000 SOC Series allows you to perform digital capturing with any normal digital pin. This gives you maximum flexibility for your DUT board design, and makes the setup for digital capturing easy.
Page 326 Lesson 3 – Setting Up the Digital Capturing captured data in Standard Mode, or 512 M samples in Double Mode (the capture modes will be explained below). However, the actual size of free vector memory that is available for captured data is limited by the source vectors for other tests that are already stored in the vector memory.
Page 327 Lesson 3 – Setting Up the Digital Capturing Series. Capturing can be performed at up to 32 capture pins in parallel. Digital Capture Data Rates...
Page 328: Setup For Digital Capture
The normal sequence for the setup of Digital Capture is: Digital Capture Setup Sequence Pins for Digital Capture The Agilent 93000 SOC Series uses normal digital pins (also called digital channels) for data capturing. No additional capture hardware is required. This gives you the flexibility to perform data capturing at any available digital pin of the test system.
Page 329 Lesson 3 – Setting Up the Digital Capturing Setting up the Levels Levels for digital capture pins can be defined in the same way as for standard digital output pins. This is done in the Level Setup window. When capturing digital data, for example, to obtain the generated output codes of an ADC, typically not the quality of the output signal levels is of interest (these would be tested with other tests), but only whether a 1 or a 0 is received.
Page 330 Lesson 3 – Setting Up the Digital Capturing Setting up the Timing for Sequential Capturing When using the Sequential Capture Mode, capturing will be performed on edge 1 in Standard Mode • edge 1 and edge 4 in Double Mode •...
Page 331 Lesson 3 – Setting Up the Digital Capturing Setting up the Timing for Selective Capturing Selective Capturing lets you define for every vector of a capture label whether you want data to be captured or not. Especially when highest speed of capturing is needed, this mode is to be preferred over the Sequential Mode, as the transfer of undesired data to the workstation and later blending out of this data by means of a vector variable can be avoided.
Page 332 Lesson 3 – Setting Up the Digital Capturing The syntax for using 14 edges, is shown in the following example: Selective Capture Timing Syntax In the following section you will see an example of how to use the capture/do not capture waveforms in a vector label. When defining selective capture actions (C and D actions) in a wave NOTE table, some capabilities of the Device Cycle Expander will be used...
Page 333 Lesson 3 – Setting Up the Digital Capturing E R R O R S "WAVE TABLES" ERROR: line X: No more set space ("Y"). CAPTURE cannot be defined Setting up the Vectors As mentioned before, the device input vectors for Digital Capture must reside in the sequencer memory.
Page 334 Lesson 3 – Setting Up the Digital Capturing The number of vectors taking samples must be multiple of 64. • The multiple of 64 is necessary because the data transfer to the vector memory during capturing (writing), and also from the vector memory when retrieving captured data (reading) is performed in blocks of captured data of 64 vectors.
Page 335 Lesson 3 – Setting Up the Digital Capturing For Selective Capturing: You should use a designated ‘capture’ device cycle and also a • designated ‘do not capture’ device cycle in the vectors to determine at which vector data is to be captured and at which vector not.
Page 336 Lesson 3 – Setting Up the Digital Capturing Digital Capture Settings The Sequential or Selective Capture Mode cannot be selected here. NOTE The mode is determined by the selected capture vector label. If this vector label uses a wave table that contains selective capture actions (‘C’...
Page 337 Lesson 3 – Setting Up the Digital Capturing Defining a Vector Variable A vector variable is always related to one specific vector label and cannot be used with another one. Setup Window for a Vector Variable Enter the name for the vector variable. Check the box Show only DIGCapt pins if you want to see only capture pins in the pin list.
Page 338 Lesson 3 – Setting Up the Digital Capturing Captured Data pin_1 1 0 1 1 0 ... 0 1 0 0 1 ... pin_2 pin_3 1 0 1 1 0 ... Sample (3 bits) 1 0 1 0 1 0 Parallel Transfer Mode In serial mode, only one pin must be selected in the vec variable pins field.
Page 339 Lesson 3 – Setting Up the Digital Capturing had been taken with half the sample rate. nr frame interdisc: the number of samples to be skipped between frames. When all settings have been made, click D Examples The following to example illustrates how a vector variable defines a sub-set of captured samples.
Page 340: Summary And Discussion
Lesson 3 – Setting Up the Digital Capturing Summary and Discussion In this lesson you have learned how to prepare the system for capturing and uploading digital data. The setup procedure is simple and straightforward: Setup Procedure for Digital Capturing The concept of vector variables makes extracting of sub-sets of captured data easy.
Page 341: Lesson 4
Lesson 4 Executing the ADC Linearity Test...
Page 342: Executing The Adc Linearity Test
ADC Linearity test, and how to display the waveform results. Related documents The testfunctions are documented in the manual Agilent 93000 SOC Series “Standard Test Function Reference”. • The Mixed-Signal Tool is described in Agilent 93000 SOC Series “Test Setup”...
Page 343: Adc Linearity Measurements
Lesson 4 – Executing the ADC Linearity Test ADC Linearity Measurements The parameters that describe the linearity of an ADC have the same names as those used for describing the linearity of a DAC. But they are calculated differently. • Differential Non-Linearity (DNL) •...
Page 344 Lesson 4 – Executing the ADC Linearity Test ADC Differential Non-Linearity, DNL ADC DNL is calculated from the transition voltages which are in turn calculated from the histogram of the captured data points. ADC Differential Non-Linearity, DNL ADC Integral Non Linearity, INL ADC INL measures the deviation of each code center point from an ideal straight line.
Page 345 Lesson 4 – Executing the ADC Linearity Test ADC Offset Error ADC offset error measures the analog input voltage range that leads to output code zero. Binary Output Code Ideal code center line Actual code center line 1/4 FS 1/2 FS 3/4 FS Offset Analog Input Error...
Page 346 Lesson 4 – Executing the ADC Linearity Test To calculate FS gain error and LSB gain error, the following formulas are used: Calculation of ADC Gain Error...
Page 347: Adc Linearity Test Parameters
Lesson 4 – Executing the ADC Linearity Test ADC Linearity Test Parameters In the Test Control window you enter the parameters for the execution of the ADC Linearity testfunction. SOC ADC Linearity Test Control Window : The vector variable to be used to retrieve the captured •...
Page 348 Lesson 4 – Executing the ADC Linearity Test to methods used for the DAC tests. See the Appendix “Definition of DAC and ADC Characteristics” on page 567 for more information. Waveform Capture Parameters : Type in the pin name for the waveform generator. This •...
Page 349: Uploading Result Waveforms With The Mixed-Signal Tool
Lesson 4 – Executing the ADC Linearity Test Uploading Result Waveforms with the Mixed-Signal Tool Uploading and displaying ADC result waveforms with the Mixed- Signal Tool is done in the same way as described in the previous Unit for the DAC test. Typical configurations are: Mixed-Signal Tool Display Configurations How to Specify Upload Parameters...
Page 350 Lesson 4 – Executing the ADC Linearity Test Upload Configuration Window...
Page 351: Summary And Discussion
Lesson 4 – Executing the ADC Linearity Test Summary and Discussion This lesson provided an overview of the ADC linearity parameters and their calculation. You have learned how to set up the testfunction for the ADC Linearity test. You know how to use the Mixed-Signal Tool for uploading and displaying the result waveforms of an ADC Linearity test.
Page 352 Lesson 4 – Executing the ADC Linearity Test...
Page 353: Lesson 5
Lesson 5 Executing the ADC Distortion Test...
Page 354: Executing The Adc Distortion Test
After this lesson you will know how set up the DAC Distortion testfunction. Related documents More details about the testfunction can be found in the manual Agilent 93000 SOC Series “Standard Test Function Reference”. • The Mixed-Signal Tool is described in Agilent 93000 SOC Series “Test Setup”...
Page 355: Adc Distortion Measurements
Lesson 5 – Executing the ADC Distortion Test ADC Distortion Measurements ADC distortion is usually measured by sourcing a sine wave. The digital response is first captured and then analyzed in frequency domain. This means, the processed waveform is converted into its spectrum using the FFT algorithm, and the calculations are based on the frequency components.
Page 356 Lesson 5 – Executing the ADC Distortion Test Even an ideal ADC produces a quantization error which can be seen as a sawtooth function. Ideal ADC Binary Output Code Analog Input Quantization Error +1/2 LSB Analog Input –1/2 LSB ADC Quantization Error But other factors also reduce the available resolution: Calculation of N...
Page 357: Adc Distortion Test Parameters
Lesson 5 – Executing the ADC Distortion Test ADC Distortion Test Parameters In the Test Control window you enter the parameters for the execution of the ADC Distortion testfunction. SOC ADC Distortion Test Control Window , and R are entered as for the ADC EC LIST OG LIST OUT LIST...
Page 358 Lesson 5 – Executing the ADC Distortion Test : Synchronous or asynchronous. • : Specify the resolution of the ADC as number of bits. • ESOLUTION Synchronous mode means synchronized start of AWG and digital waveform capturing. The delay between the AWG trigger pulse and the waveform start must be specified with the Analog Setup Tool.
Page 359 Lesson 5 – Executing the ADC Distortion Test Uploading the Result Waveforms with the Mixed- Signal Tool Uploading and displaying the result waveforms with the Mixed- Signal Tool is done in the same way as described before for the other ADC and DAC tests.
Page 360: Summary And Discussion
Lesson 5 – Executing the ADC Distortion Test Summary and Discussion This lesson has started with an overview of the ADC distortion parameters and their calculation. You have then learned how to set up the DAC Distortion testfunction to perform the distortion tests according to your test requirements.
Page 361: Unit 5
Using the Analog Clock Domain Unit 5...
Page 362 Unit 5 – Using the Analog Clock Domain In this Unit ... Overview This Unit comprises: A description of the analog clock domain, its clock sources and the • distribution of the clock signal to the analog modules. A description of the setup parameters for the analog clock domain •...
Page 363: Lesson 1
Lesson 1 Analog Clock Domain Description...
Page 364 Lesson 1 – Analog Clock Domain Description In this Lesson ... Overview This lessons briefly repeats the concept of clock domains and explains the choices of clock sources for the domains, focussing on the analog clock domain. Further, you will learn how the clock signals of the various clock sources are distributed between the card cages and to the analog modules in the slots of the card cages.
Page 365: Clock Domains Summary
Lesson 1 – Analog Clock Domain Description Clock Domains Summary The clock domain concept was already explained in “What is a Clock Domain” on page 199. Here is a short summary: A SOC Series test system supports two different clock domains. The digital clock domain •...
Page 366: Clock Sources And Clock Distribution
Lesson 1 – Analog Clock Domain Description Clock Sources and Clock Distribution Clock Sources For both the digital and the analog clock domain, there are more than one clock source options. In general, the clock can either be supplied by a testhead internal clock board, or by an external clock source, called Alternate Master Clock (AMC).
Page 367 Lesson 1 – Analog Clock Domain Description Selecting the Digital Domain Clock Source Also the clock frequency is set in the timing setup. It cannot be set in the Clock Domain Setup page of the Analog Setup Tool. This has been described in “Digital Clock Domain Setup for the Digitizer”...
Page 368 Lesson 1 – Analog Clock Domain Description Also the clock frequency is set in Clock Domain Setup page. This is described in the next lesson. The selected clock is supplied to all analog modules you set to be connected to the analog clock domain. This is independent of the card cages in which the modules are installed.
Page 369 Lesson 1 – Analog Clock Domain Description Clock Distribution to the Analog Card Cage Slots The clock frequency range of the AMC is 200 - 500 MHz. It should be noted, that the AMC requires considerably more time for NO TE changing and stabilizing its output frequency than the clock board —...
Page 370: Clock Distribution Between Card Cages
Lesson 1 – Analog Clock Domain Description Clock Distribution between Card Cages This section summarizes the clock distribution between the card cages of the testhead for the digital and for the analog clock domain. In the previous section, the clock distribution to the slots in an analog card cage was shown.
Page 371 Lesson 1 – Analog Clock Domain Description (analog domain) C. Cage 1 C. Cage 3 C. Cage 4 C. Cage 2 Master Slave Slave Slave (digital domain) Ext. Ext. Ext. Ext. Local PLL Local PLL Local PLL External External External Ring Ring Ring...
Page 372 Lesson 1 – Analog Clock Domain Description C. Cage 5 C. Cage 3 C. Cage 8 C. Cage 2 Master Slave Slave Slave Ext. Ext. Ext. Ext. Local PLL Ring Ring Ring RING A RING A RING A RING A Ring Ring Ring...
Page 373 Lesson 1 – Analog Clock Domain Description (analog domain) C. Cage 5 C. Cage 3 C. Cage 8 C. Cage 2 Master Slave Slave Slave (digital domain) Ext. Ext. Ext. Ext. Local PLL Local PLL Local PLL External External External Ring Ring Ring...
Page 374 Lesson 1 – Analog Clock Domain Description provides a more stable and precise reference and ensures a stable frequency relationship between the digital and analog domain. The reference signal is generated by the AMC in addition to the AMC clock signal.
Page 375: Summary And Discussion
Lesson 1 – Analog Clock Domain Description Summary and Discussion In this lesson you have learned which clock sources are available for the digital and the analog clock domain, and how their clock signals are distributed in the system. This is the background knowledge you will need to understand the options and parameters when setting up an analog module in the analog clock domain, as described in the next lesson.
Page 376 Lesson 1 – Analog Clock Domain Description...
Page 377: Lesson 2
Lesson 2 Analog Clock Domain Setup...
Page 378 Lesson 2 – Analog Clock Domain Setup In this Lesson ... Overview This lessons explains the setup parameters for the analog clock domain and describes the procedure how to set up analog modules in the analog clock domain. Several clock domain parameters and specific parameters for analog modules must be set.
Page 379: Overview Of Analog Clock Domain Setup Parameters
Lesson 2 – Analog Clock Domain Setup Overview of Analog Clock Domain Setup Parameters The Analog Setup Tool provides the Clock Domain Setup page to make the clock domain settings for all analog modules. The clock domain settings are a part of an analog set, like, for example, the hardware settings.
Page 380 Lesson 2 – Analog Clock Domain Setup Analog Clock Domain Setup Parameters The clock domain settings are: The clock source selection (Analog Clock Source: AMC or INT) • The clock frequency (Clock Value: 200 - 500MHz) • The mode how the clock frequency is determined (Clock Mode: •...
Page 381 Lesson 2 – Analog Clock Domain Setup Unlike the other analog modules, the WGC features an on-board clock NO TE generation. It is independent from the clock of the clock domain (digital clock domain or analog clock domain). This means that the clock frequency for the WGC can be freely chosen within the range of 200MHz - 500MHz.
Page 382: Analog Clock Domain Setup Procedure
Lesson 2 – Analog Clock Domain Setup Analog Clock Domain Setup Procedure To explain all setup parameters and options in the analog clock domain, an example setup for two analog modules, the WDA and the WGB, will be used here. Here is a summary of the setup steps.
Page 383 Lesson 2 – Analog Clock Domain Setup Analog Clock Domain Setup Steps and Example (2) The setup steps in detail: Select the Analog Set Like the hardware settings, all clock domain settings for analog modules to be used in one test must be made in the same set.
Page 384 Lesson 2 – Analog Clock Domain Setup Select the Analog Clock Source To choose the internal clock boards of the analog card cages, select INT. To choose the Alternate Master Clock as the clock source for the analog clock domain, select AMC. The selected source provides the clock signal to all analog modules in the analog domain.
Page 385 Lesson 2 – Analog Clock Domain Setup of the analog module’s frequency divider and Fs range. Analog Module Nmin - Nmax * 98 – 62500 40 - 4000 5 - 500 1 – 500 (4 – 500 for sampler mode) 200 - 62500 20 - 5000 196 - 62500...
Page 386 Lesson 2 – Analog Clock Domain Setup if the clock value was changed, a re-calculation for Fs and N of other modules in the analog domain may be done, following the specific rule that was selected for each module. When doing the re-calculations, the SW will always find the best compromise to approximate Fs to the desired Fs value for all modules.
Page 387: Analog Module Setup Interdependencies
Lesson 2 – Analog Clock Domain Setup Analog Module Setup Interdependencies As explained at the beginning of this lesson, there are parameters in the analog clock domain setup that affect all modules in the domain, and other parameters that are specific to one module. Sometimes, a change of a module specific parameter can also cause a change of a parameter that affects all modules.
Page 388 Lesson 2 – Analog Clock Domain Setup Example 1a: The desired Fs Values can be generated precisely The next figure shows an example, where the desired Fs for the WGB gets approximated.
Page 389 Lesson 2 – Analog Clock Domain Setup Example 1b: The Fs Value of the WGB gets approximated The general algorithm for the calculation is to first accept the direct changes of parameters that affect all modules in the domain. Then, to find a combination of Clock Value and N values that fulfills all modules’...
Page 390 Lesson 2 – Analog Clock Domain Setup Example 1c: The Fs Value of the WGB is forced to be generated precisely You can see that now the Fs of the WDA gets approximated. If you had chosen the Fixed Fs rule also for the WDA, this would have NOTE caused a setup conflict which the software cannot resolve.
Page 391 Lesson 2 – Analog Clock Domain Setup Example 2: Changing the Clock Mode Before the software accepts the change of the Clock Mode parameter a confirmation is required. Confirmation Message for Changes of Clock Domain Parameters As you can see in the example above, the clock mode gets changed to Fixed for all modules, and the Clock Value is set to 350 MHz as specified in the WGA setup.
Page 392 Lesson 2 – Analog Clock Domain Setup analog domain. The different characteristics of the clock sources, however, can influence the measurement results of the modules.
Page 393: Summary And Discussion
Lesson 2 – Analog Clock Domain Setup Summary and Discussion In this lesson you have learned how to use the Clock Domain Setup page of the Analog Setup Tool to set up analog modules in the analog clock domain. You know the setup parameters and the setup procedure, and understand which interdependencies of the setup parameters need to be considered.
Page 394 Lesson 2 – Analog Clock Domain Setup...
Page 395: Using Test Methods
Using Test Methods Unit 6...
Page 396 Unit 6 – Using Test Methods In this Unit ... Overview This unit explains how to create an individual test method and how to use the test method application programming interface. The general concept of test methods is explained in Unit 1, Lesson...
Page 397: Test Method Structure
Lesson 1 Test Method Structure...
Page 398 After this lesson you will be able to interpret the contents of a test method file and you will know how the test method works. Related documents More details can be found in the manual • Agilent 93000 SOC Series “Test Method Programming Reference”.
Page 399: Test Method Overview
Lesson 1 – Test Method Structure Test Method Overview As explained in Units 3 and 4, the 93000 system provides standard mixed-signal tests for DAC and ADC as the testfunctions. These can be executed by using the Test Flow Editor. In addition, to perform tests that are not provided, the test programs can be created as test method programs by using the the C++ language and customized functions.
Page 400 Lesson 1 – Test Method Structure Primary Sets Test Method Parameter Dialog (User Interface) Auto-Download Input Parameters Pass/Fail Limit Values Result Program Test Method HRESULT Cclass::THD_Test(..) Change EXECUTE_TEST(0.01 sec, &timeout_flag); Trigger Hardware rawWave=Analog.DGT("Aout").getWaveform(); Upload DSP_THD(rawWave,result,..); TEST("Aout","THD",result.thd); Test Method-Based Test Suite When the test method is specified for the test suite, the primary sets are used as the test conditions.
Page 401 Lesson 1 – Test Method Structure Almost all test method APIs are grouped depending on what is to be done: setting hardware, testing, reading measurement results, digital signal processing, or judgement of the result. Test Method Program Flow Changing the existing setup data and enabling the trigger line of •...
Page 402 Lesson 1 – Test Method Structure The following shows an example of test method program that uses these test method APIs:...
Page 403: Data Types
Lesson 1 – Test Method Structure Data Types The programming language is a superset of the C++ language. Therefore, the normal data types of the C++ language can be used to declare variables and arrays. In addition, to handle the measurement data and calculation data easily in a test method program, some customized data types are provided, which can be also used to declare input parameters for a test method program.
Page 404 Lesson 1 – Test Method Structure To process measurement data by using Computation APIs, the N O TE number of data items to be processed is needed. For the ARRAY_x array variable, use size() to find the present data size of the array: INT n_of_data;...
Page 405: Input/Output Data Of Test Method Program
Lesson 1 – Test Method Structure Input/Output Data of Test Method Program The test method program (one function for a test suite) can handle two kinds of input data and two kinds of output data between the test method program and the outside of it: Input Data: Input parameter of a test method program •...
Page 406 Lesson 1 – Test Method Structure parameter. You can handle the return values of the output parameter as a global value on the test flow using the build-in function of the Test Flow Editor in the same way as a testfunction.
Page 407 Lesson 1 – Test Method Structure Test judgement result (pass or fail) • The system can carries the pass/fail judgement from the test method program to the test flow by using the TEST API. At this time, the TEST API compares the specified test result with the limit values using the identifier (test name) if necessary.
Page 408 Lesson 1 – Test Method Structure // add your codes return S_OK; In the above example, you can find the defined variable (pin) as the input parameter of THD_test and the system-defined variable (_result[4]) as the output parameter. From the testsuite dialog of the Test Flow Editor, you can open the Parameter dialog for entering values of input parameters and limit range.
Page 409: Programming Style Of Test Method Api
Lesson 1 – Test Method Structure Programming Style of Test Method There are two styles in the test method APIs. One is C function style, and another is C++ class style. The difference between the two is a style of writing as follows: C Function Style This style test method API is provided as C function so that the function has the programming style similar to a generic C...
Page 410 Lesson 1 – Test Method Structure Depending on data that you want to access, the syntax of this type is a little difference as follows: For data related to digital and DPS settings, the data container specifier is one keyword such as follows: Primary.level(3);...
Page 411 Lesson 1 – Test Method Structure For data related to analog module and routing settings, the data container specifier is two keywords such as follows: Analog.AWG("Ain").vOffset(0.5 V); Routing.pin("Ain").connect(TM:SINGLE); The following show the behavior of these statements. Specifier: points to a sub-container of setting data for the specified module in a data container of primary analog set for a test suite.
Page 412 Lesson 1 – Test Method Structure where, : points to data to be accessed DataCategory Analog:Primary analog set (Currently-used analog module conditions) ANALOG(i):Existing analog set specified by a number (i) Routing:For routing set or single routing setting : points to analog module or routing hardware Module AWG:AWG (for Analog or ANALOG(i)) DGT:Digitizer or Sampler (for Analog or ANALOG(i))
Page 413 Lesson 1 – Test Method Structure raw_data = Analog.DGT(“Vout”).getWaveform( );...
Page 414: Test Method Apis
Lesson 1 – Test Method Structure Test Method APIs Setup API When a test flow is executed, all setup files specified in the Setup dialog window of the Test Flow Editor are downloaded to the tester hardware automatically. Then, when the test flow execution reaches the test suite, the primary sets will be set and the test method is executed line by line.
Page 415 Lesson 1 – Test Method Structure to apply the changes. In addition, FLUSH can be used to apply the changes without executing the digital sequence program before the Execution API. For the primary waveform set, timing set, level set, DPS set, or vector label, only the set number or label can be changed to another set number or label.
Page 416 Lesson 1 – Test Method Structure For the primary analog set, you can change the set number or parameter(s) of the primary analog set. The Setup APIs have the following style: •To change the primary analog set number to another number: Analog.primary( INT no ) •To change conditions of the specified module in the primary analog set: Analog.MDL(STRING pin).
Page 417 Lesson 1 – Test Method Structure For the routing set, you can set a routing set as the primary, change the routing set, or switch the connection of a specified pin directly. •To set a routing set as the primary or change the primary routing set to another: Routing.primary( INT no ) •To connect or disconnect a specified pin to the analog module core or other: Routing.pin( STRING pin_name ).
Page 418 Lesson 1 – Test Method Structure By default, trigger lines in the analog modules are disabled in order to prevent these modules from starting operation owing to unintended input such as noise. Therefore, the following APIs must be used to enable the trigger lines before Execution APIs and to disable the trigger lines after the Execution APIs: •To enable the trigger line of a specified analog module : Analog.MDL(STRING pin) .enable( )
Page 419 Lesson 1 – Test Method Structure Execution API After the trigger lines are enabled, to run the test with the present primary sets including the changes by Setup APIs, use the following APIs: EXECUTE_TEST(timeout, &flag); START_TEST(); WAIT_TEST_DONE(timeout, &flag); DIGITAL_CAPTURE_TEST(); The changes by Setup APIs are reflected to the tester hardware by an Execution API.
Page 420 Lesson 1 – Test Method Structure The timeout time is compared to the elapsed time from when the measurement was started. If the measurement time exceeds the timeout time you set, the measurement stops (that is, digital and analog sequence program executions are terminated), and the program execution goes to the next statement in the test method program.
Page 421 Lesson 1 – Test Method Structure The pin parameter is used to specify which module to access. The meas_no corresponds to the downloaded sequence program of the digitizer or sampler. The meas_no “1” specifies the sequence statement in which the start label was defined. By default, the meas_no is set to 1.
Page 422 Lesson 1 – Test Method Structure To retrieve measurement data that was measured under the present primary analog set condition, you can use the following API: result_data = Analog.TIA(pin, coreNum).getXXX(); result_data = TIA(pin, coreNum).getXXX(); coreNum parameter is used only if one front-end module is occupied by two TIAs.
Page 423 Lesson 1 – Test Method Structure Special operations like A-law and u-law encoding/decoding for • CODEC devices. To compute the test result from the raw measurement data, you can use the Computation APIs. Judgement API To make a judgement (pass or fail) on a test, use the following API: TEST (pin, testname, result_value, continue_if_fails);...
Page 424 Lesson 1 – Test Method Structure TEST(“aout”, “THD”, dTHD, TRUE); The GET_TESTFLOW_FLAG API can be used to get the current setting of a specified test flow flag. By using this API in a test method program and setting the related test flow flag, you can switch the option: INT iGlobalOverOn;...
Page 425: Test Method Program For Dc Tests
Lesson 1 – Test Method Structure Test Method Program for DC Tests You can also create a test method program of DC test with the following DC resources: Pin PMU: identifier is PPMU • High Precision (System) PMU: identifier is SPMU •...
Page 426 Lesson 1 – Test Method Structure DC Test with PPMU You can program a DC test with PPMU in the following steps: Defines Measurement Settings: • Force mode (VFIM, IFVM) PPMU_SETTING • Force value • Lower and upper limit for pass/fail judgement Setting up PPMU_RELAY Defines Relay Connection:...
Page 427 Lesson 1 – Test Method Structure Defining Relay Connection: • relay1 is an object name to which relay settings of the PPMU(s) will be set, status is a member function to specify the status of relays per pin (use the specifier, PPMU_ON to connect PPMU relays and ALL_OFF to disconnect all the relays of the PMUs), wait is a member function to specify a wait time after the relays are opened or closed.
Page 428 Lesson 1 – Test Method Structure defined. getValue(“pin1”) is a member function of the PPMU_MEASURE class to retrieve a measurement result, pin1 is a pin name that is used for the DC measurement, testname1 is a test name of the method program. For retrieving global and per pin pass/fail result, you can use the getPassFail member functions instead of getValue.
Page 429 Lesson 1 – Test Method Structure The following example shows how to specify PMU type for the PMU_IFVM API. •For pin1 and pin_group2 connected to the Pin PMUs: PMU_IFVM("pin1, pin_group2"); PMU_IFVM("pin1, pin_group2", TM::PPMU); •For pin1 connected to the High Precision PMU: PMU_IFVM("pin1", TM::SPMU);...
Page 430 Lesson 1 – Test Method Structure This is available for I-force/V-measure testing (continuity test). The following shows the relays on pin electronics. Pogo Pin SPMU ISOL Relay Relay System PMU Pogo Pin DC Relay Electronics Pin PMU Relay Relay Driver Pin PMU Receiver Active Load...
Page 431: Lesson 2
Lesson 2 Creating a Test Method...
Page 432: Creating A Test Method
After this lesson you will be able to create, set up, execute and debug a test method program. You will also know how the test method works. Related documents More details can be found in the manual Agilent 93000 SOC Series “Test Method Programming Reference”. •...
Page 433: Overview
Lesson 2 – Creating a Test Method Overview To execute one or more testmethod-based test suites on the Test Flow editor, a shared library, which is an executable library, must be built for test methods related with the test. To handle files related to test method program such as a shared library and source files on the SmarTest software, the environment called a project is needed.
Page 434 Lesson 2 – Creating a Test Method If the first testmethod-based test suite does not have the CONNECT API, the testfunction must be executed before the first connect testmethod-based test suite in a test flow. In addition, if the testfunction is executed in a test flow and if there is a disconnect testmethod-based test suite later, a test suite that executes the testfunction must be used between the test suites.
Page 435 Lesson 2 – Creating a Test Method 1. Performing preparation tasks for test method programs you will develop. 2. Developing each test method program using the Text Editor tool. 3. Compiling and linking the test method programs for creating a shared library. 4.
Page 436: Preparations To Develop A Test Method Program
Lesson 2 – Creating a Test Method Preparations to Develop a Test Method Program Before you develop a test method program, at least the following preparation tasks are required in the following order: 1. Creating a project directory. 2. Adding a class source file to the project directory. 3.
Page 437 Lesson 2 – Creating a Test Method directory name displayed in the Location field also automatically changes to the specified new project name at same time. b. Click on OK. The Project Window opens. Project Window Adding a Class to the Project To add a class for the test methods you will program to the project, do as follows: Click the first line in the Class List.
Page 438 Lesson 2 – Creating a Test Method Click the first line in the Method List. Enter a new method name as shown in the following figure: Entering a New Method Name Click on Add. The Parameter and Limit Table Dialog window opens.
Page 439 Lesson 2 – Creating a Test Method Parameter and Limit Table Dialog Window Adding a Parameter For each parameter entry, set the following items in the Parameters area. Entry Type • Click on the Type option menu of the first or new parameter entry, then select the data type of the parameter variable.
Page 440 Lesson 2 – Creating a Test Method After completing your entry, click on OK. The Text Editor window opens for programming your method function. See the next section.
Page 441: Using The Text Editor For Editing A Test Method Program
Lesson 2 – Creating a Test Method Using the Text Editor for Editing a Test Method Program The Text Editor window is used to edit a test method program. The Text Editor window can be started from the Project window only.
Page 442 Lesson 2 – Creating a Test Method Using the Test Method Panel You can also use the Test Method Panel to enter the API statements into the Text Editor window. The contents of the Test Method Panel depend on your selected API’s style (C++ class or C function style) as follows: Test Method Panel for a C++ class style API The following describes the parts of above panel.
Page 443 Lesson 2 – Creating a Test Method Test Method Panel for a C function style API The following describes the parts of above panel. Syntax Selection Area: • This area displays the syntax of the function. If the function has some syntax types, this area displays a selection box for selecting a syntax type for the function.
Page 444 Lesson 2 – Creating a Test Method Pop-up Menu for API Selection Set up the details (class, member functions, parameter settings, and so on) from top to bottom in the Test Method Panel, step by step. Click on OK. The API statement is entered in the Text Editor window and the Test Method Panel will close.
Page 445: Compiling And Linking Test Method Programs
Lesson 2 – Creating a Test Method Compiling and Linking Test Method Programs Both the Project window and Text Editor window have compilation and building functions. Compiling a Class Source File To compile a class source file in the Project window, do as follows: Select a class to be compiled from the Class List area in the Project window.
Page 446 Lesson 2 – Creating a Test Method After compilation is done successfully, the object file (class_source.o) is generated under the <project_dir>/ Debug/ directory. Building a Shared Library To generate the executable shared library file that includes all class source files, do one of the following: Click on Build on the bottom of the Project window •...
Page 447: Registering A Test Method Shared Library
Lesson 2 – Creating a Test Method Registering a Test Method Shared Library Before you select a test method program in the Test Flow Editor, the corresponding shared library must be registered to the system. There are the following two types of the registration: DEV Type •...
Page 448: Setting Up Testmethod-Based Test Suite
Lesson 2 – Creating a Test Method Setting Up Testmethod-Based Test Suite You can set up a testmethod-based test suite with the following two steps: Adds test suites Sets parameters for each test suite For details, see the following sub-sections. Adding Testsuites Prior to applying parameters, you have to invoke the Test Flow Editor.
Page 449 Lesson 2 – Creating a Test Method 1. Activate this button. 4. Click Select button. 2. Fill these areas. Set testsuite name, vector label, 3. Place cursor in testmethod entry box. and primary set numbers of various data Testsuite Dialog Then, place the cursor in the test method entry box at the bottom of the testsuite dialog, and click the Select button.
Page 450 Lesson 2 – Creating a Test Method Setting Parameters To set parameters for the specified test method, do as follows. Highlight the desired test method in the test method entry box and click the Edit button. The parameter dialog box opens. Click Edit button Highlight desired Test Method Then, a test method parameter dialog box shown in the following...
Page 451 Lesson 2 – Creating a Test Method In the dialog, you can view or modify the following Parameter Description Class Class name specified in the test method Method Method name specified in the test method Scope Registration mode SYS or DEV Index Parameter index that is automatically assigned Name...
Page 452 Lesson 2 – Creating a Test Method symbol selection feature, the limit symbol must be "N/A", and you should select the check buttons PRIOR TO entering limit values. To close this dialog, double-click on the upper-right corner of the window. After closing the parameter dialog, click the Done button in the testsuite dialog to apply parameters to the existing method.
Page 453: Executing Testmethod-Based Test Suite
Lesson 2 – Creating a Test Method Executing Testmethod-Based Test Suite This section explains how to execute a testmethod-based test suite. Setting Flags Before Execution In the system flags, testflow flags, and testsuite flags, there are flags related to the test method program execution. To invoke the flags window where you can define the system flags, •...
Page 454 Lesson 2 – Creating a Test Method Output on pass/output on fail (testsuite flags) These testsuite flags determine whether the test suite returns an overall pass and/or fail message. These flags must be set if the output needs to be sent to the event datalog subsystem. Use these flags according to your testing purpose.
Page 455 Lesson 2 – Creating a Test Method...
Page 456: Debugging Test Method Programs
Lesson 2 – Creating a Test Method Debugging Test Method Programs SmarTest uses the HP WDB GUI for debugging test method programs. The HP WDB GUI is a graphical user interface (GUI) designed by Hewlett-Packard for the WDB debugger. Starting the WDB For starting to debug testmethod-based test suites, you must do the following procedure in the Test Flow Editor.
Page 457 Lesson 2 – Creating a Test Method Setting a Breakpoint To set a breakpoint at a specified point, do as follows: In the text column of the Source view, place the cursor where you want to insert a breakpoint. Right-click to display the pop-up menu. Click “Insert/Remove Breakpoint”.
Page 458 Lesson 2 – Creating a Test Method Controlling Test Method Program Execution Step Into Run to Cursor Insert/Remove Step Over Breakpoints Debugger Icons Single Stepping Test To single step a test method program, use the Step Into or Step Over button of the WDB. Method Program Step Into •...
Page 459 Lesson 2 – Creating a Test Method To change a value for a specified variable or expression, enter the value into the corresponding cell of the Value column in the Watch view. Viewing Values of the ARRAY_X Array Variable To view values in variables of the system-defined data type like in the WDB GUI, do as follows: ARRAY_I ARRAY_D...
Page 460 Lesson 2 – Creating a Test Method before the test execution, function must be used between FLUSH the Setup APIs and Execute API. Monitoring Changes for Analog Set Using FLUSH If you change the contents of the testsuite dialog in the Test Flow Editor, the changes will be reflected when you re-start the testsuite from the Test Flow Editor after completing the current execution, even before completing the current debug session.
Page 461 Lesson 2 – Creating a Test Method EXECUTE_TEST(1.0 sec); dVdtz=Analog.DGT(“aout”).getWaveform(); PUT_DEBUG(“aout”,“Wave1”,dVdtz); Updating Mixed Signal Tool Displaying Measured Data on Mixed Signal Tool Using PUT_DEBUG Starting Analog While debugging a test method program, you may execute sequence program(s) for AWG, digitizer, and/or sampler multiple times by Sequence Program at re-executing the corresponding Execute APIs.
Page 462 Lesson 2 – Creating a Test Method and save it using the Test Method Editor. Then build a shared library from all source files and register the generated shared library once again. When you build a shared library from the source files after fixing bugs, the HP WDB GUI window will be closed automatically if the debugger window remains open.
Page 463: Debugging Tests Using Hardware Response Emulator
Lesson 2 – Creating a Test Method Debugging Tests using Hardware Response Emulator This section is just an introduction of a powerful debugging tool, the Hardware Response Emulator (Emulator). For details of this tool, see the Test Method Programming Reference manual after this lesson.
Page 464 Lesson 2 – Creating a Test Method Supported APIs The following APIs are supported by the Emulator: • DGT().getWaveform () • TIA.getMean(),.getMean(),.getMin(),.getMax(),.getJitter() • Vector().getVector() • SpecSearch API; .getResultSpec(),.getPassVal(),.getFailVal() • PMU_IFVM(),PMU_VFIM(),DPS_VFIM(),PPMU_MEASURE • FW_TASK(command,answer) • GET_FUNCTIONAL_RESULT() • TEST() (except DC test) Data File for Data to be returned by the Emulator is previously prepared in the file that is called “Hardware (HW) Response File”.
Page 465 Lesson 2 – Creating a Test Method result (pass/fail) or hardware response. You can also use the data files as virtual data in online mode. Testsuite Offline Mode: API for retrieving Judge pass/fail (Test Method Program) hardware response of testsuite Test Execution Not Access Emulator...
Page 466 Lesson 2 – Creating a Test Method...
Page 467: Unit 7
Time Interval Analyzer Unit 7...
Page 468 Unit 7 – Time Interval Analyzer In this Unit ... Overview This Unit describes the Time Interval Analyzer (TIA) and its usage. You will learn about the two-component setup of the TIA (front- end module and TIA instrument), the measurement capabilities of the TIA, how to make all settings for a TIA test, and how to program and execute a test method to perform a TIA test.
Page 469: Lesson 1
Lesson 1 TIA Overview...
Page 470: Tia Overview
Related documents More details about the front-end module and the TIA instruments can be found in the manual Agilent 93000 SOC Series “System Reference”. • Details about the TIA test setup are provided in the manual Agilent 93000 SOC Series “Test Setup”.
Page 471: Front-End Module And Time Interval Analyzer (Tia)
Lesson 1 – TIA Overview Front-End Module and Time Interval Analyzer (TIA) The Time Interval Analyzer implementation of the Agilent 93000 SOC Series comprises the actual TIA instrument in the analog support rack and a front-end module in the testhead. This arrangement and the basic functions of the front-end module and the TIA have already been explained in the lesson “Time Interval Analyzer”...
Page 472 Lesson 1 – TIA Overview The following figure shows the front-end/TIA arrangement. It is repeated from the Unit “Analog Hardware”. Block Diagram of TIA You will find the two component approach, front-end module and TIA instrument, reflected in the setup page of the Analog Setup Tool.
Page 473: Setup And Test Execution Overview
Lesson 1 – TIA Overview Setup and Test Execution Overview The setup for a test using the TIA is done with the same tools that are used to set up the other analog modules, but the setup of the TIA is simpler than that of digitizers/samplers and of arbitrary waveform generators.
Page 474: Tia Setup
Lesson 1 – TIA Overview digitzers and arbitrary waveform generators. Therefore, the mere TIA setup is explained here, and no setups for a device. In the labs, you will perform measurements with the TIA on signals that are directly fed to the TIA inputs by digital pins. The test setup used in the labs will also be used in examples shown in this Unit.
Page 475: Summary And Discussion
Lesson 1 – TIA Overview Summary and Discussion In this lesson you have learned which tasks the front-end module and the TIA instrument perform during a mixed-signal test. You now know what type of measurements you can make with the TIA, and you have a general understanding of the steps that need to be carried out to set up a TIA test and to execute it.
Page 476 Lesson 1 – TIA Overview...
Page 477: Tia Setup
Lesson 2 TIA Setup...
Page 478: Tia Setup
TIA, how it will be performed, and at which pins. Related documents Details about the TIA test setup are provided in the manual Agilent 93000 SOC Series “Test Setup”. •...
Page 479: Overview
Lesson 2 – TIA Setup Overview The following figure summarizes the steps to set up a TIA test, and to execute it. TIA Test Setup and Execution Sequence Trigger Pin Setup The first 4 steps deal with the setup of a normal digital channel to provide an external trigger signal to the TIA.
Page 480: Pin Configuration For The Tia
Lesson 2 – TIA Setup Pin Configuration for the TIA In the Pin Configuration Editor, a pin of the TIA is specified by the channel number and the software identifier TIA followed by the slot number where the front-end module is installed (e.g. TIA225).
Page 481: Front-End And Tia Setup
Lesson 2 – TIA Setup Front-End and TIA Setup The setups for the front-end module and the TIA are made in the Hardware Settings page of the Analog Setup Tool. Unlike the other modules, the TIA only requires Hardware Settings. This means that the Sequencer Memory, the Waveform Memory and the Clock Domain setup pages are not applicable for the TIA.
Page 482 Lesson 2 – TIA Setup To do this, you select the instrument TIAxxx_1 or TIAxxx_2 directly from the drop down list of the B field (xxx is the slot OARD number where the front-end module is installed, typically 225). Selecting the TIA Instrument (Core) You can also select any of the defined TIA pins from the drop down NOTE list of the P...
Page 483 Lesson 2 – TIA Setup Input Pin Output Pin (for loop-back) Pins routed to the TIA core External Triggering Front-End Setup Parameters Front-End Setup Area The settings you make only apply to the input channels of the TIA core displayed in the B field.
Page 484 Lesson 2 – TIA Setup Specifying the Input Termination You can specify a termination voltage when Z = 10kOhm is selected, NOTE but this voltage will be ignored because the 10kOhm termination is always connected to ground. NOTE Naming of the TIA input channels: There are three input channels to each TIA core.
Page 485 Lesson 2 – TIA Setup each input channel (CH1 and CH2). The following figure illustrates this. In the Hardware Settings page you enter the thresholds for the CH1 and CH2 input signals as shown below. Specifying the Threshold Voltage for Signal Conditioning TIA Settings For the TIA, you need to specify which measurements to make, how to make them, and how the triggering for each measurement...
Page 486 Lesson 2 – TIA Setup TIA Setup Area Measurement Settings TIA Measurement Setup Section In the Measurement section, you can specify the type of measurement (Measurement Mode) to be made, and the number of repetitions for the selected measurement (Sample Size). From the results of a repeated measurement, for example, the jitter can be calculated.
Page 487 Lesson 2 – TIA Setup TIA Measurement Options A measurement of the TIA always means that the time between two specific input signal edges gets measured. If both are edges of the same input channel, the measurement is called a single channel measurement;...
Page 488 Lesson 2 – TIA Setup TIA Measurements In addition to the pure time interval measurements, the TIA can perform calculations on the measured values, for example to determine jitter. A calculated result can be retrieved, like a direct time interval measurement result, with a test method. This is described in the next lesson.
Page 489 Lesson 2 – TIA Setup TIA Arming Setup Section There are two ways to provide the arming signal. They differ in the source of the signal. Source = EXTERNAL • In this mode, the TIA is armed when it detects an edge on the external trigger input.
Page 490 Lesson 2 – TIA Setup This is a special mode for propagation delay measurements. In this mode, any edge on channel 2 is ignored that occurs after the arming and before the edge on channel 1 that marks the starting point for the time measurement. This guaranties positive measurement results, if negative results need to be avoided, which may be the case in custom test methods.
Page 491 Lesson 2 – TIA Setup Start Count and Stop Count With the Start Count and Stop Count parameters, you can delay the start and the stop of a measurement. For example, if you have a measurement that is specified to start from a rising edge on channel 1, and you have entered a Start Count of 6, the measurement will not start on the first rising edge on channel 1 after arming.
Page 492 Lesson 2 – TIA Setup Source = EXTERNAL: In this mode the arming trigger must be provided for each measurement. After one measurement is done, the trigger for the next measurement must be set with a distance of 30 µs or later. Source = AUTO •...
Page 493: Defining The Routing
Lesson 2 – TIA Setup Defining the Routing The routing for a TIA test is defined with the Routing Setup Tool. The routing defines how the input pins to the front-end module get connected to the possible two TIAs that are connected to the front- end module.
Page 494 Lesson 2 – TIA Setup TIA Routing Definition...
Page 495: Summary And Discussion
Lesson 2 – TIA Setup Summary and Discussion In this lesson you learned how to make the settings for a TIA test. You now know all the test setup parameters for the front-end module and for the TIA instrument, and understand how these parameters define the test to be performed.
Page 496 Lesson 2 – TIA Setup...
Page 497: Tia Test Method Programming And Test Execution
Lesson 3 TIA Test Method Programming and Test Execution...
Page 498: Tia Test Method Programming And Test Execution
After this lesson you will know how to program a test method for a TIA test that initializes the test, executes it and retrieves the test results. Related documents Detailed information about test method programming is available in the manual Agilent 93000 SOC Series “Test Method Programming Reference”. •...
Page 499: Test Method Flow
Lesson 3 – TIA Test Method Programming and Test Execution Test Method Flow The test execution of TIA tests and the result retrieval have to be done with test methods. SmarTest does not provide standard testfunctions for TIA tests. The concept of test methods, their structure, the various APIs, and how to write, execute and debug a test method have been covered in Unit 6 of this training.
Page 500 Lesson 3 – TIA Test Method Programming and Test Execution Test Method Flow for a TIA Test The above figure also shows the main API calls that are used to build a TIA test. These API calls are described in more detail in the next section.
Page 501: Tia Api Functions
Lesson 3 – TIA Test Method Programming and Test Execution TIA API Functions This lesson describes how to use the basic API commands that build a test method for a TIA Test. Setting the Primary Routing Set Unlike the other primary sets, the primary routing set is not defined in the test suite.
Page 502 Lesson 3 – TIA Test Method Programming and Test Execution Executing the Test To perform the measurement, the test must be executed. The execution starts the digital sequencer (for analog modules other than the TIA also the analog sequencer) and stops when the sequencer(s) stop.
Page 503 Lesson 3 – TIA Test Method Programming and Test Execution With the following API function, you can retrieve the measured data: Getting Measurement Results from the TIA Calculated results can be retrieved with these API functions: Getting Calculated Results from the TIA In the next section, you will see an example test method that demonstrates how to use these functions.
Page 504: Tia Example Test Method
Lesson 3 – TIA Test Method Programming and Test Execution TIA Example Test Method You will now see an example of a test method for a TIA test. The test method contains all the basic elements and uses the API function that have been discussed in the previous sections.
Page 505 Lesson 3 – TIA Test Method Programming and Test Execution The routing for the test is defined in routing set 1. Routing for Example Test Method Test method code: TIA Example Test Method (1)
Page 506 Lesson 3 – TIA Test Method Programming and Test Execution TIA Example Test Method (2)
Page 507: Summary And Discussion
Lesson 3 – TIA Test Method Programming and Test Execution Summary and Discussion In this lesson you learned know how to program a test method for a TIA test that initializes the test, executes it and retrieves the test results.
Page 508 Lesson 3 – TIA Test Method Programming and Test Execution...
Page 509 Advanced Procedures Unit 8...
Page 510 Unit 8 – Advanced Procedures In this Unit ... Overview This unit contains various topics, beyond the standard tools and procedures for mixed-signal testing. The topics covered in this unit may not be relevant for each training class. They can be discussed in class, or can be omitted, according to the individual needs of the students.
Page 511: Multi-Site Test
Lesson 1 Multi-Site Test...
Page 512: Multi-Site Test
After this lesson you will know how to set up test methods than run multi- site tests, and understand the basic differences between single-site and multi-site test programs. Related documents More details can be found in the manual Agilent 93000 SOC Series “Multi-Site Testing”. •...
Page 513: Overview
Lesson 1 – Multi-Site Test Overview For a test method-based test suite, if you set up the Parallel Mode Enable testflow flag and Allow Parallel testsuite flag, the test suite can be executed for multiple sites. However, if a test method program is developed as single-site test, the test method program is invoked site by site (serial testing).
Page 514 Lesson 1 – Multi-Site Test Test Method Programs for Parallel Execution The following summarizes each operation in the execution flow: The first invocation of the test method program (the invocation for the first • site) is used to make all necessary setups and tests (measurements) in parallel for all sites.
Page 515: Defining Pin Configuration
Lesson 1 – Multi-Site Test Defining Pin Configuration By using the Pin Configuration, you must define pin configurations for all sites to be tested. To define the pin configurations for multi-site testing, do as follows: In the Pin Configuration, choose define multi site from the Select pull-down menu.
Page 516: Setting Up Flags For Multi-Site Testing
Lesson 1 – Multi-Site Test Setting Up Flags for Multi-Site Testing For a test method-based test suite, if you set up the Parallel Mode Enable testflow flag and Allow Parallel testsuite flag, the test suite can be executed for multiple sites. To set up the Parallel Mode Enable testflow flag, select the Testflow Flags •...
Page 517: Test Method Program For Multi-Site Testing
Lesson 1 – Multi-Site Test Test Method Program for Multi-Site Testing Setting Up a Block for Parallel Execution For parallel execution of setup and test (measurement) for all sites at the first invocation of the program, enclose the setup and test execution part of a test method program by the following two Multi-site APIs: ON_FIRST_INVOCATION_BEGIN();...
Page 518 Lesson 1 – Multi-Site Test The APIs to be added for multi-site testing are ignored in single-site testing. N O TE Consequently, you can develop test method programs that are compatible with both single-site and multi-site tests. The Multi-site APIs make it possible to upgrade from single-site testing to multi-site testing if the need arises.
Page 519 Lesson 1 – Multi-Site Test •There are setup-focus state to perform the site-specific setup, and query-focus state to perform the site-specific retrieve. •There are two approaches for site-specified Setup as follows: •Controlling the Setup/Query-focus state of Site Automatically •Controlling the Setup-focus state of Sites Manually...
Page 520 Lesson 1 – Multi-Site Test Controlling the Setup/ To execute a specified set up block within parallel execution block serially, Query-Focus State of enclose the Setup APIs within the first invocation block by the following two Site Automatically Multi-site APIs: ON_FIRST_INVOCATION_BEGIN ;...
Page 521 Lesson 1 – Multi-Site Test Controlling the Setup/ In addition to auto-controlling the setup/query-focus state of sites, you can Query-Focus State of also control the state of setup-focus in the currently-active sites by using the Site Manually following APIs. The first two APIs specify which sites are addressed by Setup APIs which follow, for performing the site-specific setup.
Page 522 Lesson 1 – Multi-Site Test The CURRENT_SITE_NUMBER API is designed for executing on a single active site. Hence, use this API in the each site loop block or outside the first invocation block, as follows: DOUBLE voff[2]; voff[0] = 0.25 V;// DC offset for site#1 voff[1] = 0.28 V;// DC offset for site#2 ON_FIRST_INVOCATION_BEGIN();...
Page 523 Lesson 1 – Multi-Site Test Measurement Data Management The result APIs store the results of all sites into the cache for quick access in later invocations of the program. The result data in the cache is identified by site number, used memory area in resource, kind of resource, order of measurement (n-th measurement), and so on.
Page 524 Lesson 1 – Multi-Site Test Judging Test Result for Multi-Site Testing By default, the program execution will be terminated if the TEST API failed. However, to continue executing the program for the second and later sites, the TEST API does not terminate the program execution if a site to be judged remains later.
Page 525 Lesson 1 – Multi-Site Test GET_USER_DOUBLE() • GET_USER_STRING() • SET_SYSTEM_FLAG() • SET_TESTFLOW_FLAG() • SET_TESTSUITE_FLAG() • SET_USER_FLAG() • SET_USER_DOUBLE() • SET_USER_STRING() • Regardless of single-site or multi-site testing, it is NOT recommended to set N OT E the system, testflow, and testsuite flags in the test method program. Even if you set them by using APIs, any flag state will be valid when the next testsuite is executed.
Page 526 Lesson 1 – Multi-Site Test...
Page 527: Dut Board Design Considerations
Lesson 2 DUT Board Design Considerations...
Page 528: Dut Board Design Considerations
Lesson 2 – DUT Board Design Considerations In this Lesson ... Overview This lesson explains the criteria that a DUT board for mixed-signal devices must fulfill. Even if you do not design the DUT board yourself, you may need to communicate the information to the designer and to judge the result.
Page 529: Dut Board Overview
Lesson 2 – DUT Board Design Considerations DUT Board Overview If a packaged device is tested, an IC socket is mounted on the DUT board to connect the device to the test system hardware. The IC socket can be directly mounted on the DUT board. For pro- duction tests, the socket adapter is generally used between the IC socket and DUT board so that the IC socket can be replaced easily if it breaks.
Page 530 Lesson 2 – DUT Board Design Considerations AWGs, digitizers, samplers, digital pin electronics or SCAN boards located in the testhead slots. For each pogo block, there are 17 pogo signals surrounded by the pogo ground (GND). Signal Pin Ground Pins Orientation Marker Pogo Pin Contacts...
Page 531: Dut Board Design Consideration
Lesson 2 – DUT Board Design Considerations DUT Board Design Consideration Analog signals can be easily disrupted by pulses (for example clocks and digital signals). To avoid this problem, both signal types must be physically separated. Therefore, designing a DUT board for a mixed-signal device requires more effort than designing a DUT board for a purely digital device.
Page 532 Lesson 2 – DUT Board Design Considerations or picking up noise. Matching the source impedance will provide maximum signal power and least distortion. Use separate power supply cards for supplying the digital and analog • circuits of the DUT, if possible. Remove spikes that can be induced via the power supply.
Page 533: Grounding And Signal Shielding
Lesson 2 – DUT Board Design Considerations Grounding and Signal Shielding Proper grounding is essential for precise measurements. Mixed-signal devices differentiate between digital and analog ground and often also between digital and analog supply voltage. You will need two ground planes on the DUT board which are connected somewhere via an inductor as shown in the following figure: Analog Ground (Ground Plane)
Page 534 Lesson 2 – DUT Board Design Considerations on the digital ground. Then connect the ground lines to the digital ground plane near as to the device as possible. signal Analog Ground Plane Analog ground Connect ground planes Module AGND close to the DUT 50 ohm coaxial cable signal...
Page 535 Lesson 2 – DUT Board Design Considerations Also, changes of the supply voltage will influence the generated or received signal and thus increase the noise level. Use lowpass filters or at least bypass capacitors to reduce noise. A lowpass filter can be directly inserted into the supply lines. •...
Page 536: Printed Circuit Board
Lesson 2 – DUT Board Design Considerations Printed Circuit Board To run the same application on multiple testers for production tests, the DUT board is developed as a printed circuit board (PCB). As the operation rate of a mixed-signal device increases, application engineers who develop test circuits need to be skilled not only in schematic design but also in printed circuit board design.
Page 537 Lesson 2 – DUT Board Design Considerations Ground Plane Strip Line Ground Plane Characteristic Impedance: Zo = π ( 0.8*w + t ) 0.67 Strip Line Model As shown in the above figures, the microstrip line and strip line consist of a set N OT E of a trace and ground or power plane(s).
Page 538 Lesson 2 – DUT Board Design Considerations Stubs Branch (Stub) In the above example, if the signal frequency is very high, these stubs cause signal reflections at the points. Consequently, the trace should be drawn without a stub. Crosstalk If two signal lines are traced in parallel on a PC board and if one carries a small and precise signal and the other carries a high level signal, the large signal may couple to the sensitive line and cause trouble (level change and jitter).
Page 539: Troubleshooting Noise Problems
Lesson 2 – DUT Board Design Considerations Troubleshooting Noise Problems During test circuit development, you may encounter one or several of the following problems: A correctly specified filter does not cut the signal as required. • A relay does not disconnect a signal completely. •...
Page 540: Summary And Discussion
Lesson 2 – DUT Board Design Considerations Summary and Discussion Let us summarize what you have learned: For easy replacement, active devices on the DUT board, such as opamps or • relays, should be mounted on sockets. Input and output signals as well as analog and digital signals should be •...
Page 541: Special Synchronization Options
Lesson 3 Special Synchronization Options...
Page 542: Special Synchronization Options
Lesson 3 – Special Synchronization Options In this Lesson ... Overview For the High Speed AWG (WGB), 500M AWG (WGD), 100MHz Digitizer (WDG), 1GHz Digitizer (WDD), Dual High Speed Sampler (SPA), and 3GHz Sampler (SPB), there is a special synchronization function to synchronize modules of the same type.
Page 543: Master/Slave Trigger Function
Lesson 3 – Special Synchronization Options Master/Slave Trigger Function When performing tests that require to use multiple high speed analog modules simultaneously, it is important to remove uncertainty between the analog modules as much as possible. When you use different master clock sources for digital channels and analog modules, uncertainty occurs not only between the digital channel as the trigger source and the related analog module, but also between analog modules.
Page 544 Lesson 3 – Special Synchronization Options You can define any module in the loop of the “Master-Slave” internal connection as master or slave. To define the slave module, use the ACMD “SYNM” firmware command. If you define a module as a slave module, the upstream module in the internal connection loop is defined as a master module automatically.
Page 545 Appendix...
Page 546 Overview This Appendix contains A brief refresher of Mixed-Signal Test Fundamentals. • Definitions of the typical characteristics DACs and ADCs are • tested for The technical specifications of the DAC and ADC used for the • training.
Page 547 Appendix A Basics of Mixed-Signal Testing...
Page 548 Appendix A Some Notes on Digital Signal Processing The samples captured from the DUT are stored as contiguous blocks of sampled points, also called vectors. Sampling and digitizing of analog data brings us from the continuous to the discrete signals domain. Continuous Signals Domain vs.
Page 549 Appendix A Principle of Digital Integration From the picture above, some general characteristics of digital signal processing become obvious: • The mean value determined by the digital system will only be correct, if the samples used for the computation cover exactly one or several whole signal periods.
Page 550 Appendix A Emulation of Analog Instruments The computer emulates the functions of analog instruments by mathematical algorithms. For example: Low-pass filters are emulated by integration. • • High-pass filters are emulated by differentiation. Spectral (band-pass) filters are emulated by Fourier •...
Page 551 Appendix A Sampling and Averaging Sampled signals differ from analog signals. An example may be helpful to understand what happens when we sample a signal. Let us consider a speech signal that has been filtered by a bandpass with a lower frequency of 300 Hz and an upper frequency of 3400 Hz.
Page 552 Appendix A The computer has no idea which spectral region represents the NOT E original signal. The signal processing routines simply use the primitive values, that means the components in the Nyquist band. So, if you are sampling a band-limited signal at bandpass conditions, that means with a rate that is lower than twice the highest frequency contained in that signal, you need to consider that the DSP processes and reports the frequency components in...
Page 553 Appendix A Example: If we use a sampling frequency F of 120 kHz and the signal contains a 100 kHz component, this component will appear as a 20 kHz frequency. Undersampling Example in Frequency Domain Aliasing is not always bad. It is frequently used in radio tuners and communication products and is also called heterodyning.
Page 554 Appendix A Averaging by point Point repetition is most useful for linearity tests. repetition If point repetition is enabled, each analog or digital value is sent several times to the DUT. The computer automatically sums up the results p(i) and divides the sum by the specified number of repetitions n: ∑...
Page 555 Appendix A Example: Averaging by Waveform Repetition Oversampling Oversampling is a method to increase the measurement accuracy. This method is also based on averaging. Assume you need to measure the signal-to-noise ratio of an 18-bit audio DAC that is operated at a conversion rate of 48 kHz. However, your waveform digitizer has only a resolution of 16 bits.
Page 556 Appendix A By means of oversampling, an 18-bit resolution can be achieved even with a 16-bit digitizer. Oversampling Method Coherent Sampling We have already mentioned that digital signal processing requires some kind of synchronization between the signal frequency and the sampling frequency in order to obtain accurate and reproducible results.
Page 557 Appendix A The Unit Test Period (UTP) UTP = Unit Test Period For a periodic signal, the UTP is a time interval over which unique information is spread. Example: Let us take 10 equally spaced samples of a signal which comprises two cycles.
Page 558 Appendix A However, all the samples contained in one UTP describe just one • signal cycle. You should at least Capturing one UTP is the minimal requirement for dynamic • capture one UTP. mixed-signal tests. One UTP is the shortest valid test window. Redundant sampling •...
Page 559 Appendix A The Effective Sampling Rate In coherent under-sampling, the effective spacing is the spacing obtained by shuffling the samples so as to get one single, primitive, cycle of the waveform. The effective or primitive spacing is T = 1 / (F * M).
Page 560 Appendix A Time Domain vs. Frequency Domain The traditional way of observing signals is to view them in time domain. The time domain shows a record of what happened to a parameter versus time. This view is similar to the paper strip produced by a strip chart recorder.
Page 561 Appendix A So, the spectrum of a signal (the view of amplitude over frequency) is just another way of looking at the signal. This is illustrated in the figure below. Three-Dimensional View of a Signal Moreover, periodic signals have a discrete spectrum (that is, frequency components only occur at discrete values), whereas non- periodic (arbitrary) signals have a continuous spectrum If we view our signal over the time axis, we see the sum of all the...
Page 562 Appendix A Characteristics of the Frequency Domain In frequency domain, we can see the purity of a signal. Harmonics Appear in the Spectrum Signals that seem perfect in time domain, may show major distortions (additional components) in frequency domain. Purpose of Frequency Domain Measurements In general, we use the frequency domain to measure the ‘purity’...
Page 563 Appendix A Measurements in Frequency Domain The distortion caused by a device, for example, is determined by applying a spectrally pure input signal to that device and measuring the spectrum of the output signal. By separating the output frequencies, we can distinguish between harmonic and disharmonic distortions and determine their impact on the whole output signal.
Page 564 Appendix A The result is a tremendous increase in processing speed compared to DFT: FFT vs. DFT This advantage is the reason why FFT is preferred. Neither DFT nor FFT convert a single data point into a single frequency line. Every Fourier transformation requires a complete set of samples.
Page 565 Appendix A Leakage appears in a The FFT algorithm calculates frequency components which “leak” into the pure spectrum. This is illustrated in the following picture. FFT spectrum, if the assumed waveform differs from the original waveform. Correct and Incorrect Time Record Leakage makes it impossible to detect minor signal components.
Page 566 Appendix A...
Page 567 Appendix B Definition of DAC and ADC Characteristics...
Page 568 Appendix B This appendix summarizes definitions of the typical characteristics DACs and ADCs are tested for. DAC Linearity Characteristics DAC linearity is measured by applying a digital ramp signal which covers the full code range. DAC linearity measurements include: • Differential Non-Linearity (DNL) •...
Page 569 Appendix B maximum of these values against a given limit to determine the pass/fail result. Differential Non-Linearity can be calculated using the end point method, zero- point method, or minimum root mean square method. All three methods use the same formula. Only the definition of the DeviceLSB varies from method to method.
Page 570 Appendix B The following formulas are used: End point method: = # of sampled points Zero-point method: Minimum RMS method: Calculation of DAC DeviceLSB The end point method assumes a straight line between the first and last measured value. The other two methods consider all the measured values and derive the DeviceLSB from two sorts of linear regression calculations.
Page 571 Appendix B Discrete Analog Output Voltage Digital Input code Definition of DAC INL The INL calculation returns 2 values, where n is the resolution of the DAC (the number of bits). A DAC INL test checks the maximum of these values against a given limit to determine the pass/fail result.
Page 572 Appendix B End point method: Zero-point method: Minimum RMS method: Calculation of DAC V DAC Offset Error The offset error is calculated from the output voltage at code zero. The offset error is also called linear displacement. The end point method is used to calculate the DeviceLSB. V(0) Offset Error = DeviceLSB...
Page 573 Appendix B You can choose between several measurement units. The software provides two calculation alternatives: • Nominal calculation Device-dependent calculation • The nominal calculation refers to an ideal DAC, the device- dependent calculation takes the measured offset into account. Discrete Analog Output Voltage V(2 -1) V(0)
Page 574 Appendix B Nominal and Device-Dependent Calculation of DAC Full Scale Gain Error DAC LSB Gain Error The LSB gain error is a measure of the error between the LSB of an ideal DAC (LSB ) and the actual DeviceLSB. There are several ways to calculate the LSB gain error, for example, in % of LSB , or in % of DeviceLSB DAC LSB Gain Error in % of LSB...
Page 575 Appendix B Nominal and Device-Dependent Calculation of DAC LSB Gain Error DAC Gain Mismatch Gain mismatch measures the difference in full scale output values ) between two DACs. It is expressed in %. Gain mismatch is the difference in full scale output values (V ) from one DAC to the next, expressed in %.
Page 576 Appendix B ADC Linearity Characteristics The parameters that describe the linearity of an ADC have the same names as those used for describing the linearity of a DAC. But they are calculated differently. • Differential Non-Linearity (DNL) • Integral Non-Linearity (INL) •...
Page 577 Appendix B ADC Integral Non Linearity, INL ADC INL measures the deviation of each code center point from an ideal straight line. ADC Integral Non-Linearity, INL ADC Offset Error ADC offset error measures the analog input voltage range that leads to output code zero. Binary Output Code Ideal code center line Actual code center line...
Page 578 Appendix B ADC Gain Error ADC gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. ADC Gain Error To calculate FS gain error and LSB gain error, the following formulas are used: Calculation of ADC Gain Error...
Page 579 Appendix B Distortion Characteristics Distortion is usually measured by sourcing a sine wave. The analog response is first captured and then analyzed in the frequency domain. This means, the processed waveform is converted into its spectrum using the FFT algorithm, and the calculations are based on the frequency components.
Page 580 Appendix B Signal-to-Noise Ratio Signal-to-noise ratio (SNR) is calculated as the ratio of the rms value of the input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and Calculation of SNR Signal-to-Noise plus Distortion The SND compares the power of the input signal with the combined power of the harmonics and noise.
Page 581 Appendix B Spurious Free Dynamic Range Spurious free dynamic range (SFDR) is the ratio of the largest spectral component excluding DC to the rms value of the full-scale input signal. Calculation of SFDR Signal Resolution Signal resolution is the root of the fundamental output signal component divided by the squared half number of harmonics.
Page 582 Appendix B A major factor is the ADC’s inherent uncertainty. Even an ideal ADC produces a quantization error which can be seen as a sawtooth function. Ideal ADC Binary Output Code Analog Input Quantization Error +1/2 LSB Analog Input –1/2 LSB ADC Quantization Error But other factors also reduce the available resolution: Calculation of N...
Page 583 Appendix B Dynamic Range The dynamic range of a DAC or an ADC is determined by the number of bits. DAC/ADC Dynamic Range...
Page 584 Appendix B...
Page 585 Appendix C DAC Training Device Specifications...
Page 586 Appendix C The DUT board used for the training contains a DAC and an ADC. The following pages are a copy of the data sheet of the high speed 8-bit D/A converter THS5641A.
Page 587 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 SOIC (DW) OR TSSOP (PW) PACKAGE Member of the Pin-Compatible (TOP VIEW) CommsDAC Product Family 100 MSPS Update Rate 8-Bit Resolution DGND Signal-to-Noise and Distortion Ratio MODE (SINAD) at 5 MHz: 50 dB Integral Nonlinearity INL: 0.25 LSB...
Page 588 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 description (continued) The THS5641A provides a nominal full-scale differential output current of 20 mA and >300 kΩ output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required.
Page 589 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 Terminal Functions TERMINAL DESCRIPTION NAME AGND Analog ground return for the internal analog circuitry AV DD Positive analog supply voltage (3 V to 5.5 V) BIASJ Full-scale output current bias External clock input.
Page 590 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AV = 5 V, = 5 V, IOUT = 20 mA (unless otherwise noted) dc specifications PARAMETER TEST CONDITIONS UNIT...
Page 591 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AV = 5 V, = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load (unless = 5 V, IOUT otherwise noted) ac specifications...
Page 592 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AV = 5 V, = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load (unless = 5 V, IOUT otherwise noted) (continued) ac specifications...
Page 593 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 † TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION OUTPUT FREQUENCY OUTPUT FREQUENCY –42 Fclock = 5 MSPS 100 MSPS 70 MSPS AV DD = 5 V –48 DV DD = 5 V Fclock = 25 MSPS...
Page 594 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 † TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION RATIO OUTPUT FREQUENCY OUTPUT FREQUENCY –48 AV DD = 3.3 V 67 MSPS DV DD = 3.3 V –54 25 MSPS 5 MSPS...
Page 595 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 † TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE AND DISTORTION RATIO FULL-SCALE OUTPUT CURRENT AT 100 MSPS FULL-SCALE OUTPUT CURRENT AT 100 MSPS Fout = 2.5 MHz Fout = 2.5 MHz Fout = 10 MHz Fout = 10 MHz...
Page 596 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 † TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE AND DISTORTION RATIO OUTPUT FREQUENCY OUTPUT FREQUENCY AV DD = 3.3 V AV DD = 3.3 V DIFFERENTIAL OUTPUT DV DD = 3.3 V DV DD = 3.3 V...
Page 597 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 † TYPICAL CHARACTERISTICS OUTPUT SPECTRUM FOR Fout = 10 MHz AND Fclock = 100 MSPS –10 AV DD = 5 V –20 DV DD = 5 V –30 –40 –50...
Page 598 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 † TYPICAL CHARACTERISTICS DIGITAL SUPPLY CURRENT ANALOG SUPPLY CURRENT RATIO (Fclock/Fout) AT DV = 5 V FULL-SCALE OUTPUT CURRENT AV DD = 5 V AV DD = 5 V DV DD = 5 V 100 MSPS...
Page 599 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION The THS5641A architecture is based on current steering, combining high update rates with low power consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are capable of delivering a full-scale current up to 20 mA.
Page 600 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION D[7:0] Valid Data t s(DAC) t pd 0.1% Output 0.1% (IOUT1 or t r(IOUT) IOUT2) t h(D) t su(D) t d(D) 1/f CLK t w(LPH) Figure 23.
Page 601 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION DAC transfer function The THS5641A delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the binary input word has the decimal representation 255.
Page 602 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION reference operation The THS5641A comprises a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor R .
Page 603 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION analog current outputs Figure 26 shows a simplified schematic of the current source array output with corresponding switches. Differential PMOS switches direct the current of each individual PMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2.
Page 604 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION C FB R FB 50 Ω 100 Ω – IOUT1 IOUT1 VOUT VOUT –) IOUT2 IOUT2 THS4001 –) THS4011 50 Ω Figure 27. Differential and Single-Ended Output Configuration The THS5641A can be easily configured to drive a doubly terminated 50 Ω...
Page 605 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION sleep mode The THS5641A features a power-down mode that turns off the output current and reduces the supply current to less than 5 mA over the analog supply range of 3 V to 5.5 V and temperature range. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD).
Page 606 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 offset drift The change in offset error versus temperature from the ambient temperature (T = 25°C) in ppm of full-scale range per °C. gain drift The change in gain error versus temperature from the ambient temperature (T = 25°C) in ppm of full-scale range per °C.
Page 607 THS5641  8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A – MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION • • POST OFFICE BOX 1443 POST OFFICE BOX 655303 HOUSTON, TEXAS 77251–1443 DALLAS, TEXAS 75265...
Page 608 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION Figure 30. Board Layout, Layer 1 Figure 31. Board Layout, Layer 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265...
Page 609 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION Figure 32. Board Layout, Layer 3 Figure 33. Board Layout, Layer 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265...
Page 610 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION Figure 34. Board Layout, Layer 5 Table 2. Bill of Materials REF. DES PART NUMBER DESCRIPTION MFG. Ceranucm 1 µF, 10 V, X7R, 10% C1, C22, C31 1206ZC105KAT2A 6.3 V, 4.7 µF, tantalum...
Page 611 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION Table 2. Bill of Materials (Continued) REF. DES PART NUMBER DESCRIPTION MFG. 1206 Chip resistor, 33 Ω, 1/4 W, 1% R12, R19, R7, R9 1206 1206 Chip resistor, 0 Ω, 1/4 W, 1% R13, R17.
Page 612 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.010 (0,25) 0.014 (0,35) 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane...
Page 613 THS5641A 8-BIT, 100 MSPS, CommsDAC Appendix C DIGITAL-TO-ANALOG CONVERTER SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,10 0,65 0,19 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°– 8° 0,75 0,50 Seating Plane...
Page 614 Appendix C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
Page 615 Appendix D ADC Training Device Specifications...
Page 616 Appendix D The DUT board used for the training contains a DAC and an ADC. The following pages are a copy of the data sheet of the high speed 8-bit A/D converter TLC5510.
Page 617 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 features 5-V Single-Supply Operation Low Power Consumption Analog Input Range TLC5510 . . . 127.5 mW Typ – TLC5510 . . . 2 V Full Scale TLC5510A .
Page 618 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 functional block diagram Resistor Reference Divider REFB 270 Ω Lower Sampling REFT Lower Encoder D1(LSB) Comparators (4-Bit) REFBS (4-Bit) Lower Data 80 Ω Latch AGND Lower Sampling AGND...
Page 619 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 Terminal Functions TERMINAL DESCRIPTION NAME AGND 20, 21 Analog ground ANALOG IN Analog input Clock input DGND 2, 24 Digital ground D1 – D8 3 –...
Page 620 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 electrical characteristics at V = 5 V, V = 2.5 V, V = 0.5 V, f = 20 MHz, T = 25°C (unless REFT REFB (CLK) otherwise noted)
Page 621 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 operating characteristics at V = 5 V, V = 2.5 V, V = 0.5 V, f = 20 MHz, T = 25°C (unless REFT REFB (CLK) otherwise noted)
Page 622 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 operating characteristics at V = 5 V, V = 2.5 V, V = 0.5 V, f = 20 MHz, T = 25°C (unless REFT REFB (CLK) otherwise noted)
Page 623 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 PRINCIPLES OF OPERATION internal referencing TLC5510 The three internal resistors shown with V can generate a 2-V reference voltage. These resistors are brought out on V , REFTS, REFT, REFB, REFBS, and AGND.
Page 624 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 PRINCIPLES OF OPERATION functional operation The output code change with input voltage is shown in Table 1. Table 1. Functional Operation DIGITAL OUTPUT CODE INPUT SIGNAL INPUT SIGNAL STEP...
Page 625 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION DV DD TLC5510 AV DD Clock V DDD V REF V DDA V DDD V DDA D8 (MSB) REFTS Video REFT Input V DDA ANALOG IN AGND...
Page 626 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION DV DD TLC5510A AV DD Clock V DDD V REF V DDA V DDD V DDA D8 (MSB) REFTS Video REFT Input V DDA ANALOG IN AGND...
Page 627 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION AV DD 4.7 µF 0.1 µF 1 kΩ 10 kΩ POT CLOCK 1 kΩ TLC5510 4.7 µF 49.9 Ω CLOCK THS3001 ANALOG IN 49.9 Ω...
Page 628 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION 0.1µF 6.8µF CLOCK 698Ω TLC5510A 0.1µF 50Ω CLOCK 49.9Ω ANALOG IN OPA690 59Ω 100pF 698Ω 402Ω To Processor 402Ω 0.1µF † 4.7µF 0.1µF 4.7µF 0.1µF...
Page 629 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,10 0,65 0,19 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°– 8° 0,75 0,50 Seating Plane...
Page 630 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS Appendix D SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 MECHANICAL DATA NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN PINS ** 10,50 10,50 12,90 15,30 0,51 A MAX 1,27 0,25 0,35 9,90 9,90 12,30 14,70 A MIN...
Page 631 Appendix D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
Page 632 Appendix D...

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