Master And Slave Spi Configuration Port Pins; Table 4.5. Master Spi Configuration Port Pins; Table 4.6. Slave Spi Configuration Port Pins - Lattice Semiconductor CrossLink Programming And Configuration Manual

4.10.2. Master and Slave SPI Configuration Port Pins

Table 4.5. Master SPI Configuration Port Pins

Pin Name Function
MCK MCK
CRESET_B CRESET_B
MOSI MO
MISO MI
CSN CSN

Table 4.6. Slave SPI Configuration Port Pins

Pin Name Function
SPI_SCK SPI_SCK
CRESET_B CRESET_B
MOSI SI
MISO SO
SPI_SS SPI_SS
MCK/SPI_SCK
The MCK/SPI_SCK, when active, are clocks used to sequentially load the configuration data for the FPGA. The pin
functions as:
The MCK/SPI_SCK pin's default state for a CrossLink in the Feature Row HW Default Mode state is to act as the
configuration clock (that is MCK or SPI_SCK). This allows an external Slave SPI master controller to program CrossLink.
The maximum SPI_SCK frequency and the data setup/hold parameters can be found in the AC timing section of the
CrossLink Family Data Sheet
you want to use the port to reprogram CrossLink after it enters User Mode.
The MCK/SPI_SCK pin functions as a Master Clock (MCK) when CrossLink is configured in Dual Boot or External Boot
modes. The MCK becomes an output and provides a reference clock for a SPI Flash attached to the CrossLink's Master
SPI Configuration port. MCK actively drives until all of the configuration data has been received. When CrossLink enters
User Mode, the MCK output tri-states. This allows the MCK to become a general purpose I/O. The MCK is reserved for
use, in most post-configuration applications, as the reference clock for performing memory transactions with the
external SPI PROM.
CrossLink generates MCK from an internal oscillator. The initial frequency of the MCK is nominally 2 MHz. The MCK
frequency can be altered using the MCCLK_FREQ parameter. You can select the MCCLK_FREQ using the Diamond
Spreadsheet View. Following is a complete list of supported MCCLK frequencies:

2 MHz

3 MHz

6 MHz

12 MHz

24 MHz

48 MHz
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FPGA-TN-02014-1.2
Direction
Output with weak pullup
Input with weak pullup
Output
Input
Output
Direction
Input with weak pullup
Input with weak pullup
Input
Output
Input with weak pullup
(FPGA-DS-020017). The Feature Row must be configured to ENABLE the Slave SPI Port if
CrossLink Programming and Configuration Usage Guide
Description
Master clock used to time data transmission/reception from
the CrossLink Configuration Logic to a slave SPI PROM.
CRESETB is used to initiate programming / configuration
Optional: Tie HIGH for MSPI mode
This is the Master output which carries configuration
commands to the external SPI PROM.
This is the input to the Master which carries output data from
the slave SPI PROM to the CrossLink Configuration Logic.
CrossLink Master SPI chip select output pin for external SPI
Flash.
Description
Clock used to time data transmission/reception from an
external SPI master device to the CrossLink Configuration
Logic.
CRESETB is used to initiate programming / configuration
Optional: Tie to GND for SSPI mode
This is the input to the slave which receives data from the
external SPI master to the CrossLink Configuration Logic.
This is the output from the slave which carries output data
from the CrossLink Configuration Logic to the external SPI
master.
CrossLink Configuration Logic slave SPI chip select input.
Technical Note
13