Lattice Semiconductor MachXO2 Programming And Configuration Usage Manual

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Page 1 • Optional security bits for design protection © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Page 2: Definition Of Terms
This document uses the following terms to describe common functions: • BIT – The BIT file is the configuration data for the MachXO2 that is stored in an external SPI Flash. It is a binary file and is programmed unmodified into the SPI Flash.
Page 3: Configuration Process And Flow
The MachXO2 sysCONFIG ports provide industry standard communication protocols for programming and config- uring the FPGA. Each of the protocols shown in Table 1 provides a way to access the MachXO2 device’s internal Flash memory, or to load its configuration SRAM. The Memory Space Accessibility section provides information about the capabilities of each sysCONFIG port.
Page 4: Power-Up Sequence
MachXO2 Programming and Configuration Usage Guide Power-up Sequence In order for the MachXO2 to operate, power must be applied to the device. During a short period of time, as the voltages applied to the system rise, the FPGA will have an indeterminate state.
Page 5 • External DONE The first phase of the Wake-Up process is for the MachXO2 to release the Global Output Enable. When it is asserted, permits the FPGA’s I/O to exit a high-impedance state and take on their programmed output function.
Page 6: User Mode
Memory Space Accessibility The two internal memories, Flash and SRAM, of the MachXO2 have the ability to be read and written. Each port on the MachXO2 has a different level of access to each memory space. Table 2 provides a cross-reference of the MachXO2 ports and the memory space they can access.
Page 7: On-Chip Flash Programming
Bitstream/PROM Sizes The MachXO2 is a SRAM based FPGA. The SRAM configuration memory must be loaded from a non-volatile memory that can store all of the configuration data. The size of the configuration data is variable. It is based on the amount of logic available in the FPGA, and the number of pre-initialized Embedded Block RAM (EBR) components.
Page 8 MachXO2 Programming and Configuration Usage Guide The Configuration Flash is, for most designs, large enough to store the compressed configuration data that is loaded into the SRAM configuration memory. However, as the amount of logic in the design increases, and the amount of pre-initialized EBR increases, the size of the configuration data also increases.
Page 9: Feature Row
MachXO2 Programming and Configuration Usage Guide Feature Row The MachXO2 includes a Feature Row that is used to control FPGA resources. For example, the Feature Row is used to determine how the MachXO2 SRAM configuration memory is loaded. In other FPGAs this operation is con- trolled using external I/O pins.
Page 10 I/O: Erasing and re-programming the Feature Row causes the GPIO to temporarily revert to PROGRAMN input. In this case, if the general purpose I/O is driven or held low the MachXO2 will not complete its configuration process.
Page 11: Sysconfig™ Ports
Internal WISHBONE bus interface sysCONFIG Pins The MachXO2 provides a set of sysCONFIG I/O pins that you use to program and configure the FPGA. The sys- CONFIG pins are grouped together to create ports (i.e. JTAG, SSPI, I C, MSPI) that are used to interact with the FPGA for programming, configuration, and access of resources inside the FPGA.
Page 12 • You must prevent external logic from interfering with device programming. Make sure that recovered sysCONFIG pins are not asserted when the MachXO2 is in Feature Row HW Default Mode state. One example is driving PROGRAMN with an active low signal after the MachXO2 is in Feature Row HW Default Mode state. Failure to reprogram the Feature Row with PROGRAMN disabled prevents the FPGA from configuring and entering user mode.
Page 13 INTIL • After the t time period has elapsed the INITn pin is deasserted (i.e. is active high) to indicate the MachXO2 INTIL is ready for its configuration bits. The MachXO2 begins loading configuration data from either the internal Flash memory or an external SPI Flash.
Page 14 DONE The INITN pin of a MachXO2 device is not visible external to the device when in the Feature Row HW Default Mode state. The INITN pin, when in this mode, is pulled high by default. The INITN behavior described in Figure 7 is only visible outside the MachXO2 when the INITN pin is enabled.
Page 15 FPGA. The pin functions as: The MCLK/CCLK pin’s default state for a MachXO2 in the Feature Row HW Default Mode state is to act as the con- figuration clock (i.e., CCLK). This allows an external Slave SPI master controller to program the MachXO2. The...
Page 16 MachXO2’s programming and configuration logic. The SN pin is available when the MachXO2 is in the Feature Row HW Default Mode state, and in user mode when the Slave SPI port is set to the ENABLE setting.
Page 17 CSSPIN enters a high impedance state. When the MachXO2 is in the Feature Row HW Default Mode state the CSSPIN is a general purpose I/O with a weak pulldown. It must have an external pullup resistor when the External and Dual Boot configuration modes are used.
Page 18 MachXO2 Programming and Configuration Usage Guide The JTAG port is enabled by default when the MachXO2 is in the Feature Row HW Default Mode state. Like all of the other configuration port pins the JTAG pins can become general purpose I/O. Unlike the other ports, the default state for the JTAG port is to remain active in user mode (i.e.
Page 19: Configuration Modes
Configuration Mode include: • Speed: The MachXO2 is ready to run in a few milliseconds depending on the density of the device. • Security: The configuration data is never seen outside the device during the load to SRAM. You can prevent the internal memory from being read.
Page 20: Master Spi Configuration Mode (Mspi)
SPI Flash. The MSPI configuration port is not available when the MachXO2 is in the Feature Row HW Default Mode state. When configuring using the MSPI mode be sure to enable the MSPI port in the Feature Row. Lattice recommends having a secondary configuration port available, one that is active when the MachXO2 is in Feature Row HW Default Mode state (that is, blank/erased), that allows you to recover the MachXO2 in the event of a programming error.
Page 21 To ensure that the MachXO2 operates correctly using the MSPI configuration mode, make sure that: • The POR of the SPI Flash device is lower than the POR of the MachXO2 or the SPI Flash must be powered first. • SPI Flash Fmax is greater than the MachXO2 MCLK Fmax •...
Page 22 The microprocessor reads a data file crafted by the Diamond Deployment Tool, and runs the ispVME code. The firmware uses port I/O to drive the JTAG port of the MachXO2, which in turn passes the data to the Master SPI port. Refer to the ispVME tool suite for information about updating an attached SPI Flash using a microprocessor.
Page 23: Dual Boot Configuration Mode
4. MachXO2 times out because it fails to get the preamble in time and the boot up likewise fails. It is highly recommended that an SPI Flash be chosen which POR level is lower than the MachXO2 POR. If one is not available here are some workaround solutions: •...
Page 24: Slave Spi Mode (Sspi)
2. Program MachXO2 internal flash (using Flash Programming Mode). 3. Refresh or power cycle. To prevent the MachXO2 from using dual boot mode when using the User Master SPI controller, set the MASTER_SPI_PORT preference to EFB_USER. This reserves the Master SPI configuration port pins and pre- vents dual-boot.
Page 25 In the Slave SPI mode, the MCLK/CCLK pin becomes CCLK (i.e. Configuration clock). Input data is read into the MachXO2 device on the SI pin at the rising edge of CCLK. Output data is valid on the SO pin at the falling edge of CCLK.
Page 26: I 2 C Configuration Mode
C bus data line The I C Configuration port is available when the MachXO2 is in Feature Row HW Default Mode state (that is, blank/erased). The default state set for the I2C_PORT in the Diamond design software is to place the I2C_PORT in the DISABLE state.
Page 27: Wishbone Configuration Mode
Configuration Logic will operate correctly. WISHBONE Configuration Mode The MachXO2 can access the Configuration Flash, User Flash Memory, and the Feature Row from an internal WISHBONE bus. To use the WISHBONE bus the Embedded Function Block must be inserted into your design. You design logic to interface to the EFB and then perform WISHBONE bus transactions to access resources attached to the configuration logic.
Page 28: Jtag Mode
The JTAG port is available when the MachXO2 is in Feature Row HW Default Mode state (that is, blank/erased). The port is enabled by default by Diamond 1.4. The MachXO2 JTAG port pins are not dedicated to performing the IEEE 1149.1 TAP function. The JTAG port may be recovered for use as general purpose I/O. See the...
Page 29: Transfr Operation
2. User can use operations such as “XFlash Program Feature Rows” for this. 3. User can use operations like “XFlash TransFR” for this. 4. If new image failed to config MachXO2, the golden image in Flash will still config MachXO2, so system will still be running with original image.
Page 30: Software Selectable Options
Feature Row to select how it will configure. The Feature Row’s default state needs to be modified in almost every design. You use the Diamond Spreadsheet View to make the changes to the operation of the MachXO2 Feature Row which alters the operation of the configuration logic.
Page 31 The configuration and port options allow you to decide which configuration ports continue to operate after the MachXO2 device is in user mode. You can also control the availability of status pins, as well as the speed at which configuration data is read from an external PROM. The selections made here are saved in the Feature Row and remain in effect until the Feature Row is erased.
Page 32 There are two states to which the SLAVE_SPI_PORT preference can be set: • ENABLE – This setting preserves the SPI port I/O when the MachXO2 device is in user mode. When the pins are preserved, an external SPI master controller can interact with the configuration logic. The preference also prevents you from over-assigning I/O to the port pins.
Page 33 5.5%) clock frequency to begin retrieving data from the external SPI Flash. The MCLK_FREQ value is stored in the incoming configuration data. It is not stored in the Feature Row. The MachXO2 device reads a series of padding bits, a “start of data” word (0xBDB3) and a control register value. The control register contains the new MCLK_FREQ value.
Page 34: Bitstream Generation Options
EXTERNAL mode. EXTERNAL mode does not use any Configuration Flash or UFM resources. The UFM is available for your use in user mode. The MachXO2-256 device does not contain any UFM. The only configuration options available to this device are the CFG and EXTERNAL modes.
Page 35 MachXO2 Programming and Configuration Usage Guide USERCODE The MachXO2 Configuration Flash sector contains a 32-bit register for storing a user-defined value. The default value stored in the register is 0x00000000. Using the USERCODE preference you can assign any value to the reg- ister you desire.
Page 36: Security Options
MachXO2 Programming and Configuration Usage Guide Security Options The Security Options allow you to select from a range of options for tracking or securing the MachXO2 device. Table 19 provides a summary of these options. Table 19. Security Options Option Name...
Page 37: Device Wake-Up Sequence
When configuration is complete (the SRAM has been loaded), the device will wake up in a predictable fashion. If the MachXO2 device is the only device in the chain, or the last device in a chain, the wake-up process should be initiated by the completion of configuration.
Page 38: Wake-Up Clock Selection
The clock source used to complete the four state transitions in the wake-up sequence is user-selectable. Once the MachXO2 is configured, it enters the wake-up state, which is the transition between the configuration mode and user mode. This sequence is synchronized to a clock source, which defaults to MCLK/CCLK when sysCONFIG is used, or TCK when JTAG is used.
Page 39 Flash Programming The MachXO2’s internal Flash memory is the heart of the FPGA’s configuration system. It is flexible, allowing you to store the FPGA’s configuration data, as well as storing design specific data in the User Flash Memory. It is also a resource that uses a precise erase and programming sequence.
Page 40: Machxo2 Jedec File Format
MachXO2 Programming and Configuration Usage Guide MachXO2 JEDEC File Format All Lattice non-volatile devices support JEDEC files. Utilities are available in the Deployment Tool software for con- verting the JEDEC file into other programming file formats, such as STAPL, SVF, or bitstream (hex or binary). The relevant detail about the JEDEC file is provided in the table below for completeness.
Page 41 1. For encrypted JEDEC file, the first sixteen (16) bits of USERCODE is the CRC value calculated from of the row 0 only; the second sixteen (16) bits is the CRC value calculated from row 0 to the last row. An example of a MachXO2 unencrypted JEDEC file is shown in Figure 19...
Page 42 MachXO2 Programming and Configuration Usage Guide Figure 19. Unencrypted JEDEC File Example NOTE Diamond_1.2_Production (92) JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* NOTE DATE CREATED:Fri Dec 02 14:50:08 2011* NOTE DESIGN NAME:control_SoC_demo_impl1.ncd*...
Page 43: Machxo2 Flash Memory Programming Flow
MachXO2 Flash Memory Programming Flow The MachXO2 Flash memory erasure, and programming requires a specific set of steps and timing. The flow chart in this section describes the command sequences and the timing required for successful Flash programming. The commands and timing are common between all of the configuration ports.
Page 44 MachXO2 Programming and Configuration Usage Guide Program Configuration Flash? Transmit Reset Configuration Address (0x46) or Set Address Command (0xB4) Transmit PROGRAM command and 128 Bits of Data Delay Check 200 µs Busy? Transmit Read Busy Flag or Read Status Register...
Page 45 MachXO2 Programming and Configuration Usage Guide Program Usercode? Transmit Program USER- CODE with Data (0xC2) Delay Check 200 µs Busy? Transmit Read Busy Flag (0xF0) or Read Status Register Command (0x3C) Busy? Transmit Read Status Register Command (0x3C) Clean Fail?
Page 46 MachXO2 Programming and Configuration Usage Guide Transmit Read (Continued from Command with Previous Page) Number of Pages (0x73) Read Page Data Data Clean Transmit Reset UFM Address (0x46) or Set Address Command (0xB4) All Pages Read? Verify UFM? Write Transparent...
Page 47 MachXO2 Programming and Configuration Usage Guide Delay Check 200 µs Busy? Transmit Read Busy Flag (0xF0) or Read Status Register Command (0x3C) Busy? Transmit Read FEABITS Command (0xFB) Clean FEABITS Transmit Program Program DONE Done Command (0x5E) Delay Check 200 µs...
Page 48 MachXO2 Programming and Configuration Usage Guide Write Security Bit? Transmit Program SECURITY (0xCE) or SECURITY PLUS Command (0xCF) Delay Check 200 µs Flags? Transmit Read Busy Flag (0xF0) and Read Status Register Command (0x3C) Busy? Exit Fail? Program OTP Fuses?
Page 49 Notes: To 'Read Status Register' over the I C configuration port, the MachXO2 must have the EFB instantiated and with the EFB 'wb_clk_i' input connected to a valid clock source Retry of at least 7.5x the I2C bus rate. If the EFB is not instantiated...
Page 50 MachXO2 Programming and Configuration Usage Guide Clean Up Transmit Erase Flash CF/UFM/FR Command (0x0E) Transmit Read Busy Flag (0xF0) or Read Note: Do Not use fixed delays Status Register for the Flash erase sequence. Command (0x3C) Busy? Transmit Refresh Command (0x79)
Page 51: Machxo2 Programming Commands
MachXO2 Programming and Configuration Usage Guide MachXO2 Programming Commands Table 22. MachXO2 sysCONFIG Programming Commands Command Name [SVF Synonym] Command Operands Write Data Read Data Notes Read Device ID YY characters represent the device-specific 0xE0 00 00 00 YY YY YY YY...
Page 52 MachXO2 Programming and Configuration Usage Guide Table 22. MachXO2 sysCONFIG Programming Commands (Continued) Command Name [SVF Synonym] Command Operands Write Data Read Data Notes Retrieves PPPP count UFM pages. Only the least significant 14 bits of PP PP are used for the page count.
Page 53: Reading Flash Pages
For example, reading two pages requires the page count supplied in the Read Flash/Read UFM Flash command to be assigned a value of 3. If the Page Address Pointer is 0000, the MachXO2 will return three pages, Page 0, Page 0, and Page 1. A restriction must be observed when using the WISHBONE interface to read the configuration flash or UFM.
Page 54: Technical Support Assistance
Reading the final four dummy bytes is optional. References • DS1035, MachXO2 Family Data Sheet • TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices • TN1207, Using TraceID in MachXO2 Devices Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport.
Page 55 Updated Technical Support Assistance section. Updated Self Download Port Pins section. Added information on the DONE pin. Updated Dual Boot Configuration Mode section. — Added information on delay MachXO2 POR until SPI Flash POR is completed. — Updated Figure 11, RC Delay. March 2015 Updated Master and Slave SPI Configuration Port Pins section.
Page 56 Clarified recovered PROGRAMN, SN danger when erasing FR. November 2013 02.8 Corrected FEABits Command (0xFB) to FEABITS Command (0xF8) in Step 3 of the MachXO2 Flash Memory Programming Flow diagram. October 2013 02.7 Updated the Default State of the sysCONFIG Pins table.
Page 57 Change Summary July 2012 02.1 Clarified SECURITY/SECURITY PLUS in Figure 16, MachXO2 Flash Memory Programming Flow, and Table 21, MachXO2 sysCONFIG Pro- gramming Commands. Added Figure 17, Retrieval Delay Timing Requirement for Single-Page Reads. Clarified Retrieval delay in Figure 18, Flash Page Command and Data Sequence.

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