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Instruction Words
With the exception of certain peripheral equipment operations, a GE-235 instruction i s a single-
address word consisting of 20 bits.
Except for branching operations, instructions a r e executed
sequentially; the reading of the next instruction from memory occurs after the execution of the
current instruction.
The basic format of the instruction word
is:
Bits
0
4
5
6
7
19
Bits
0
4
5
6
7
19
DO THIS
Bits 0 through
4
designate the operation to be performed, bits 5 and 6 indicate whether the in-
struction i s to be automatically modified (indexed), and bits 7 through 19 indicate the operand
address.
Opera tion
Code
Because the five bit positions allowed in the instruction word for the operation code can define
only 32 operations, additional bit positions a r e required to define the more than 300 instructions
in the repertoire of the GE-235.
This i s achieved by using bit positions in the operand address
field f o r instructions that require only a limited portion of that field.
X
X
REGISTERS
WITH DATA LOCATED HERE
X X
With the exception of shift instructions, all information transfers between Central P r o c e s s o r
registers, between the registers and memory, and between the registers and the adder occur in
parallel.
That i s , all 20 bits comprising words in transit o r being operated upon arithmetically
a r e transferred a t the same time.
Operand Address
A Register
The
A
register i s a 20-bit register that s e r v e s a s the accumulator for the Central Processor.
It performs this function by holding:
The augend during addition.
The sum after addition.
The minuend during subtraction.
IV- 6
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