Usb Phase Locked Loop - Usb Pll; Table 16. Feedback Divider 2 Value Mapping; Figure 17. Usb Pll Block Diagram - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Table 16. Feedback Divider 2 Value Mapping

Feedback divider 2 setting B4 ~ B0 (PFBD)
USB Phase Locked Loop – USB PLL
This USB PLL can provide 4 ~ 48 MHz clock output for USB peripheral which is 2 ~ 24 multiples
of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies
on the digital Phase Locked Loop (PLL) which includes a reference divider, a feedback divider, a
digital phase frequency detector (PFD), a current-controlled charge pump (CP), a built-in loop filter
and a voltage-controlled oscillator (VCO) to achieve a stable phase-locked state.
Ref. Divider
CLK
IN
(NR)
= 4 ~ 16 MHz
/2

Figure 17. USB PLL Block Diagram

Rev. 1.10
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
....
....
11110
11111
PD CP VCO
Loop
Filter
Feedback Divider 2 Feedback Divider 1
(NF2) (NF1)
/4
B3 ~ B0
88 of 590
NF2 (Feedback divider 2 value)
32
1
2
3
4
5
6
7
8
9
10
11
....
....
30
31
VCO = 48 ~ 96 MHz
out
Output Divider 1 Output Divider 2
(NO1) (NO2)
/2
S1 ~ S0
November 28, 2018
PLL
out
= 4 ~ 48 MHz