1. Manuals
  2. Brands
  3. Cypress Manuals
  4. Microcontrollers
  5. PSoC 4000 Series
  6. Architecture technical reference manual

Cypress PSoC 4000 Series Architecture Technical Reference Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
PSoC 4000 TRM
PSoC 4000 Family
®
PSoC
4 Architecture Technical Reference
Manual (TRM)
Document No. 001-89309 Rev. *D
May 31, 2017
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): +1.800.858.1810
Phone (Intnl): +1.408.943.2600
www.cypress.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PSoC 4000 Series and is the answer not in the manual?

Questions and answers

Related Manuals for Cypress PSoC 4000 Series

Summary of Contents for Cypress PSoC 4000 Series

  • Page 1 PSoC 4000 TRM PSoC 4000 Family ® PSoC 4 Architecture Technical Reference Manual (TRM) Document No. 001-89309 Rev. *D May 31, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): +1.800.858.1810 Phone (Intnl): +1.408.943.2600 www.cypress.com...
  • Page 2 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
  • Page 3 Contents Overview Section A: Overview Introduction ........................13 Getting Started ......................17 Document Construction ....................19 Section B: CPU System Cortex-M0 CPU ......................25 Interrupts ........................31 Section C: Memory System Memory Map ......................... 41 Section D: System Resources Subsystem (SRSS) I/O System ........................
  • Page 4 Contents PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 5: Table Of Contents

    Contents Section A: Overview Introduction Top Level Architecture......................13 Features..........................14 CPU System ...........................14 1.3.1 Processor.......................14 1.3.2 Interrupt Controller ....................14 Memory...........................15 System-Wide Resources ......................15 1.5.1 Clocking System ....................15 1.5.2 Power System......................15 1.5.3 GPIO ........................15 Fixed-Function Digital ......................15 1.6.1 Timer/Counter/PWM Block..................15 1.6.2 Serial Communication BlocksI2C Block..............15 Special Function Peripherals ....................15 1.7.1 CapSense ......................15...
  • Page 6 Contents 4.7.1 Address Alignment ....................29 4.7.2 Memory Endianness ....................29 Systick Timer .......................... 29 Debug ............................. 29 Interrupts Features ..........................31 How It Works .......................... 31 Interrupts and Exceptions - Operation..................32 5.3.1 Interrupt/Exception Handling ................. 32 5.3.2 Level and Pulse Interrupts ..................32 5.3.3 Exception Vector Table ..................
  • Page 7 Contents Clocking System Block Diagram ........................55 Clock Sources.........................56 8.2.1 Internal Main Oscillator ..................56 8.2.2 Internal Low-speed Oscillator ................57 8.2.3 External Clock (EXTCLK) ..................57 Clock Distribution........................57 8.3.1 HFCLK Input Selection ..................57 8.3.2 HFCLK Predivider Configuration................58 8.3.3 SYSCLK Prescaler Configuration ................58 8.3.4 Peripheral Clock Divider Configuration ..............58 Low-Power Mode Operation .....................59 Register List..........................59...
  • Page 8 Contents 13.1.3 Watchdog Reset ....................77 13.1.4 Software Initiated Reset..................78 13.1.5 External Reset ....................... 78 13.1.6 Protection Fault Reset ................... 78 13.2 Identifying Reset Sources....................... 78 13.3 Register List..........................78 14. Device Security 14.1 Features ..........................79 14.2 How It Works .......................... 79 14.2.1 Device Security......................
  • Page 9 Contents 17.4 CapSense CSD Sensing ......................129 17.4.1 GPIO Cell Capacitance to Current Converter ............129 17.4.2 CapSense Clock Generator .................131 17.4.3 Sigma Delta Converter..................131 17.5 CapSense CSD Shielding.....................133 17.5.1 CMOD Precharge ....................134 17.6 General-Purpose Resources: IDACs and Comparator............135 17.7 Register List..........................135 Section G: Program and Debug 18.
  • Page 10 Contents Index PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 11: Section A: Overview

    Section A: Overview This section encompasses the following chapters: ■ Introduction chapter on page 13 ■ Getting Started chapter on page 17 ■ Document Construction chapter on page 19 Document Revision History Origin of Revision Issue Date Description of Change Change April 15, 2014 NIDH...
  • Page 12 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 13: Introduction

    1. Introduction ® ® ® PSoC 4 is a programmable embedded system controller with an ARM Cortex -M0 CPU.CY8C4000 family is the smallest member of the PSoC 4 family of devices and is upward-compatible with larger members of PSoC 4. PSoC 4 devices have these characteristics: ■...

  • Page 14: Features

    Introduction Figure 1-1. PSoC 4000 Family Block Diagram CPU Subsystem PSoC 4000 SWD/TC SPCIF Cortex Flash SRAM 32-bit 16 KB 2 KB 4 KB 16 MHz AHB- Lite Read Accelerator SRAM Controller ROM Controller NVIC, IRQMX System Resources Lite System Interconnect ( Single/Multi Layer AHB ) Power Sleep Control Peripherals...

  • Page 15: Memory

    Introduction Memory frequency clock is ON and the low-frequency peripherals are in operation. The PSoC 4 memory subsystem consists of a 16 KB flash Multiple internal regulators are available in the system to module with a flash accelerator, 2 KB SRAM, and 4 KB support power supply schemes in different power modes.

  • Page 16: Program And Debug

    Introduction 1.7.1.1 IDACs and Comparator The CapSense block has two IDACs and a comparator with a 12-V reference, which can be used for general purposes, if CapSense is not used. Program and Debug PSoC 4 devices support programming and debugging fea- tures of the device via the on-chip SWD interface.

  • Page 17: Getting Started

    Documentation section. Development Kits The Cypress Online Store contains development kits, C compilers, and the accessories you need to successfully develop PSoC projects. Visit the Cypress Online Store website at www.cypress.com/cypress-store. Under Products, click Program- mable System-on-Chip to view a list of available items.
  • Page 18 Getting Started PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 19: Document Construction

    3. Document Construction This document includes the following sections: ■ Section B: CPU System on page 23 ■ Section D: System Resources Subsystem (SRSS) on page 43 ■ Section E: Digital System on page 81 ■ Section F: Analog System on page 125 ■...

  • Page 20: Units Of Measure

    Document Construction 3.2.3 Units of Measure Table 3-2. Acronyms (continued) Acronym Definition This table lists the units of measure used in this document. APOR analog power-on reset Table 3-1. Units of Measure broadcast clock brownout detect Abbreviation Unit of Measure bill of materials bits per second bit rate...
  • Page 21 Document Construction Table 3-2. Acronyms (continued) Table 3-2. Acronyms (continued) Acronym Definition Acronym Definition IRES initial power on reset signal-to-noise ratio interrupt request acknowledge start of frame interrupt request start of instruction interrupt service routine stack pointer interrupt vector read sequential phase detector liquid crystal display serial peripheral interconnect...
  • Page 22 Document Construction PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 23: Section B: Cpu System

    Section B: CPU System This section encompasses the following chapters: ■ Cortex-M0 CPU chapter on page 25 ■ Interrupts chapter on page 31 Top Level Architecture CPU System Block Diagram SWD/TC Cortex-M0 16 MHz (14 DMIPS) NVIC, IRQMX System Interconnect (Single Layer AHB) PSoC 4000 Family: PSoC 4 Architecture TRM, Document No.
  • Page 24 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 25: Cortex-M0 Cpu

    4. Cortex-M0 CPU ® The PSoC 4 ARM Cortex-M0 core is a 32-bit CPU optimized for low-power operation. It has an efficient three-stage pipeline, a fixed 4-GB memory map, and supports the ARMv6-M Thumb instruction set. The Cortex-M0 also features a single-cycle 32- bit multiply instruction and low-latency interrupt handling.

  • Page 26: Block Diagram

    Cortex-M0 CPU Block Diagram Figure 4-1. PSoC 4 CPU Subsystem Block Diagram CPU Subsystem Interrupt ARM Cortex-M0 CPU Test Controller System Interconnect Flash Flash SRAM SROM Programming Accelerator Controller Controller Interface CPU & Memory Flash SRAM SROM Subsystem AHB Bridge How It Works The Cortex-M0 is a 32-bit processor with a 32-bit data path, 32-bit registers, and a 32-bit memory interface.

  • Page 27: Registers

    Cortex-M0 CPU Registers The Cortex-M0 has 16 32-bit registers, as Table 4-2 shows: ■ R0 to R12 – General-purpose registers. R0 to R7 can be accessed by all instructions; the other registers can be accessed by a subset of the instructions. ■...

  • Page 28: Operating Modes

    Cortex-M0 CPU Table 4-3. Cortex-M0 PSR Bit Assignments PSR Register Name Usage 27 – 25 – – Reserved Thumb state bit. Must always be 1. Attempting to execute instructions when the T bit is 0 EPSR results in a HardFault exception. 23 –...

  • Page 29: Address Alignment

    Cortex-M0 CPU Table 4-4. Thumb Instruction Set Table 4-4. Thumb Instruction Set Mnemonic Brief Description Mnemonic Brief Description Send event ADCS Add with carry Store multiple registers, increment after ADD{S} Store register as word PC-relative address to register STRB Store register as byte ANDS Bit wise AND STRH...
  • Page 30 Cortex-M0 CPU PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 31: Interrupts

    5. Interrupts ® The ARM Cortex-M0 (CM0) CPU in PSoC 4 supports interrupts and exceptions. Interrupts refer to those events generated by peripherals external to the CPU such as timers, serial communication block, and port pin signals. Exceptions refer to those events that are generated by the CPU such as memory access faults and internal system timer events.

  • Page 32: Interrupts And Exceptions - Operation

    Interrupts Interrupts and Exceptions - When the NVIC receives an interrupt request while another interrupt is being serviced or receives multiple interrupt Operation requests at the same time, it evaluates the priority of all these interrupts, sending the exception number of the high- est priority interrupt to the CPU.

  • Page 33: Exception Vector Table

    (SROM). The boot code and addresses for the stack pointer and reset vector from SROM other data in SROM memory are programmed by Cypress, when the device reset is released. For reset, boot code in and are not read/write accessible to external users. After...

  • Page 34: Non-Maskable Interrupt (Nmi) Exception

    Interrupts of the startup code in flash memory. The CPU starts execut- supervisor call that requires privileged access to the system. ing code out of this address. Note that the reset exception Note that the CM0 in PSoC 4 uses a privileged mode for the address in the SRAM vector table will never be used system call NMI exception, which is not related to the SVCall because the device comes out of reset with the flash vector...

  • Page 35: Systick Exception

    Interrupts 5.4.6 SysTick Exception Interrupt Sources CM0 CPU in PSoC 4 supports a system timer, referred to as PSoC 4 supports nine interrupts (IRQ0 to IRQ8 or exception SysTick, as part of its internal architecture. SysTick provides numbers 16 – 24) from peripherals. The source of each a simple, 24-bit decrementing counter for various timekeep- interrupt is listed in Table...

  • Page 36: Enabling And Disabling Interrupts

    Interrupts Exception States Table 5-3. Interrupt Priority Register Bit Definitions Each exception can be in one of the following states. Bits Name Description Table 5-5. Exception States PRI_N0 Priority of interrupt number N. 15:14 PRI_N1 Priority of interrupt number N+1. Exception State Meaning 23:22...

  • Page 37: Stack Usage For Exceptions

    Interrupts Table 5-6 shows the register access properties for these two current exception, the MSP is used for stack push/pop registers. Note that writing zero to these registers has no operations, because the CPU is already in handler mode. effect. See the Cortex-M0 CPU chapter on page 35 for details.

  • Page 38: Exceptions - Initialization And Configuration

    Interrupts 5.11 Exceptions – Initialization and Configuration This section covers the different steps involved in initializing and configuring exceptions in PSoC 4. 1. Configuring the Exception Vector Table Location: The first step in using exceptions is to configure the vector table location as required –...

  • Page 39: Section C: Memory System

    Section C: Memory System This section presents the following chapter: ■ Memory Map chapter on page 41 Top Level Architecture Memory System Block Diagram SPCIF FLASH SRAM SROM 16 KB 2 kB 4 kB Read Accelerator SRAM Controller ROM Controller System Interconnect (Single Layer AHB) PSoC 4000 Family: PSoC 4 Architecture TRM, Document No.
  • Page 40 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 41: Memory Map

    6. Memory Map ® All PSoC 4 memory (flash, SRAM, and SROM) and all registers are accessible by the CPU and in most cases by the debug system. This chapter contains an overall map of the addresses of the memories and registers. Features The PSoC 4 memory system has the following features: ■...
  • Page 42 Memory Map Table 6-2 shows the PSoC 4 address map. Table 6-2. PSoC 4 Address Map Address Range 0x00000000 - 0x00003FFF 16 KB flash 0x0FFFF000 - 0x10000000 4 KB supervisory flash 0x20000000 - 0x200007FF 2 KB SRAM 0x40100000 - 0x4011FFFF CPU subsystem registers 0x40020000 - 0x40023FFF I/O port control (high-speed I/O matrix) registers...

  • Page 43: Section D: System Resources Subsystem (Srss)

    Section D: System Resources Subsystem (SRSS) This section encompasses the following chapters: ■ I/O System chapter on page 45 ■ Clocking System chapter on page 55 ■ Power Supply and Monitoring chapter on page 61 ■ Chip Operational Modes chapter on page 67 ■...
  • Page 44 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 45: I/O System

    7. I/O System ® This chapter explains the PSoC 4 I/O system, its features, architecture, operating modes, and interrupts. The GPIO pins in PSoC 4 are grouped into ports; a port can have a maximum of eight GPIOs. PSoC 4000 family has a maximum of 20 GPIOs arranged in four ports.

  • Page 46: I/O Cell Architecture

    I/O System Figure 7-1. GPIO Interface Overview GPIO Port Control Fixed Function Digital Controller Peripherals (TCPWM, I2C) High Speed IO Matrix (HSIOM) IO Cell CapSense AMUXBUS-A AMUXBUS-B GPIO pins are connected to I/O cells. These cells are equipped with an input buffer for the digital input, providing high input impedance and a driver for the digital output signals.

  • Page 47: Digital Input Buffer

    I/O System Figure 7-2. I/O Cell Architecture in PSoC 4000 IO CELL PORT_VTRIP_SEL (GPIO_PRTx_PC[24]) INP_DIS (GPIO_PRTx_PC2[y]) EDGE_SEL (GPIO_PRTx_INTR_CFG[2y+1:2y]) DATA GPIO (GPIO_PRTx_INTR[y]) Edge Detect Pin Interrupt Signal Buffer Mode Select -------------------------- CMOS LVTTL Input Buffer Disable DATA (GPIO_PRTx_PS[y]) HSIOM HSIOM_PORT_SELx[4y+3:4y] Input Buffer PORT_SLOW (GPIO_PRTx_PC[25]) Output Driver HSIOM_PORT_SELx[4y+3:4y]...

  • Page 48: Digital Output Driver

    I/O System These buffer modes are selected by the PORT_VTRIP_SEL peripheral is selected by writing to the HSIOM port select bit (GPIO_PRTx_PC[24]) of the Port Configuration register. register (HSIOM_PORT_SELx). PSoC 4000 has a dedicated I/O supply voltage pin VDDIO in Table 7-1.
  • Page 49 I/O System Figure 7-3. I/O Drive Mode Block Diagram 0 . High Impedance 1 . High Impedance 2 . Resistive Pull Up 3 . Resistive Pull Down Analog Digital 4 . Open Drain , 5 . Open Drain , 6 . Strong Drive 7 .
  • Page 50 I/O System ■ Resistive Pull-Up and Resistive Pull-Down In the resistive pull-up and resistive pull-down mode, the GPIO will have a series resistance in both logic 1 and logic 0 output states. The high data state is pulled up while the low data state is pulled down. This mode is used when the bus is driven by other signals that may cause shorts.

  • Page 51: High-Speed I/O Matrix

    I/O System High-Speed I/O Matrix The high-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the peripherals inside the device. As the GPIOs are shared for multiple functions, HSIOM multiplexes the pin and connects to a particular peripheral selected by the user.
  • Page 52 I/O System Figure 7-4 shows the GPIO Edge Detect block architecture. Figure 7-4. GPIO Edge Detect Block Architecture Edge Detector 50 ns Glitch Filter Pin 0 Edge Detector Pin 1 Edge Detector Pin 2 Edge Detector Pin 3 Interrupt Edge Detector Signal Pin 4 Edge Detector...

  • Page 53: Peripheral Connections

    I/O System Peripheral Connections affecting other pins. Writing ‘1’ into these registers will set, clear, or invert; writing ‘0’ will have no affect on the pin sta- tus. 7.8.1 Firmware Controlled GPIO GPIO_PRTx_PS is the I/O pad register that provides the Table 7-3 to know the HSIOM settings for a firmware state of the GPIOs when read.
  • Page 54 I/O System PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 55: Clocking System

    8. Clocking System ® The PSoC 4 clock system includes these clock resources: ■ Two internal clock sources: ❐ 24–48 MHz internal main oscillator (IMO) with ±2 percent accuracy across all frequencies with trim ❐ 40-kHz internal low-speed oscillator (ILO) (can be calibrated using the IMO) ■...

  • Page 56: Clock Sources

    Clocking System The three clock sources in the device are IMO, EXTCLK, Table 8-1. IMO Frequency Configuration and ILO, as shown in Figure 8-1. The HFCLK mux selects the HFCLK source from the EXTCLK or the IMO. The CLK_IMO_TRIM2 Frequency in HFCLK predivider divides the HFCLK input.

  • Page 57: Internal Low-Speed Oscillator

    Clocking System 8.2.1.1 Startup Behavior from flash and the IMO is configured to achieve datasheet specified accuracy. The HFCLK predivider is initially set to a After reset, the IMO is configured for 24-MHz operation. divide value of 4 to reduce current consumption at startup. During the “boot”...

  • Page 58: Hfclk Predivider Configuration

    Clocking System 8.3.2 HFCLK Predivider Configuration The HFCLK predivider allows the device to divide the HFCLK selection mux input before use as HFCLK. The predivider is capable of dividing the HFCLK by powers of 2 between 1 and 8. The predivider value is set using register CLK_SELECT bits HFCLK_DIV, as described in Table 8-3.

  • Page 59: Low-Power Mode Operation

    Clocking System Input clocks to the peripherals are selected by PERI_PCLK_CTLx registers. Table 8-6 shows the peripheral clocks and their respective registers. See the PSoC 4000 Family: PSoC 4 Registers TRM for more details. Table 8-6. Selecting Peripheral Clocks Clock Register SCB (I2C) PERI_PCLK_CTL0...
  • Page 60 Clocking System PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 61: Power Supply And Monitoring

    9. Power Supply and Monitoring ® PSoC 4 is capable of operating from a 1.71 V to 5.5 V externally supplied voltage. This is supported through one of the two following operating ranges: ■ 1.80 V to 5.50 V supply input to the internal regulators ■...

  • Page 62: Block Diagram

    Power Supply and Monitoring Block Diagram Figure 9-1. Power System Block Diagram DDIO 1 uF 0.1 uF 1 uF 0.1 uF 1 uF Note: Do not connect external load to V Active Domain Digital Examples: CPU, Regulator IMO, Flash Bandgap Quiet Voltage Regulator...

  • Page 63: Power Supply Scenarios

    Power Supply and Monitoring Power Supply Scenarios The following diagrams illustrate the different ways in which the device is powered. 9.2.1 Single 1.8 V to 5.5 V Unregulated Supply If a 1.8-V to 5.5-V supply is to be used as the unregulated power supply input, it should be connected as shown in Figure 9-2.

  • Page 64: Vddio Supply

    Power Supply and Monitoring Figure 9-3. Single Unregulated V Supply 1.71 V-1.89 V PSoC 4 0.1 uF 1 uF In this mode, V and V pins are shorted together and in the Deep-Sleep mode (see Table 9-1 Figure 9-1). bypassed. The internal regulator should be disabled in firm- Table 9-1.

  • Page 65: Voltage Monitoring

    Power Supply and Monitoring a high-power supply rejection ratio. The Quiet regulator is POR circuits are not very accurate with respect to trip-point. available only in Active and Sleep power modes. POR circuits are used during initial chip power-up and then disabled.
  • Page 66 Power Supply and Monitoring PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 67: 10. Chip Operational Modes

    10. Chip Operational Modes ® PSoC 4 is capable of executing firmware in four different modes. These modes dictate execution from different locations in flash and ROM, with different levels of hardware privileges. Only three of these modes are used in end-applications; debug mode is used exclusively to debug designs during firmware development.
  • Page 68 Chip Operational Modes PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 69: 11. Power Modes

    11. Power Modes ® The PSoC 4 provides three power modes, intended to minimize the average power consumption for a given application. The power modes, in the order of decreasing power consumption, are: ■ Active ■ Sleep ■ Deep-Sleep Active, Sleep, and Deep-Sleep are standard ARM-defined power modes, supported by the ARM CPUs and instruction set architecture (ISA).

  • Page 70: Active Mode

    Power Modes Table 11-1 illustrates the power modes offered by PSoC 4. Table 11-1. PSoC 4 Power Modes Power Wakeup Wakeup Description Entry Condition Active Clocks Available Regulators Mode Sources Action Wakeup from other All regulators are available. Primary mode of opera- power modes, inter- All (programma- The Active digital regulator...

  • Page 71: Power Mode Summary

    Power Modes 11.4 Power Mode Summary Table 11-3 illustrates the peripherals available in each low-power mode; Table 11-3 illustrates the wakeup sources available in each power mode. Table 11-2. Available Peripherals Peripheral Active Sleep Deep-Sleep Available Retention Retention SRAM Available Retention Retention High-speed peripherals...

  • Page 72: Low-Power Mode Entry And Exit

    Power Modes 11.5 Low-Power Mode Entry and Exit A Wait For Interrupt (WFI) instruction from the Cortex-M0 (CM0) triggers the transitions into Sleep and Deep-Sleep mode. The Cortex-M0 can delay the transition into a low-power mode until the lowest priority ISR is exited (if the SLEEPONEXIT bit in the CM0 System Control Register is set).

  • Page 73: 12. Watchdog Timer

    12. Watchdog Timer The watchdog timer (WDT) is used to automatically reset the device in the event of an unexpected firmware execution path or a brownout that compromises the CPU functionality. The WDT runs from the LFCLK, generated by the ILO. The timer must be serviced periodically in firmware to avoid a reset.

  • Page 74: Enabling And Disabling Wdt

    Watchdog Timer The IGNORE_BITS in the WDT_MATCH register can be used to reduce the entire WDT counter period. The ignore bits can specify the number of MSBs that need to be discarded. For example, if the IGNORE_BITS value is 3, then the WDT counter becomes a 13-bit counter.

  • Page 75: Wdt Interrupts And Low-Power Modes

    Watchdog Timer 12.3.2 WDT Interrupts and Low-Power Modes The watchdog counter can send interrupt requests to the CPU in Active power mode and to the WakeUp Interrupt Controller (WIC) in Sleep and Deep-Sleep power modes. It works as follows: ■ Active Mode: In Active power mode, the WDT can send the interrupt to the CPU.
  • Page 76 Watchdog Timer PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 77: 13. Reset System

    13. Reset System ® PSoC 4 supports several types of resets that guarantee error-free operation during power up and allow the device to reset based on user-supplied external hardware or internal software reset signals. PSoC 4 also contains hardware to enable the detection of certain resets.

  • Page 78: Software Initiated Reset

    Reset System 13.1.4 Software Initiated Reset Software initiated reset (SRES) is a mechanism that allows a software-driven reset. The Cortex-M0 application interrupt and reset control register (CM0_AIRCR) forces a device reset when a ‘1’ is written into the SYSRESETREQ bit. CM0_AIRCR requires a value of A05F written to the top two bytes for writes.

  • Page 79: Device Security

    14. Device Security ® PSoC 4 offers a number of options for protecting user designs from unauthorized access or copying. Disabling debug fea- tures and enabling flash protection provide a high level of security. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging.

  • Page 80: Flash Security

    Device Security gram flash is not available. The part cannot be taken out of KILL mode; devices in KILL mode may not be returned for fail- ure analysis. 14.2.2 Flash Security The PSoC 4 devices include a flexible flash-protection system that controls access to flash memory. This feature is designed to secure proprietary code, but it can also be used to protect against inadvertent writes to the bootloader portion of flash.

  • Page 81: Section E: Digital System

    Section E: Digital System This section encompasses the following chapters: ■ Inter-Integrated Circuit (I2C) chapter on page 83 ■ Timer, Counter, and PWM chapter on page 101 Top Level Architecture Digital System Block Diagram Peripheral Interconnect (MMIO) High Speed I/O Matrix PSoC 4000 Family: PSoC 4 Architecture TRM, Document No.
  • Page 82 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 83: Inter-Integrated Circuit (I2C)

    15. Inter-Integrated Circuit (I2C) PSoC 4 contains a Serial Communication Block (SCB) configured to operate as a fixed-function I2C block. This section explains the I C implementation in PSoC. For more information on the I C protocol specification, refer to the I C-bus specifi- cation available on the website.

  • Page 84: Terms And Definitions

    Inter-Integrated Circuit (I2C) 15.2.1 Terms and Definitions clock on the SCL line. Table 15-2 illustrates the I C modes of operation. Table 15-1 explains the commonly used terms in an I communication network. Table 15-2. I C Modes Mode Description Table 15-1.
  • Page 85 Inter-Integrated Circuit (I2C) 15.2.2.1 Write Transfer Figure 15-2. Master Write Data Transfer Write data transfer(Master writes the data) Write ACK START Slave address (7 bits) Data(8 bits) STOP LEGEND : SDA: Serial Data Line SCL: Serial Clock Line(always driven by the master) Slave Transmit / Master Receive ■...

  • Page 86: Easy I2C (Ezi2C) Protocol

    An EZ write to a memory array index is by means of an I scheme built on top of the I C protocol by Cypress. It uses a write transfer. The first transmitted write data is used to send software wrapper around the standard I C protocol to com- an EZ address from the master to the slave.

  • Page 87: I2C Registers

    Inter-Integrated Circuit (I2C) 15.2.4 I2C Registers The I C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed in Table 15-4. Table 15-4. I2C Registers Register Function Enables the I2C block and selects the type of serial interface (I2C). Also used to select internally and exter- SCB_CTRL nally clocked operation and EZ and non-EZ modes of operation.

  • Page 88: I2C Interrupts

    Inter-Integrated Circuit (I2C) 15.2.5 I2C Interrupts ❐ I2C STOP detection at the end of a write transfer ❐ I2C STOP detection at the end of a read transfer The fixed-function I C block generates interrupts for the fol- The I2C interrupt signal is hard-wired to the Cortex-M0 NVIC lowing conditions.

  • Page 89: Internal And External Clock Operation In I2C

    Inter-Integrated Circuit (I2C) Table 15-6. SCB_TX_CTRL/SCB_RX_CTRL Register Bits Name Description 'DATA_WIDTH + 1' is the number of bits in the transmitted or received data [3:0] DATA_ WIDTH frame. This is always 7. 1= MSB first (this should always be true) MSB_FIRST 0= LSB first This is for SCB_RX_CTRL only.
  • Page 90 Inter-Integrated Circuit (I2C) ■ EC_AM_MODE (Externally Clocked Address Matching Mode) : Indicates whether I2C address matching is internally ('0') or externally ('1') clocked. ■ EC_OP_MODE (Externally Clocked Operation Mode) : Indicates whether the rest of the protocol operation (besides I2C address match) is internally ('0') or externally ('1') clocked.

  • Page 91: Wake Up From Sleep

    Inter-Integrated Circuit (I2C) nally clocked logic (rest of the operation). The combination EC_AM_MODE = 0 and EC_OP_MODE = 1 is invalid and the block will not respond. Table 15-10. I2C Operation in EZ Mode I2C, EZ Mode EC_OP_MODE= 0 EC_OP_MODE = 1 System Power Mode EC_AM_MODE = 0...

  • Page 92: Master Mode Transfer Examples

    Inter-Integrated Circuit (I2C) 15.2.9 Master Mode Transfer Examples Master mode transmits or receives data. 15.2.9.1 Master Transmit Figure 15-5. Single Master Mode Write Operation Flow Chart Begin TX FIFO Empty? Disable Fixed Function I2C block Transmission (stretch) Error of one byte Select Master data complete? mode...
  • Page 93 Inter-Integrated Circuit (I2C) 15.2.9.2 Master Receive Figure 15-6. Single Master Mode Read Operation Flow Chart Begin RX FIFO full? Disable Fixed Function I2C block Receiving Error one byte data Select Master complete? mode Enable Data transfer RX FIFO Send ACK complete? Enable Fixed Function I2C block...

  • Page 94: Slave Mode Transfer Examples

    Inter-Integrated Circuit (I2C) 15.2.10 Slave Mode Transfer Examples Slave mode transmits or receives data. 15.2.10.1 Slave Transmit Figure 15-7. Slave Mode Write Operation Flow Chart Begin TX FIFO empty? Disable Fixed Function I2C block Error Transmitting one byte Select Slave data complete? mode Enable...
  • Page 95 Inter-Integrated Circuit (I2C) 15.2.10.2 Slave Receive Figure 15-8. Slave Mode Read Operation Flow Chart Begin Disable Fixed Function I2C block RX FIFO full? Select Slave mode (stretch) Error Receiving one byte Enable data complete? RX FIFO Enable Fixed Function I2C block Send Data transfer complete?

  • Page 96: Ez Slave Mode Transfer Example

    Inter-Integrated Circuit (I2C) 15.2.11 EZ Slave Mode Transfer Example The EZ Slave mode transmits or receives data. 15.2.11.1 EZ Slave Transmit Figure 15-9. EZI2C Slave Mode Write Operation Flow Chart Begin Disable Fixed Function I2C block EZ buffer empty? Select Slave mode Error Transmitting one byte...
  • Page 97 Inter-Integrated Circuit (I2C) 15.2.11.2 EZ Slave Receive Figure 15-10. EZI2C Slave Mode Read Operation Flow Chart Begin Receiving one byte EZ address complete? Disable Fixed (stretch) Function I2C block Address ACK’ed or NACK Begin NACK’ed? Select Slave mode EZ buffer full Select EZ mode...

  • Page 98: Multi-Master Mode Transfer Example

    Inter-Integrated Circuit (I2C) 15.2.12 Multi-Master Mode Transfer Example In multi-master mode, data can be transferred with the slave mode enabled or not enabled. 15.2.12.1 Multi-Master - Slave Not Enabled Figure 15-11. Multi-Master, Slave Not Enabled Flow Chart B e g in D is a b le F ixe d F u n c tio n I2C b lo ck S e le ct M a ste r...
  • Page 99 Inter-Integrated Circuit (I2C) 15.2.12.2 Multi-Master - Slave Enabled Figure 15-12. Multi-Master, Slave Enabled Flow Chart B eg in D isab le F ixed F u nctio n I2C b lock S elect M a ster a nd S lave m od e T ran sm issio n (stretch ) E rror...
  • Page 100 Inter-Integrated Circuit (I2C) PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 101: 16. Timer, Counter, And Pwm

    16. Timer, Counter, and PWM ® The Timer, Counter, and Pulse Width Modulator (TCPWM) block in PSoC 4 implements the 16-bit timer, counter, pulse width modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadra- ture signals.

  • Page 102: Enabling And Disabling Counter In Tcpwm Block

    Timer, Counter, and PWM The block has these interfaces: ■ Bus interface: Connects the block to the CPU subsystem. ■ I/O signal interface: Connects input triggers (such as reload, start, stop, count, and capture) and output signals (such as overflow (OV), underflow (UN), and capture/compare (CC)) to dedicated GPIOs. ■...

  • Page 103: Events Based On Trigger Inputs

    Timer, Counter, and PWM 16.2.3 Events Based on Trigger Inputs These are the events triggered by hardware or software. ■ Reload ■ Start ■ Stop ■ Count ■ Capture/switch Hardware triggers can be level signal, rising edge, falling edge, or both edges. Figure 16-2 shows the selection of edge detec- tion type for any event trigger signal.

  • Page 104: Output Signals

    Timer, Counter, and PWM 16.2.4 Output Signals The TCPWM block generates several output signals, as shown in Figure 16-3. Figure 16-3. TCPWM Output Signals Interrupt Underflow TCPWM block Overflow Capture / Compare line_out line_compl_out 16.2.4.1 Signals upon Trigger Conditions ■ Counter generates an internal overflow (OV) condition when counting up and the count register reaches the period value.

  • Page 105: Power Modes

    Timer, Counter, and PWM 16.2.4.3 Outputs The TCPWM has two outputs, line_out and line_compl_out (complementary of line_out). Note that the OV, UN, and CC con- ditions can be used to drive line_out and line_compl_out if needed, by configuring the TCPWM_CNT_TR_CTRL2 register (Table 16-3).

  • Page 106: Modes Of Operation

    Timer, Counter, and PWM 16.3 Modes of Operation The counter block can function in six operational modes, as shown in Table 16-5. The MODE [26:24] field of the counter con- trol register (TCPWM_CNTx_CTRL) configures the counter in the specific operational mode. Table 16-5.

  • Page 107: Timer Mode

    Timer, Counter, and PWM 16.3.1 Timer Mode The timer mode is commonly used to measure the time of occurrence of an event or to measure the time difference between two events. 16.3.1.1 Block Diagram Figure 16-4. Timer Mode Block Diagram Reload PERIOD Start...
  • Page 108 Timer, Counter, and PWM Figure 16-5. Timing Diagram for Timer in Multiple Counting Modes Timer, down counting mode counter_clock Period 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFE 0xFFFE 0xFFFE 0xFFFD 0x0003 0xFFFD Counter 0xFFFC 0x0002 0xFFFC 0x0001 0x0001 0x0000 Timer, up counting mode counter_clock 0xFFFF Period...
  • Page 109 Timer, Counter, and PWM Timer, up/down counting mode 0 counter_clock 0xFFFF Period 0xFFFF 0xFFFF 0xFFFF 0xFFFE 0xFFFE 0xFFFE 0x0003 0xFFFE 0x0003 Counter 0x0002 0xFFFE 0x0002 0x0001 0x0001 0x0001 0x0000 Timer, up/down counting mode 1 counter_clock 0xFFFF Period 0xFFFF 0xFFFF 0xFFFF 0xFFFE 0xFFFE 0xFFFE...

  • Page 110: Capture Mode

    Timer, Counter, and PWM 16.3.2 Capture Mode In the capture mode, the counter value can be captured at any time either through a firmware write to command register (TCPWM_CMD) or a capture trigger input. This mode is used for period and pulse width measurement. 16.3.2.1 Block Diagram Figure 16-6.
  • Page 111 Timer, Counter, and PWM In the figure, observe that: ■ The period register contains the maximum count value. ■ Internal overflow (OV) and TC conditions are generated when the counter reaches the period value. ■ A capture event is only possible at the edges or through software. Use trigger control register 1 to configure the edge detection.

  • Page 112: Quadrature Decoder Mode

    Timer, Counter, and PWM 16.3.3 Quadrature Decoder Mode Quadrature decoders are used to determine speed and position of a rotary device (such as servo motors, volume control wheels, and PC mice). The quadrature encoder signals are used as phiA and phiB inputs to the decoder. 16.3.3.1 Block Diagram Figure 16-8.
  • Page 113 Timer, Counter, and PWM Figure 16-9. Timing Diagram for Quadrature Mode, X1 Encoding Quadrature, X1 encoding counter_clock index/reload event phiA phiB Period 0x8000 counter 0x8002 0x8001 0x8003 0xFFFF 0x7FFF 0x8000 0x8000 capture 0xFFFF buffer capture The quadrature phases are detected on the counter_clock. Within a single counter_clock period, the phases should not change value more than once.
  • Page 114 Timer, Counter, and PWM Figure 16-10. Timing Diagram for Quadrature Mode, X2 and X4 Encoding Quadrature, X2 encoding counter_clock index/reload event phiA phiB Period counter Quadrature, X4 encoding counter_clock index/reload event phiA phiB Period counter 9 10 11 11 10 9 16.3.3.3 Configuring Counter for Quadrature Mode The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows.

  • Page 115: Pulse Width Modulation Mode

    Timer, Counter, and PWM 16.3.4 Pulse Width Modulation Mode The PWM mode is also called the Digital Comparator mode. The comparison output is a PWM signal whose period depends on the period register value and duty cycle depends on the compare and period register values. PWM period = (period value/counter clock frequency) in left- and right-aligned modes PWM period = (2 ×...
  • Page 116 Timer, Counter, and PWM Figure 16-12. Timing Diagram for Center Aligned PWM PWM center aligned buffered counter_clock SW update of buffers new period value B, new compare value N reload event period buffer period compare buffer compare Switch at TC condition Counter line_out Figure 16-12...
  • Page 117 Timer, Counter, and PWM Figure 16-13. Timing Diagram for Center Aligned PWM (software switch event PWM, center aligned, buffered (software switch event) counter_clock Switch event reload event period buffer period compare buffer compare Switch at TC condition Counter line_out 16.3.4.3 Other Configurations ■...
  • Page 118 Timer, Counter, and PWM A kill event can be programmed to be asynchronous or synchronous, as shown in Table 16-8. Table 16-8. Field Setting for Synchronous/Asynchronous Kill PWM_SYNC_KILL Field Comments An asynchronous kill event lasts as long as it is present. This event requires pass through mode. A synchronous kill event disables the output lines until the next TC event.

  • Page 119: Pulse Width Modulation With Dead Time Mode

    Timer, Counter, and PWM 16.3.5 Pulse Width Modulation with Dead Time Mode Dead time is used to delay the transitions of both ‘line_out’ and ‘line_out_compl’ signals. It separates the transition edges of these two signals by a specified time interval. Two complementary output lines 'dt_line' and 'dt_line_compl' are derived from these two lines.
  • Page 120 Timer, Counter, and PWM Figure 16-15. Timing Diagram for PWM, with and without Dead Time PWM, Deadtime insertion line_out Dead time duration : 0 dt_line dt_line_compl Deadtime duration : dt_line dt_line_compl 16.3.5.3 Configuring Counter for PWM with Dead Time Mode The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows: 1.

  • Page 121: Pulse Width Modulation Pseudo-Random Mode

    Timer, Counter, and PWM 16.3.6 Pulse Width Modulation Pseudo-Random Mode This mode uses the linear feedback shift register (LFSR). LFSR is a shift register whose input bit is a linear function of its pre- vious state. 16.3.6.1 Block Diagram Figure 16-16. PWM-PR Mode Block Diagram BUFFER PERIOD reload PERIOD...
  • Page 122 Timer, Counter, and PWM The following steps describe the process: ■ At TC, a switch/capture event conditionally switches the compare and period register pairs (based on the ■ The PWM output line, ‘line_out’, is driven with '1' when AUTO_RELOAD_CC and AUTO_RELOAD_PERIOD the lower 15-bit value of the counter register is smaller fields of the counter control register).

  • Page 123: Tcpwm Registers

    Timer, Counter, and PWM 16.4 TCPWM Registers Table 16-9. List of TCPWM Registers Register Comment Features TCPWM_CTRL TCPWM control register Enables the counter block TCPWM_CMD TCPWM command register Generates software events TCPWM_INTR_CAUSE TCPWM counter interrupt cause register Determines the source of the combined interrupt signal Configures counter mode, encoding modes, one shot mode, TCPWM_CNT_CTRL Counter control register...
  • Page 124 Timer, Counter, and PWM PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 125: Section F: Analog System

    Section F: Analog System This section encompasses the following chapter: ■ CapSense chapter on page 127 Top Level Architecture Analog System Block Diagram Peripheral Interconnect (MMIO) CapSense (2 IDACs and 1 Comparator available for general purpose use) High Speed I/O Matrix GPIO Pins PSoC 4000 Family: PSoC 4 Architecture TRM, Document No.
  • Page 126 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 127: 17. Capsense

    17. CapSense ® ® PSoC 4 uses a capacitive touch sensing method known as CapSense Sigma Delta (CSD). The CapSense Sigma Delta touch sensing method provides the industry's best-in-class signal-to-noise ratio (SNR). CSD is a combination of hardware and firmware techniques. This chapter explains how the CSD hardware is implemented in PSoC 4. See the PSoC 4 CapSense Design Guide for more details on the basics of CSD operation, available CapSense design tools,...

  • Page 128: How It Works

    CapSense 17.3 How It Works Figure 17-2. Raw Count Versus Time With CSD, each GPIO has a switched capacitance circuit that converts the sensor capacitance into an equivalent cur- rent. An analog multiplexer then selects one of the currents and feeds it into the current-to-digital converter. The current- to-digital converter is similar to a sigma delta ADC.

  • Page 129: Capsense Csd Sensing

    CapSense 17.4 CapSense CSD Sensing Figure 17-3 shows the block diagram of the PSoC 4 CapSense hardware. Figure 17-3. PSoC 4 CapSense CSD Sensing AMUXBUS A forms an analog multiplexer for the sensors current to digital converter IO cells configured as switched capacitance circuits for capacitance to current conversion 7 bit IDAC...
  • Page 130 CapSense Figure 17-5. Sourcing Current to AMUXBUS A AMUXBUS A AMUXBUS A Two non-overlapping, out of phase clocks of frequency F (see Figure 17-3) control the switches SW and SW . The contin- uous switching of SW and SW forms an equivalent resistance R , as Figure 17-5 shows.

  • Page 131: Capsense Clock Generator

    CapSense Figure 17-7. Sinking Current From AMUXBUS A AMUXBUS A AMUXBUS A Figure 17-8. Voltage Across Sensor Capacitance However, the final switching clock frequency depends on the CapSense clock generator. It has the following output options: Open Closed ■ Direct: Uses the output of programmable clock dividers (1.2 V) directly.
  • Page 132 CapSense sinking digital-to-analog converters (IDACs), as Figure 17-3 COMP ------------------------ - C --------------- - shows. Rawcount – Equation 17-9 The sigma delta modulator controls the current of the 8-bit IDAC in an on/off manner. This IDAC is known as the modu- Raw count in IDAC sinking mode is given by equation 16-10.

  • Page 133: Capsense Csd Shielding

    CapSense 17.5 CapSense CSD Shielding PSoC 4 CapSense supports shield electrodes for waterproofing and proximity sensing. For waterproofing, the shield elec- trode is always kept at the same potential as the sensors. PSoC 4 CapSense has a shielding circuit that drives the shield electrode with a replica of the sensor switching signal (see GPIO Cell Capacitance to Current Converter on page 129) to nul-...

  • Page 134: Cmod Precharge

    CapSense Figure 17-10. Shield Driving Using GPIO Precharge GPIO cell switch SH_TANK Reference Shield Tank Comparator Capacitor Channel 2 sensing line SH_TANK GPIO Pin GPIO Cell (1.2V) Shield electrode capacitance AMUXBUS B SHIELD (Always kept at V Shield Electrode This GPIO cell precharge capability is available only on a select which capacitor is connected to the reference fixed C pin.

  • Page 135: General-Purpose Resources: Idacs And Comparator

    CapSense 17.6 General-Purpose Resources: IDACs and Comparator If the CapSense block is not used for touch sensing, the sense comparator and the two IDACs can be used as general-pur- pose analog blocks. You can use AMUXBUS A to connect any CSD-supported GPIO to the non-inverting input of the sense comparator. The inverting input is connected to the 1.2-V V (see Figure...
  • Page 136 CapSense PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 137: Section G: Program And Debug

    Section G: Program and Debug This section encompasses the following chapters: ■ Program and Debug Interface chapter on page 139 ■ Nonvolatile Memory Programming chapter on page 147 Top Level Architecture Program and Debug Block Diagram PROGRAM AND DEBUG Program Debug and Trace PSoC 4000 Family: PSoC 4 Architecture TRM, Document No.
  • Page 138 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 139: 18. Program And Debug Interface

    4 Program and Debug interface provides a communication gateway for an external device to perform program- ming or debugging. The external device can be a Cypress-supplied programmer and debugger, or a third-party device that supports programming and debugging. The serial wire debug (SWD) interface is used as the communication protocol between the external device and PSoC 4.

  • Page 140: Serial Wire Debug (Swd) Interface

    Program and Debug Interface 18.3 Serial Wire Debug (SWD) Interface PSoC 4’s Cortex-M0 supports programming and debugging through the SWD interface. The SWD protocol is a packet-based serial transaction protocol. At the pin level, it uses a single bidirectional data signal (SWDIO) and a unidirectional clock signal (SWDCK).

  • Page 141: Swd Timing Details

    Program and Debug Interface b. The data parity bit indicates the parity of the data 18.3.2 ACK Details read or written. It is an even parity; this means when The acknowledge (ACK) bit-field is used to communicate XORed with the data bits, the result will be 0. the status of the previous transfer.

  • Page 142: Cortex-M0 Debug And Access Port (Dap)

    Program and Debug Interface 18.4 Cortex-M0 Debug and Access Port (DAP) The Cortex-M0 program and debug interface includes a Debug Port (DP) and an Access Port (AP), which combine to form the DAP. The debug port implements the state machine for the SWD interface protocol that enables communication with the host device.

  • Page 143: Programming The Psoc 4 Device

    Program and Debug Interface 18.5 Programming the PSoC 4 return //check (time_elapsed >= 2 ms) FAIL; for acquire time out Device return //confirm SWD ID (ID != CM0_ID) FAIL; PSoC 4 is programmed using the following sequence. of Cortex-M0 CPU. (0x0BB11477) 1.

  • Page 144: Psoc 4 Swd Debug Interface

    Program and Debug Interface 18.6 PSoC 4 SWD Debug the BKPT instruction in the Cortex-M0. The BPU has two types of registers. Interface ■ The breakpoint control register (CM0_BP_CTRL) is used to enable the BPU and store the number of hardware Cortex-M0 DAP debugging features are classified into two breakpoints supported by the debug system (four for types: invasive debugging and noninvasive debugging.

  • Page 145: Registers

    Program and Debug Interface rect CM0 DAP SWDID is read from the target device. For as stepping, halting, breakpoint configuration, and watch- the debug transactions to occur on the SWD interface, the point configuration are carried out by writing to the appropri- corresponding pins should not be used for any other pur- ate registers in the debug system.
  • Page 146 Program and Debug Interface PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...

  • Page 147: 19. Nonvolatile Memory Programming

    Cypress-supplied programmers and other third-party programmers can use these functions to program the PSoC 4 device with the data in an application hex file. They can also be used to perform bootload operations where the CPU will update a portion of the flash memory.

  • Page 148: System Call Implementation

    Nonvolatile Memory Programming 19.3 System Call Implementation ory. When a non-blocking function is called from SRAM, the SPC timer triggers its interrupt when each of the sub-opera- tions in a write or program operation is complete. Call the A system call consists of the following items: Resume Non-Blocking function from the SPC interrupt ser- ■...

  • Page 149: System Calls

    Nonvolatile Memory Programming maximum execution time is one second. If these two bits YY indicates the reason for failure. See Table 19-1 are not cleared after one second, the operation should the complete list of status codes and their description. be considered a failure and aborted without executing 5.

  • Page 150: Configure Clock

    Nonvolatile Memory Programming Address Value to be Written Description Bits [31:16] 0x0000 Not used CPUSS_SYSREQ register Bits [15:0] 0x0000 Silicon ID opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Return Address Return Value Description CPUSS_SYSARG register Bits [7:0] Silicon ID Lo See the device datasheet for Silicon ID values for different...

  • Page 151: Load Flash Bytes

    Nonvolatile Memory Programming 19.5.3 Load Flash Bytes This function loads the page latch buffer with data to be programmed into a row of flash. The load size can range from 1-byte to the maximum number of bytes in a flash row, which is 64 bytes. Data is loaded into the page latch buffer starting at the location specified by the “Byte Addr”...

  • Page 152: Write Row

    Nonvolatile Memory Programming 19.5.4 Write Row This function erases and then programs the addressed row of flash with the data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped. The parameters for this function are stored in SRAM. The start address of the stored parameters is written to the CPUSS_SYSARG register.

  • Page 153: Erase All

    Nonvolatile Memory Programming Address Value to be Written Description CPUSS_SYSARG register 32-bit word-aligned address of the SRAM that Bits [31:0] 32’hYY stores the first function parameter (key1) CPUSS_SYSREQ register Bits [15:0] 0x0006 Program Row opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Return Address Return Value...

  • Page 154: Write Protection

    Nonvolatile Memory Programming performing a checksum only on one row of flash, the flash row number is passed as a parameter. Bytes 2 and 3 of the param- eters select whether the checksum is performed on the whole flash memory or a row of user code flash. Parameters Address Value to be Written...

  • Page 155: Non-Blocking Write Row

    Nonvolatile Memory Programming Parameters Address Value to be Written Description CPUSS_SYSARG register Bits [7:0] 0xB6 Key1 Bits [15:8] 0xE0 Key2 Parameter applicable only for Flash Macro 0 0x01 – OPEN mode Bits [23:16] Device Protection Byte 0x02 – PROTECTED mode 0x04 –...

  • Page 156: Non-Blocking Program Row

    Nonvolatile Memory Programming Parameters Address Value to be Written Description SRAM Address 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xDA Key2 Row number to write Bits [31:16] Row ID 0x0000 – Row 0 CPUSS_SYSARG register 32-bit word-aligned address of the SRAM that stores the first function Bits [31:0] 32’hYY...

  • Page 157: Resume Non-Blocking

    Nonvolatile Memory Programming Address Value to be Written Description 32-bit word-aligned address of the SRAM that stores the first Bits [31:0] 32’hYY function parameter (key1) CPUSS_SYSREQ register Bits [15:0] 0x0008 Non-Blocking Program Row opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Return Address Return Value...

  • Page 158: System Call Status

    Nonvolatile Memory Programming 19.6 System Call Status At the end of every system call, a status code is written over the arguments in the CPUSS_SYSARG register. A success sta- tus is 0xAXXXXXXX, where X indicates don’t care values or return data in the case of the system calls that return a value. A failure status is indicated by 0xF00000XX, where XX is the failure code.

  • Page 159: Non-Blocking System Call Pseudo Code

    Nonvolatile Memory Programming 19.7 Non-Blocking System Call Pseudo Code This section contains pseudo code to demonstrate how to set up a non-blocking system call and execute code out of SRAM during the flash programming operations. #define REG(addr) (*((volatile uint32 *) (addr))) #define CM0_ISER_REG REG( 0xE000E100 ) #define CPUSS_CONFIG_REG...
  • Page 160 Nonvolatile Memory Programming //Write load size param (64 bytes) to SRAM REG( 0x20000004 ) = 0x0000003F; for(i = 0; i < ROW_SIZE/4; i += 1) REG( 0x20000008 + i*4 ) = 0xDADADADA; /*Write the address of the key1 param to CPUSS_SYSARG reg*/ CPUSS_SYSARG_REG = 0x20000000;...

  • Page 161: Glossary

    Glossary The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual. accumulator In a CPU, a register in which intermediate results are stored. Without an accumulator, it is neces- sary to write the result of each calculation (addition, subtraction, shift, and so on.) to main mem- ory and read them back.
  • Page 162 Index See Boolean Algebra . API (Application Pro- A series of software routines that comprise an interface between a computer application and gramming Interface) lower-level services and functions (for example, user modules and libraries). APIs serve as build- ing blocks for programmers that create software applications. array An array, also known as a vector or list, is one of the simplest data structures in computer pro- gramming.
  • Page 163 Index A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8 bits is called a byte. Because the PSoC's M8CP is an 8-bit microcontroller, the PSoC devices's native data chunk size is a byte.
  • Page 164 Index capture To extract information automatically through the use of software or hardware, as opposed to hand-entering of data into a computer file. chaining Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another.
  • Page 165 Index data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. data stream A sequence of digitally encoded signals used to represent information in transmission.
  • Page 166 Index falling edge A transition from a logic 1 to a logic 0. Also known as a negative edge. feedback The return of a portion of the output, or processed portion of the output, of a (usually active) device to the input. filter A device or process by which certain frequency components of a signal are attenuated.
  • Page 167 Index hardware A comprehensive term for all of the physical parts of a computer or embedded system, as distin- guished from the data it contains or operates on, and the software that provides instructions for the hardware to accomplish tasks. hardware reset A reset that is caused by a circuit, such as a POR, watchdog reset, or external reset.
  • Page 168 Index impedance 1. The resistance to the flow of current caused by resistive, capacitive, or inductive devices in a circuit. 2. The total passive opposition offered to the flow of electric current. Note the impedance is determined by the particular combination of resistance, inductive reactance, and capacitive reactance in a given circuit.
  • Page 169 Index Linear Feedback Shift A shift register whose data input is generated as an XOR of two or more elements in the register Register (LFSR) chain. load The electrical demand of a process expressed as power (watts), current (amps), or resistance (ohms).
  • Page 170 Index mode A distinct method of operation for software or hardware. For example, the Digital PSoC block may be in either counter mode or timer mode. modulation A range of techniques for encoding information on a carrier signal, typically a sine-wave signal. A device that performs modulation is known as a modulator.
  • Page 171 ® PSoC Cypress’s Programmable System-on-Chip (PSoC ) devices. PSoC blocks See analog blocks and digital blocks . PSoC Creator™ The software for Cypress’s next generation Programmable System-on-Chip technology. PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...
  • Page 172 Index pulse A rapid change in some characteristic of a signal (for example, phase or frequency), from a base- line value to a higher or lower value, followed by a rapid return to the baseline value. pulse width modulator An output in the form of duty cycle which varies as a function of the applied measure. (PWM) An acronym for random access memory.
  • Page 173 Index To force a bit/register to a value of logic 1. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift The movement of each bit in a word one position to either the left or right. For example, if the hex value 0x24 is shifted one place to the left, it becomes 0x48.
  • Page 174 Index sticky A bit in a register that maintains its value past the time of the event that caused its transition, has passed. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block.
  • Page 175 Index user The person using the PSoC device and reading this manual. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map.
  • Page 176 Index PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D...
  • Page 177 Index watchdog timer ......73 active mode PSoC ........70 glossary .
  • Page 178 Index power on reset ....... . 77 program and debug PSoC .

This manual is also suitable for:

Psoc 4

Table of Contents