Teledyne SP Devices ADQ7DC Manual
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Teledyne SP Devices ADQ7DC Manual

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Manual ADQ7DC
This manual describes how to get the full potential out of Teledyne SP Devices'
digitizer ADQ7DC. The manual includes these steps:
•
Set up the analog front-end
•
Master the triggers
•
Control the acquisition
•
Manage the sampling clock
•
Understanding data transfer to host PC
•
Using GPIO
Teledyne Signal Processing Devices Sweden AB | Teknikringen 6, SE-583 30 Linköping, Sweden | www.spdevices.com
Regional sales offices | www.spdevices.com/contact
ADQ7DC Manual
16-1796 PC2 2019-02-01
1(50)

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Summary of Contents for Teledyne SP Devices ADQ7DC

  • Page 1 ADQ7DC Manual 16-1796 PC2 2019-02-01 1(50) Manual ADQ7DC This manual describes how to get the full potential out of Teledyne SP Devices’ digitizer ADQ7DC. The manual includes these steps: • Set up the analog front-end • Master the triggers •...

  • Page 2: Table Of Contents

    Fundamental design properties ..................5 1.2.1 Data format ..........................6 1.2.2 Calibration............................ 6 1.2.3 Data acquisition nomenclature ....................6 1.2.4 ADQ7DC sampling clock frequency .................... 7 1.2.5 System clocks..........................7 1.2.6 Analog signal range ........................7 SETTING UP THE ANALOG FRONT-END ..............9 AFE block diagram......................
  • Page 3 ADQ7DC Manual 16-1796 PC2 2019-02-01 3(50) 4.11.3Trigger event indicator ....................... 27 4.11.4Triggering external equipment with internal trigger..............27 4.11.5Distributing level trigger ......................29 CLOCK......................... 30 Clock domains ......................30 Flexible clock network....................30 Front panel SMA connector ..................31 Internal clock reference....................31 External clock reference ....................
  • Page 4 ADQ7DC Manual 16-1796 PC2 2019-02-01 4(50) 19-2233 PC2 2019-02-01 4(50)

  • Page 5: Introduction

    5 GSPS per channel. The A/D converters can be further interleaved to get 10 GSPS. Digital calibration of gain and offset. Teledyne SP Devices’ proprietary technologies for signal quality enhancement; ADX for SFDR in radio systems and DBS for baseline stability in pulse data systems.

  • Page 6: Data Format

    The 2 LSBs may not be zero in the data output from the ADQ7DC. Calibration and other computations in the FPGA may result in fractional result. This is not rounded to 14 bits in order to avoid adding com- putational noise.

  • Page 7: Adq7Dc Sampling Clock Frequency

    Section 5.9. The ADQ7DC is available in two different speed modes, 5 GSPS dual channel and 10 GSPS single channel. Both modes are supported by the hardware and included with the ADQ7DC. The firmware of the FPGA has to be changed when switching mode. This may require a re-start of parts of the system.
  • Page 8 ADQ7DC Manual 16-1796 PC2 2019-02-01 8(50) The maximum digital code 2^15 represents an analog signal with a level ACTUAL_ANALOG_RANGE / 2 at the input. A specific analog signal will then be represented by the following digital ANALOG_LEVEL code: DIGITAL_CODE_LEVEL = ANALOG_LEVEL / ( ACTUAL_ANALOG_RANGE / 2 ) * 2^15...

  • Page 9: Setting Up The Analog Front-End

    Figure 2: ADQ7 AFE control. The ADQ7DC can operate with two channels at 5 GSPS or one channel at 10 GSPS. To change mode of operation, the single or dual channel firmware has to be activated by using the ADQ7 Updater tool For more information, see [6].

  • Page 10: Adjusting The Digital Gain And Offset

    ADQ7DC Manual 16-1796 PC2 2019-02-01 10(50) cal position for the A/D converter. In this way, the full 14 bits can be used for representing the unipolar pulse. The DC-offset is set with the command SetAdjustableBias The DC-offset is set in digital codes...

  • Page 11: Signal Quality Enhancement

    ADQ7DC Manual 16-1796 PC2 2019-02-01 11(50) SIGNAL QUALITY ENHANCEMENT 3.1 Digital Baseline Stabilizer The Digital Baseline Stabilizer, DBS, is designed for pulse data measurement where high accuracy rel- ative a known baseline is required. The key features of DBS are: •...

  • Page 12: Trigger

    ADQ7DC Manual 16-1796 PC2 2019-02-01 12(50) TRIGGER 4.1 Trigger block diagram The digitizer can be triggered in various ways with a number of different internal and external trigger sources. Selected events in the trigger module can also be output to trigger external equipment. The...

  • Page 13: Position Of The Trigger In The Data

    ADQ7DC Manual 16-1796 PC2 2019-02-01 13(50) 4.2 Position of the trigger in the data The trigger position relative to the data record is controlled by the parameters pretrigger and trigger delay. The pretrigger buffer enables capturing data prior to the trigger event, Figure 4.

  • Page 14: Timestamp Reset

    Example 3: Assume an ADQ7DC sampling with a clock frequency at 5 GSPS. The pretrigger is set to 80 samples and the external trigger is used. The following parameters are returned:...
  • Page 15 ADQ7DC Manual 16-1796 PC2 2019-02-01 15(50) • Start the experiment and subtract the timing reference from each record as – TIME_STAMP TIME_STAMP_OF_RECORD TIME_STAMP_REFERENCE 3. The third method is to apply an external trigger to reset the timestamp reset, Figure 6. This method has the possibility to synchronize several boards to full precision of the external trigger.

  • Page 16: Blocking Triggers For Synchronization

    ADQ7DC Manual 16-1796 PC2 2019-02-01 16(50) 4.4 Blocking triggers for synchronization 4.4.1 Function overview In order to synchronize the acquisition to external equipment or to other ADQ digitizers, there is a mechanism for controlling the flow of triggers. The trigger blocking function allows the user to select...

  • Page 17: Block Triggers Once

    ADQ7DC Manual 16-1796 PC2 2019-02-01 17(50) '  $ ) *& !&  % !   + ,  % !   +,  % !   +,  % !   + , DESCRIPTION USER COMMAND The trigger blocker in window or gate mode allows triggers during a SetupTriggerBlocking 4.4.1 certain period. Example of rejected triggers outside the window.

  • Page 18: Trigger Jitter

    The RMS value of such a process is /sqrt(12). TRIGGER_CLOCK_PERIOD The highest resolution is achieved with an external trigger connected to the TRIG connector. ADQ7DC has a trigger clock at 20 GSPS, of 50 ps and a trigger jitter of TRIGGER_CLOCK_PERIOD 14 ps RMS (theoretical value), Section 4.5.4.

  • Page 19: Synchronous Trigger

    ADQ7DC Manual 16-1796 PC2 2019-02-01 19(50) 4.5.3 Synchronous trigger A synchronous trigger is phase locked to the clock of the digitizer. The trigger source needs access to the clock reference of the digitizer. There are three ways to achieve this synchronization: 1.

  • Page 20: External Trigger Inputs

    ADQ7DC Manual 16-1796 PC2 2019-02-01 20(50) DisArmTrigger (“software trigger”) SetTriggerMode ArmTrigger SWTrig 6. Read data and analyze the situation 4.7 External Trigger Inputs An external trigger is a dedicated signal on a dedicated input to the ADQ. There are several inputs for...

  • Page 21: External Trigger Sync Connector

    ADQ7DC Manual 16-1796 PC2 2019-02-01 21(50) 4.7.2 External trigger SYNC connector The block diagram for the SYNC input is shown in Figure 12 and related parameters are listed in Table 3. The user can control the SYNC function for adapting it to the system in the following ways: The input impedance can be set in 50 ...

  • Page 22: External Trigger In The Backplane

    4.8.1 PXIe interface There are an external trigger in the backplane of the PXIe version of ADQ7DC. The DSTAR signals are dedicated matched trigger lines from the system timing slot. To use these triggers, a dedicated timing generation board has to be used in the system timing slot. The TRIG bus is a general bus in the back- plane which can be used for triggering.

  • Page 23: Mtca.4 Interface

    ADQ7DC Manual 16-1796 PC2 2019-02-01 23(50) %  * +, - +, - !+ , !+ ,% !+ , % * * DESCRIPTION USER COMMAND Backplane Trigger bus and DSTAR connections Set direction for each port in the backplane SetDirectionPXI...

  • Page 24: Level Trigger

    ADQ7DC Manual 16-1796 PC2 2019-02-01 24(50) %  * -./  ./ -.0  .0 -.  . -.  . % * * DESCRIPTION USER COMMAND Backplane MLVDS bus Set direction for each port in the backplane SetDirectionMLVDS Output: Select output port for trigger output SetupTriggerOutput 4.11...

  • Page 25: Setting The Level Trigger Level

    ADQ7DC Manual 16-1796 PC2 2019-02-01 25(50)      )    * $ DESCRIPTION USER COMMAND When the signal passes the trigger level, a trigger event is generated and SetupLevelTrigger 4.9.1 the first record is captured.

  • Page 26: Internal Trigger

    ADQ7DC Manual 16-1796 PC2 2019-02-01 26(50)    DESCRIPTION USER COMMAND The level trigger has a hysteresis function to avoid false triggering on 4.9.3 noise. When the signal passes below the RESET_LEVEL_CODE, the ADQ may trigger again.

  • Page 27: 2Frame Sync Output On Sync Connector

    ADQ7DC Manual 16-1796 PC2 2019-02-01 27(50) 4.11.2 Frame sync output on SYNC connector The frame sync feature enables grouping of trigger signals into frames or blocks or lines. The name for this feature relate to the actual application. This function can, for example, be used in scanning three- dimensional measurements where a record is the first dimension, the trigger is the second and the frame sync is the third dimension.
  • Page 28 ADQ7DC Manual 16-1796 PC2 2019-02-01 28(50) ,    ,  ' ' /0  /&' ( $% *   *       " *   +,+- DESCRIPTION USER COMMAND Internal trigger generator SetInternalTriggerPeriod 4.10...

  • Page 29: 5Distributing Level Trigger

    ADQ7DC Manual 16-1796 PC2 2019-02-01 29(50) 4.11.5 Distributing level trigger Multiple boards may be triggered by a level trigger on one channel in one of the digitizers. This mode is intended for systems with a reference event on one channel that starts the acquisition on all channels.

  • Page 30: Clock

    ADQ7DC Manual 16-1796 PC2 2019-02-01 30(50) CLOCK 5.1 Clock domains Different parts of the digitizer system operate on different clocks. The core of the clocking system is the clock reference. This is the phase and frequency reference of the digitizer system. It is possible to use different clock reference sources to meet the requirements of different applications.

  • Page 31: Front Panel Sma Connector

    The digitizer supports its specified sample rate only. This sample rate can be tuned to allow phase locking to external equipment. To reduce the sample-rate, a sample skip function is available. Block diagrams of the clock network for ADQ7DC is given in Figure -( ( +./...

  • Page 32: Internal Clock Generator

    ADQ7DC Manual 16-1796 PC2 2019-02-01 32(50) The connector on the front panel accepts a clock reference from external equipment. The clock refer- ence quality is improved in a jitter cleaning circuitry. To match the tuning of the jitter cleaning circuitry the clock reference has to be 10 MHz.

  • Page 33: Gpio

    ADQ7DC Manual 16-1796 PC2 2019-02-01 33(50) GPIO The General Purpose Input and Output (GPIO) are digital signals available from the front panel of the digitizer. The user assigns a function to these pins, either in the firmware through the ADQ Develop- ment Kit or from software.

  • Page 34: Output

    ADQ7DC Manual 16-1796 PC2 2019-02-01 34(50) Example 3: Triggering the digitizer and an external device with GPIO 1. Connect a cable from the TRIG connector to the external device. (“external trigger”) /* This will activate the trigger module to listen to TRIG”...

  • Page 35: Dedicated Gpio Connector On Form Factor -Pcie Or -Pxie

    ADQ7DC Manual 16-1796 PC2 2019-02-01 35(50) 6.5 Dedicated GPIO connector on form factor –PCIe or –PXIe This section is only valid for ADQ7 hardware with options –PCIe or –PXIe. In addition to the GPIO functions of TRIG and SYNC signals there is a HD-DSUB connector with addi- tional GPIO connections.
  • Page 36 ADQ7DC Manual 16-1796 PC2 2019-02-01 36(50) GPDIC0_P LVDS input / clock GPIO0 Single-ended 3.3 V GPDIC0_N LVDS input / clock GPIO1 Single-ended 3.3 V GPDI1_P LVDS input GPIO2 Single-ended 3.3 V GPDI1_N LVDS input GPIO3 Single-ended 3.3 V GPDI2_P LVDS input GPIO4 Single-ended 3.3 V...

  • Page 37: Acquisition Control

    ADQ7DC Manual 16-1796 PC2 2019-02-01 37(50) ACQUISITION CONTROL The acquisition control consists of two partly independent parts; • acquisition of data in a record • transfer to host PC. Figure 28 shows the flow of data through acquisition and data transfer.

  • Page 38: Acquisition Modes

    FIFO. Figure 29: Acquisition memory. ACQUISITION MODE RECORD SIZE –2A –4A –2C –4C –1X –2X ACQUISITION MODE RECORD SIZE ADQ7DC 5 GSPS ADQ7DC 10 GSPS Header < 256 samples > 5.9 % > 11 % Header > 256 samples <...

  • Page 39: Triggered Streaming Acquisition

    ADQ7DC Manual 16-1796 PC2 2019-02-01 39(50) • Use sample skip to reduce the data rate. • Use decimation to reduce data rate. Decimation is sample skip combined with digital filtering to reduce noise and potential aliasing. This method requires the option –FW4DDC.

  • Page 40: Data Transfer Modes

    ADQ7DC Manual 16-1796 PC2 2019-02-01 40(50) 7.4 Data transfer modes The data transfer can be set up in two main ways: • Event-driven streaming, see Section 7.4.1. • User-scheduled multi-record, see Section 7.4.2. 7.4.1 Streaming data transfer mode The streaming mode is preferred for high-performance event-driven data transfer. This is the main...
  • Page 41 ADQ7DC Manual 16-1796 PC2 2019-02-01 41(50) 4!'  4   #*+    223 %    %   " '+ 8     8     /!  $ , - .+...

  • Page 42: User-Scheduled Data Transfer Mode

    ADQ7DC Manual 16-1796 PC2 2019-02-01 42(50)   '    '  !   '  0   '     '  +     ...
  • Page 43 ADQ7DC Manual 16-1796 PC2 2019-02-01 43(50) 2#' 3 2# # # )   " 001 %  # # %" # "" !  2) # # !  2) # # -"  $ * + , * + ##  " #"  "  ...

  • Page 44: Transfer Buffers

    ADQ7DC Manual 16-1796 PC2 2019-02-01 44(50) '  *  '  *  $ '  *  7 '  *       Figure 36: Timing of user-scheduled data transfer.

  • Page 45: Record Header

    ADQ7DC Manual 16-1796 PC2 2019-02-01 45(50) .    . +  "/ 0 "2 1  1     .    .    . +  "/ 0 "2 1  1  1  2345       .

  • Page 46: User Id

    ADQ7DC Manual 16-1796 PC2 2019-02-01 46(50) FIFO fill factor is indicated. This is useful when tuning a data-driven process to avoid FIFO overflow and still get maximum efficiency from the experiment. For very long records, the maximum fill factor during the record is given.

  • Page 47: Over-Range And Under-Range

    ADQ7DC Manual 16-1796 PC2 2019-02-01 47(50) 7.7 Over-range and under-range The over/under-range bit in the header indicates that over-range or under-range occurred at one or several samples within the record and at any stage in the signal chain. The result of the over-range is...

  • Page 48: Host Pc Connection

    ADQ7DC Manual 16-1796 PC2 2019-02-01 48(50) HOST PC CONNECTION The host PC connection is either USB or PCI Express. From the programmers’ perspective, there is no difference which interface to use. It only matters when the data rate to the host PC is critical.

  • Page 49: References

    ADQ7DC Manual 16-1796 PC2 2019-02-01 49(50) REFERENCES 16-1692 ADQ7DC Datasheet 14-1351 ADQAPI Reference guide 08-0214 ADQAPI User guide 18-2104 ADQ7-FWATD application note 17-1957 ADQ7-FWATD user guide 18-2059 ADQ7 updater user guide 18-2118 FWPD application note 18-2132 ADQ7-FWPD user guide 16-1790 Application note: Connecting a detector to a 14-bit digitizer...
  • Page 50 Teledyne SP Devices. In no event shall Teledyne SP Devices be liable for any damages arising out of or related to this docu- ment or the information contained in it.

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