Schematic Diagram Of The External Cs1/Cs2 Memory Interface - Motorola 56F8346 User Manual

This memory bank will operate with zero wait state access while the 56F8346 is running at
60MHz and can be disabled by removing the jumpers at JG6.
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
MOTOROLA
Freescale Semiconductor, Inc.
56F8346
A0-A16
D0-D15
RD
WR
DS/CS1
PD0/CS2
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
Technical Summary
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Program and Data Memory
GS72116
A0-A16
DQ0-DQ15
OE
WE
JG6
2 LB
1
HB
3 4
CE
2-5