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Supermicro X10DRG-O+-CPU User Manual

Supermicro X10DRG-O+-CPU User Manual

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X10DRG-O+-CPU
X10DRG-OT+-CPU
X10DRG-O-PCIE
USER'S MANUAL
Revision 1.1

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Summary of Contents for Supermicro X10DRG-O+-CPU

  • Page 1 X10DRG-O+-CPU X10DRG-OT+-CPU X10DRG-O-PCIE USER’S MANUAL Revision 1.1...
  • Page 2 For more information, go to www.P65Warnings.ca.gov. The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment, nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication devices or other critical systems whose failure to perform be reasonably expected to result in signifi...
  • Page 3 With the PCH C612 built in, the X10DRG-O+-CPU/X10DRG-OT+-CPU supports Intel® Node Manager 3.0 and Management Engine (ME) technologies. This motherboard is optimized for High-Performance Computing (HPC) or VDI platforms.
  • Page 4 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Conventions Used in the Manual Pay special attention to the following symbols for proper system installation: Warning: Important information given to ensure proper system installation or to prevent damage to the components or injury to yourself; Note: Additional information given to differentiate between models or instructions provided for proper system setup.
  • Page 5 Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Website: www.supermicro.com Europe Address: Super Micro Computer B.V. Het Sterrenbeeld 28, 5215 ML...

  • Page 6: Table Of Contents

    X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Table of Contents Preface Chapter 1 Overview Overview ......................1-1 Processor and Chipset Overview..............1-14 Special Features ................... 1-15 System Health Monitoring ................1-15 ACPI Features ....................1-16 Power Supply ....................1-16 Advanced Power Management ..............1-17 Intel ®...
  • Page 7 Table of Contents Power LED ....................2-22 HDD/UID LED ..................2-23 NIC1/NIC2 LED Indicators ............... 2-23 Overheat (OH)/Fan Fail/UID LED ............2-24 Power Fail LED ..................2-24 Reset Button ................... 2-25 Power Button ................... 2-25 Connecting Cables ..................2-26 Power Connectors ................... 2-26 Fan Headers .....................
  • Page 8 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Chapter 4 BIOS Introduction ...................... 4-1 Main Setup ...................... 4-2 Advanced Setup Confi gurations..............4-4 Event Logs ....................4-36 IPMI ....................... 4-38 Security Settings ................... 4-41 Boot Settings ....................4-44 Save & Exit ....................4-47 Appendix A BIOS POST Error Beep Codes BIOS Error Beep Codes .....................

  • Page 9: Chapter 1 Overview

    Checklist Congratulations on purchasing your system board from an acknowledged leader in the industry. Supermicro boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. The X10DRG-O(T)+-CPU/X10DRG-O-PCIE board was designed to be used with a Supermicro-proprietary chassis as an integrated server platform.
  • Page 10 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual X10DRG-O+-CPU/X10DRG-OT+-CPU Image Note: All graphics shown in this manual were based upon the latest PCB revision available at the time of publishing of the manual. The motherboard you've received may or may not look exactly the same as the graphics...
  • Page 11 Chapter 1: Overview X10DRG-O+-CPU/X10DRG-OT+-CPU Layout IPMI_LAN USB5/6(3.0) LAN2 LAN1 CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1...
  • Page 12 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual X10DRG-O-PCIE Card Image Note: All graphics shown in this manual were based upon the latest PCB revision available at the time of publishing of the manual. The motherboard you've received may or may not look exactly the same as the graphics shown in this manual.
  • Page 13 Chapter 1: Overview X10DRG-O-PCIE Card Layout FAN22 FAN21 FAN25 FAN24 FAN23 X10DRG-O-PCIE REV:1.00 DESIGNED IN USA Root Port SLOT 5 SLOT 1 SLOT 4 SLOT 2 SLOT 3 LED3 LED19 LED1 LED18 LED14 LED4 LED11 LED2 LED6 LED10 LED15 LED7 Root Port SLOT 12 SLOT 8...
  • Page 14 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual X10DRG-O+-CPU/X10DRG-OT+-CPU Jumpers Jumper Description Default Setting JBT1 Clear CMOS See Chapter 2 JPB1 BMC Enable Pins 1-2 (Enabled) JPG1 VGA Enable Pins 1-2 (Enabled) JPL1 GLAN1/GLAN2 Enable Pins 1-2 (Enabled) JPME2 Manufacturer (ME) Mode Select Pins 1-2 (Normal)
  • Page 15 Type A USB (2.0) connector 4 for front access (BP) USB 5/6 (3.0) USB 3.0 connections 5/6 for rear access (BP) USB 7/8 (3.0) USB 3.0 connections 7/8 header for rear access Backpanel VGA port X10DRG-O+-CPU/X10DRG-OT+-CPU LED Indicators Description State Status Rear UID LED Blue: On Unit Identifi...
  • Page 16 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual X10DRG-O-PCIE Connectors Connector Description JPCIE1 CPU1 Slot1 3.0 x16 JPCIE2 CPU1 Slot5 3.0 x16 JPCIE3 CPU1 Slot2 3.0 x16 JPCIE4 CPU1 Slot4 3.0 x16 JPCIE5 CPU1 Slot3 3.0 x16 JPCIE6 CPU1 Slot7 3.0 x8 (in x16) JPCIE7 CPU1 Slot8 3.0 x16 JPCIE8 CPU1 Slot12 3.0 x16...
  • Page 17 • Graphics controller via the Aspeed AST2400 BMC Network • Intel® i350 Gigabit (10/100/1000 Mb/s) Ethernet controller for LAN 1/LAN 2 ports (X10DRG-O+-CPU) • Intel® X540 10GbE (TLAN) Ethernet controller for LAN 1/LAN 2 ports (X10DRG-OT+-CPU) • Aspeed 2400 Baseboard Controller (BMC) supports IPMI_LAN 2.0...
  • Page 18 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Serial (COM) Port • One (1) Fast UART 16550 connections (COM1: for backpanel support) Peripheral USB Devices Devices • Four (4) USB 3.0 ports on the rear I/O panel (USB 5/6, USB 7/8) • Two (2) USB 2.0 header for four USB 2.0 front- accessible connections (USB 0/1, 2/3) •...
  • Page 19 CPU TDP sizing. Note 2: For IPMI confi guration instructions, please refer to the Embedded IPMI Confi guration User's Guide available @ http://www.supermicro.com/ support/manuals/. Note 3: It is strongly recommended that you change BMC login information upon initial system power-on.
  • Page 20 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual #H-3 #H-2 #H-1 #D-3 #G-3 #D-2 #G-2 #D-1 #G-1 #C-3 #F-3 #F-2 #C-2 #F-1 #C-1 #E-3 #B-3 #B-2 #E-2 #B-1 #E-1 CPU2 CPU1 #A-3 #A-2 DDR-IV 9.6G #A-1 DDR-IV 9.6G DMI2 DMI2 PCI-E X16 Gen3 PCI-E X16 Gen3 PCI-E X16 Gen3 PCI-E X16 Gen3 PCI-E X8 Gen3...
  • Page 21 Chapter 1: Overview X10 DRG-O-PCIE System Block Diagram Note: This is a general block diagram and may not represent the features on your motherboard. See the "Motherboard Features" pages for the actual specifi cations of each board. 1-13...

  • Page 22: Processor And Chipset Overview

    X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Processor and Chipset Overview Built upon the functionality and capability of the Intel® E5-2600v3/v4 Series processors (Socket R3) and the Intel® PCH C612, the X10DRG-O(T)+-CPU/ X10DRG-O-PCIE platform provides the best balanced solution of performance, power effi ciency, and features to address the diverse needs of next-generation computer users.

  • Page 23: Special Features

    Chapter 1: Overview Special Features Recovery from AC Power Loss The Basic I/O System (BIOS) provides a setting that determines how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must press the power switch to turn it back on), or for it to automatically return to the power-on state.

  • Page 24: Acpi Features

    X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual ACPI Features ACPI stands for Advanced Confi guration and Power Interface. The ACPI specifi ca- tion defi nes a fl exible and abstract hardware interface that provides a standard way to integrate power management features throughout a PC system, including its hardware, operating system, and application software.

  • Page 25: Advanced Power Management

    Chapter 1: Overview Advanced Power Management The following new advanced power management features are supported by this board: Intel ® Intelligent Power Node Manager (NM) (Available when the SPM Utility is Installed) The Intel® Intelligent Power Node Manager 3.0 (IPNM) provides your system with real-time thermal control and power management for maximum energy effi...

  • Page 26: Chapter 2 Installation

    The following statements are industry-standard warnings provided to warn the user of situations that possible bodily injury might occur. Should you have questions or experience diffi culty, contact Technical Support at Supermicro for assistance. Only certifi ed technicians should attempt to install or remove components and confi gure system settings.
  • Page 27 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Attention Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer que par une pile de type semblable ou équivalent, recommandée par le fabricant. Jeter les piles usagées conformément aux instructions du fabricant. ¡Advertencia! Existe peligro de explosión si la batería se reemplaza de manera incorrecta. Re- emplazar la batería exclusivamente con el mismo tipo o el equivalente recomen- dado por el fabricante.
  • Page 28 Chapter 2: Installation Product Disposal Warning! Ultimate disposal of this product should be handled according to all national laws and regulations. 製品の廃棄 この製品を廃棄処分する場合、 国の関係する全ての法律 ・ 条例に従い処理する必要が あります。 警告 本产品的废弃处理应根据所有国家的法律和规章进行。 警告 本產品的廢棄處理應根據所有國家的法律和規章進行。 Warnung Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen des Landes erfolgen.

  • Page 29: Static-Sensitive Devices

    X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual ‫اﻟﻘﻮاﻧﯿﻦ واﻟﻠﻮاﺋﺢ اﻟﻮطﻨﯿﺔ‬ ‫ﺠﻤﯿﻊ‬ ‫وﻓﻘﺎ ﻟ‬ ‫ﯾﻨﺒﻐﻲ اﻟﺘﻌﺎﻣﻞ ﻣﻌﮫ‬ ‫ھﺬا اﻟﻤﻨﺘﺞ‬ ‫ﻣﻦ‬ ‫اﻟﺘﺨﻠﺺ اﻟﻨﮭﺎﺋﻲ‬ ‫ﻋﻨﺪ‬ 경고! 이 제품은 해당 국가의 관련 법규 및 규정에 따라 폐기되어야 합니다. Waarschuwing De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming met alle nationale wetten en reglementen.

  • Page 30: System Board Installation

    There are fourteen (14) mounting holes on this motherboard as shown below. IPMI_LAN USB5/6(3.0) LAN2 LAN1 CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE 10G SAN MAC I-SGPIO1 CLOSE 1st CLOSE 1st JPB1...
  • Page 31 2. Locate the mounting holes on the motherboard as shown below. IPMI_LAN USB5/6(3.0) LAN2 LAN1 CTRL JPW21 JPW22 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE 10G SAN MAC I-SGPIO1 CLOSE 1st JPB1 CLOSE 1st...

  • Page 32: Processor And Heatsink Installation

    CPU socket cap is in place and that none of the socket pins are bent; otherwise, contact your retailer immediately. • Refer to the Supermicro website for updates on CPU support. Installing the LGA2011 Processor 1. There are two load levers on the LGA2011 socket. To open the socket cover, fi...
  • Page 33 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual 2. Press the second load lever labeled 'Close 1st' to release the load plate that covers the CPU socket from its locking position. Pull lever away from Press down on Load the socket Lever 'Close 1st' 3. With the lever labeled 'Close 1st' fully retracted, gently push down on the lever labeled 'Open 1st' to open the load plate.
  • Page 34 Chapter 2: Installation 1. Use your thumb and the index fi nger to loosen the lever and open the load plate. 2. Using your thumb and index fi nger, hold the CPU on its edges. Align the CPU keys, which are semi-circle cutouts, against the socket keys. Socket Keys CPU Keys 3.
  • Page 35 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual 4. With the CPU inside the socket, inspect the four corners of the CPU to make sure that the CPU is properly installed. 5. Close the load plate with the CPU inside the socket. Lock the lever labeled 'Close 1st' fi...

  • Page 36: Installing A Passive Cpu Heatsink

    Chapter 2: Installation Installing a Passive CPU Heatsink 1. Do not apply any thermal grease to the heatsink or the CPU die -- the re- quired amount has already been applied. 2. Place the heatsink on top of the CPU so that the four mounting holes are aligned with those on the motherboard and the heatsink bracket underneath.

  • Page 37: Removing The Heatsink

    X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Removing the Heatsink Warning: We do not recommend that the CPU or the heatsink be removed. However, if you do need to uninstall the heatsink, please follow the instructions below to remove the heatsink to prevent damage done to the CPU or the CPU socket. 1.

  • Page 38: Installing And Removing The Memory Modules

    Chapter 2: Installation Installing and Removing the Memory Modules Note: Check Supermicro's website for recommended memory modules. CAUTION Exercise extreme care when installing or removing DIMM modules to prevent any possible damage. Installing Memory Modules 1. Insert the desired number of DIMMs into the memory slots, starting with P1-DIMMA1.
  • Page 39 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Memory Support for the X10DRG-O+-CPU/X10DRG-OT+-CPU Board The X10DRG-O(T)+-CPU/X10DRG-O-PCIE motherboard supports up to 3072 GB of 288-pin Load Reduced (LRDIMM) or 768 GB or Registered (RDIMM) DDR4 ECC 2400/2133/1866/1600 MHz in 24 slots. For the latest memory updates, please refer to our website at http://www.supermicro.com/products/motherboard.
  • Page 40 Chapter 2: Installation Populating RDIMM/LRDIMM DDR4 Memory Modules for the E5- 2600v4-based Motherboard Speed (MT/s); Voltage (V); Slot Per Channel (SPC) and DIMM Per Channel (DPC) DIMM Capacity Ranks Per (GB) DIMM and 3 Slots Per Channel Type Data Width 1DPC 2DPC 3DPC...

  • Page 41: Control Panel Connectors And I/O Ports

    Backpanel Connectors and I/O Ports IPMI_LAN USB5/6(3.0) LAN2 LAN1 CTRL JPW21 JPW22 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1...

  • Page 42: Video Connection

    USB5/6(3.0) LAN2 LAN1 CTRL JPW22 JPW21 JPW23 JPW24 1. VGA JBT1 USB2/3 2. LAN1 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE 3. LAN2 BIOS LICENSE IPMI CODE 10G SAN MAC I-SGPIO1 4. IPMI_LAN CLOSE 1st CLOSE 1st...

  • Page 43: Universal Serial Bus (Usb)

    5. FP USB 0/1 (USB 2.0) 6. FP USB 2/3 (USB 2.0) 7. Type A USB 4 (USB 2.0) JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE 10G SAN MAC I-SGPIO1 CLOSE 1st...

  • Page 44: Unit Identifi Er Switch/Uid Led Indicator

    NIC2 Link LED JPW22 JPW21 JPW23 JPW24 NIC1 Link LED NIC1 Activity LED JBT1 USB2/3 JPW5 HDD LED X10DRG-O+-CPU ID_UID_SW/3/3V Stby REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC 3.3V PWR LED...

  • Page 45: Serial Port

    Ground 1. COM Port 1 IPMI_LAN USB5/6(3.0) LAN2 LAN1 CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE 10G SAN MAC I-SGPIO1 CLOSE 1st CLOSE 1st JPB1 CPU1...

  • Page 46: Front Control Panel

    These connectors are designed spe- cifi cally for use with Supermicro's chassis. See the fi gure below for the descriptions of the control panel buttons and LED indicators. Refer to the following section for descriptions and pin defi...

  • Page 47: Front Control Panel Pin Defi Nitions

    HDD LED ID_UID_SW/3/3V Stby 3.3V PWR LED Ground JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU 1. NMI REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC 2. PWR LED CLOSE 1st CLOSE 1st...

  • Page 48: Hdd/Uid Led

    HDD LED ID_UID_SW/3/3V Stby 3.3V PWR LED Ground JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC 1. HDD/UID LED 2. NIC1 LED CLOSE 1st...

  • Page 49: Overheat (Oh)/Fan Fail/Uid Led

    3.3V PWR LED Ground JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 1. UID LED JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 2. OH/Fail/PWR Fail LED BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC 3. PWR Supply Fail CLOSE 1st...

  • Page 50: Reset Button

    ID_UID_SW/3/3V Stby 3.3V PWR LED Ground JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 1. Reset Button JPW5 X10DRG-O+-CPU REV: 1.00 2. PWR Button I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st...

  • Page 51: Connecting Cables

    HDD use) (Req'd) 16. JPW18: 8-pin PWR (for BPD JPW22 JPW21 JPW23 JPW24 HDD use) (Req'd) JBT1 13 14 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st...

  • Page 52: Fan Headers

    5. Fan 5 6. Fan 6 7. Fan 7 8 Fan 8 JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st JPB1 CLOSE 1st...

  • Page 53: Internal Speaker

    1. Internal Speaker (Buzzer) LAN2 LAN1 2. TPM/80 Port CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1...

  • Page 54: I-Sgpio1/2 & S-Sgpio Headers

    2. I-SGPIO2 (for I-SATA4/5) LAN2 LAN1 3. S-SGPIO (for S-SATA0-3) 4. Chassis Intrusion CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st JPB1 CLOSE 1st...

  • Page 55: Sata Dom Power Connectors

    1. JSD1 IPMI_LAN USB5/6(3.0) 2. JSD2 LAN2 LAN1 CTRL JPW21 JPW22 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1 CPU2...

  • Page 56: Jumper Settings

    USB5/6(3.0) (X10DRG-O+) LAN2 LAN1 1. GLAN1/2 Enable (X10DRG-OT+) CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1 CPU2...

  • Page 57: Cmos Clear

    USB5/6(3.0) 1. Clear CMOS 2. Watch Dog Enable LAN2 LAN1 CTRL JPW21 JPW22 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1...

  • Page 58: Vga Enable

    VGA Enabled IPMI_LAN USB5/6(3.0) BMC Enabled LAN2 LAN1 CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1 CPU2...

  • Page 59: Manufacturer Mode Select

    See the table on the right for jumper settings. IPMI_LAN 1. JPME2 USB5/6(3.0) LAN2 LAN1 CTRL JPW21 JPW22 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1 CPU1...

  • Page 60: Onboard Led Indicators

    USB5/6(3.0) 1. LAN1/2 LEDs LAN2 LAN1 2. IPMI LAN LEDs CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st CLOSE 1st JPB1...

  • Page 61: Onboard Power Led

    1. PWR LED (LE2) LAN2 LAN1 2. BMC LED (LEDM1) CTRL JPW22 JPW21 JPW23 JPW24 JBT1 USB2/3 JPW5 X10DRG-O+-CPU REV: 1.00 I-SGPIO2 BAR CODE 1G/10G MAC CODE BIOS LICENSE IPMI CODE I-SGPIO1 10G SAN MAC CLOSE 1st JPB1 CLOSE 1st...

  • Page 62: 2-10 Sata Connections

    Parallel ATA. See Ground the table on the right for pin defi nitions. Note: Please refer to the Intel SATA HostRAID User's Guide posted on our website @ http://www.supermicro.com for more info on SATA. IPMI_LAN USB5/6(3.0) 1. I-SATA0 2.

  • Page 63: Chapter 3 Troubleshooting

    Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the "Technical Support Procedures" and/or "Returning Merchandise for Service" section(s) in this chapter. Note: Always disconnect the power cord before adding, changing, or installing any hardware components.
  • Page 64 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual No Video 1. If the power is on but you have no video, remove all the add-on cards and cables. 2. Use the speaker to determine if any beep codes exist. Refer to Appendix A for details on beep codes. System Boot Failure If the system does not display POST or does not respond after the power is turned on, check the following:...
  • Page 65 2. Memory support: Make sure that the memory modules are supported by test- ing the modules using memtest86 or a similar utility. Note: Refer to the product page on our website http:\\www.supermicro. com for memory and CPU support and updates.
  • Page 66 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual tings in the IPMI to make sure that the CPU and system temperatures are within the normal range. Also check the front-panel Overheat LED is not on. 5. Adequate power supply: Make sure that the power supply provides adequate power to the system.

  • Page 67: Technical Support Procedures

    Technical Support Procedures Before contacting Technical Support, please take the following steps. Also, please note that as a motherboard manufacturer, Supermicro also sells motherboards through its channels, so it is best to fi rst check with your distributor or reseller for troubleshooting services.

  • Page 68: Battery Removal And Installation

    X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual Battery Removal and Installation Battery Removal To remove the onboard battery, follow the steps below: 1. Power off your system and unplug your power cable. 2. Locate the onboard battery as shown below. 3. Using a tool such as a pen or a small screwdriver, push the battery lock out- wards to unlock it.

  • Page 69: Frequently Asked Questions

    Note : The SPI BIOS chip used on this motherboard cannot be removed. Send your motherboard back to our RMA Department at Supermicro for repair. For BIOS recovery instructions, please refer to the AMI BIOS Re- covery Instructions posted at http://www.supermicro.com.

  • Page 70: Returning Merchandise For Service

    Shipping and handling charges will be applied for all orders that must be mailed when service is complete. For faster service, you can also request an RMA authorization online (http://www.supermicro.com/RmaForm/). This warranty only covers normal consumer use and does not cover damages in- curred in shipping or from failure due to the alternation, misuse, abuse, or improper maintenance of products.

  • Page 71: Chapter 4 Bios

    When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it. Note: The AMI BIOS has default text messages built in. Supermicro retains the option to include, omit, or change any of these text messages.

  • Page 72: Main Setup

    Flashing the wrong BIOS can cause irreparable damage to the system. In no event shall Supermicro be liable for direct, indirect, special, incidental, or consequential damages arising from a BIOS update. If you have to update the BIOS, do not shut down or reset the system while the BIOS is updating to avoid possible boot failure.
  • Page 73 Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00. Supermicro X10DRG-O(T)+ BIOS Version: This item displays the version of the BIOS ROM used in the system. Build Date: This item displays the date when the version of the BIOS ROM used in the system was built.

  • Page 74: Advanced Setup Confi Gurations

    X10DRG-O(T)+-CPU User’s Manual Advanced Setup Confi gurations Use the arrow keys to select Advanced setup and press <Enter> to access the submenu items: Warning: Take caution when changing the Advanced settings. An incorrect value, a very high DRAM frequency, or an incorrect BIOS timing setting may cause the system to malfunction.
  • Page 75 Chapter 4: AMI BIOS Bootup Num-Lock State Use this feature to set the Power-on state for the Numlock key. The options are On and Off. Wait For "F1" If Error Select Enabled to force the system to wait until the <F1> key is pressed if an error occurs.
  • Page 76 X10DRG-O(T)+-CPU User’s Manual CPU Confi guration  This submenu displays the following CPU information as detected by the BIOS. It also allows the user to confi gure CPU settings. • Processor Socket • Processor ID • Processor Frequency • Processor Max Ratio •...
  • Page 77 Chapter 4: AMI BIOS codes to overwhelm the processor to damage the system during an attack. This feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX," and "Lock Chipset" for Virtualization media support. The options are Disable and Enable.
  • Page 78 X10DRG-O(T)+-CPU User’s Manual AES-NI Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc- tions (NI) to ensure data security. The options are Disable and Enable. Intel Virtualization Technology Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d sup- port by reporting the I/O device assignments to the VMM (Virtual Machine Monitor) through the DMAR ACPI tables.
  • Page 79 Chapter 4: AMI BIOS No PCIe Port Active ECO This item provides a workaround solution when there is no PCIe port active. The options are PCU Squelch exit ignore option and Reset the SQ FLOP by CSR option. Socket 0 PCIED00F0 - Port 0/DMI This submenu allows the user to confi...
  • Page 80 X10DRG-O(T)+-CPU User’s Manual Non-Fatal Err Over (Non-Fatal Error Overwrite) This item confi gures the option to overwrite non-fatal errors. The options are Disable and Enable. Corr Err Over (Correctable Error Overwrite) This item confi gures the option to overwrite correctable errors for ECC memory. The options are Disable and Enable.
  • Page 81 Chapter 4: AMI BIOS PCI-E Port L0s Exit Latency Use this feature to set the length of time required for the port specifi ed by the user to complete the transition from L0s to L0. The default setting is 4uS - 8uS. PCI-E Port L1 Exit Latency Use this feature to set the length of time required for the port specifi...
  • Page 82 X10DRG-O(T)+-CPU User’s Manual Gen3 DN Rx Preset Hint This feature allows the user to select a preset setting for a downstream compo- nent receiver. The options are Auto, P0 (-6.0 dB), P1 (-7.0 dB), P2 (-8.0 dB), P3 (-9.0 dB), P4 (-10.0 dB), P5 (-11.0 dB), and P6 (-12.0 dB). Gen3 UP Tx Preset This feature allows the user to select the preset setting for a upstream compo- nent transmitter.
  • Page 83 Chapter 4: AMI BIOS Socket 1 PCIED00F0 - Port 0/DMI / Port 1A / Port 2A / Port 3A PCI-E Port Select Enable to enable a PCI-E port specifi ed by the user. Select Disable to de-activate a PCI-E port specifi ed by the user. Select Auto for the BIOS ROM to automatically discard a PCI-E port specifi...
  • Page 84 X10DRG-O(T)+-CPU User’s Manual Non-Fatal Err (Error) Over Select Enable to force non-fatal error propagation to the II0 core error logic for the port specifi ed by the user. The options are Disable and Enable. Corr Err (Correctable Error) Over Select Enable to force correctable error propagation to the II0 core error logic for the port specifi...
  • Page 85 Chapter 4: AMI BIOS Non-Transparent Bridge PCIe Port D (Port 3A only) Select Transparent Bridge to confi gure the device installed on a PCI slot specifi ed by the user as a transparent bridge (TB) device. Select NTB (Non-Transparent Bridge) to NTB to confi gure the device installed on a PCI slot specifi ed by the user as a non-transparent bridge (TB) device used to connect to another TB device.
  • Page 86 X10DRG-O(T)+-CPU User’s Manual QPI (Quick Path Interconnect) Confi guration QPI General Confi guration QPI Status The following information will display: • Number of CPU • Number of IIO • Current QPI Link Speed • Current QPI Link Frequency • QPI Global MMIO Low Base/Limit •...
  • Page 87 Chapter 4: AMI BIOS Memory Confi guration Enforce POR Select Enable to enforce POR restrictions on memory frequency and voltage programming. The options are Enabled and Disabled. Memory Frequency Use this feature to set the maximum memory frequency for onboard memory modules.
  • Page 88 X10DRG-O(T)+-CPU User’s Manual Memory RAS (Reliability Availability Serviceability) Confi guration Use this submenu to confi gure the following Memory RAS settings. RAS Mode When Disable is selected, RAS is not supported. When Mirror is selected, the motherboard maintains two identical copies of all data in memory for data backup. When Lockstep is selected, the motherboard uses two areas of memory to run the same set of operations in parallel to boost performance.
  • Page 89 Chapter 4: AMI BIOS South Bridge Confi guration  The following South Bridge information will display: USB Confi guration  • USB Module Version • USB Devices Legacy USB Support Select Enabled to support onboard legacy USB devices. Select Auto to disable legacy support if there are no legacy USB devices present.
  • Page 90 X10DRG-O(T)+-CPU User’s Manual *If the item above "Confi gure SATA as" is set to AHCI, the following items will display: Support Aggressive Link Power Management When this item is set to Enabled, the SATA AHCI controller manages the power usage of the SATA link. The controller will put the link to a low power state when the I/O is inactive for an extended period of time, and the power state will return to normal when the I/O becomes active.
  • Page 91 Chapter 4: AMI BIOS *If the item above "Confi gure SATA as" is set to RAID, the following items will display: Support Aggressive Link Power Management When this item is set to Enabled, the SATA AHCI controller manages the power usage of the SATA link.
  • Page 92 X10DRG-O(T)+-CPU User’s Manual  sSATA Confi guration When this submenu is selected, the AMI BIOS automatically detects the presence of the SATA devices that are supported by the PCH-sSATA controller and displays the following items: sSATA Controller This item enables or disables the onboard SATA controller supported by the Intel PCH-sSATA controller.
  • Page 93 Chapter 4: AMI BIOS Port 0-Port 3 sSATA Device Type Use this item to specify if the sSATA port specifi ed by the user should be connected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State Drive.
  • Page 94 X10DRG-O(T)+-CPU User’s Manual Port 0-Port 3 Hot Plug Select Enabled to support Hot-plugging for the selected SATA port which will allow the user to replace a device without shutting down the system. The options are Disabled and Enabled. sSATA Port 0-Port 3 Spin Up Device On an edge detect from 0 to 1, set this item to allow the PCH to start a COMRE- SET initialization to the device.
  • Page 95 Chapter 4: AMI BIOS PCIe/PCI/PnP Confi guration PCI Devices Common Settings PCI Latency Timer Select Enabled to set the latency timer for PCI. The options are 32 PCI Bus Clocks, 64 PCI Bus Clocks, 96 PCI Bus Clocks, 128 PCI Bus Clocks, 160 PCI Bus Clocks, 192 PCI Bus Clocks, 224 PCI Bus Clocks, and 248 PCI Bus Clocks.
  • Page 96 X10DRG-O(T)+-CPU User’s Manual on the system confi guration. Select Disabled to disable ASPM support. The options are Disabled and Auto. Warning: Enabling ASPM support may cause some PCI-E devices to fail! MMIOHBase Use this item to select the base memory size according to memory-address map- ping for the PCH.
  • Page 97 Chapter 4: AMI BIOS CPU1 Slot 8 PCI-E x16 OPROM (Option ROM) Select Enabled to enable Option ROM support to boot the computer using a device installed on slot 5. The options are Disabled, Legacy, and EFI. CPU1 Slot 9 PCI-E x16 OPROM (Option ROM) Select Enabled to enable Option ROM support to boot the computer using a device installed on slot 5.
  • Page 98 X10DRG-O(T)+-CPU User’s Manual Super IO Confi guration  Super IO Chip AST2400  Serial Port 1 Confi guration/Serial Port 2 Confi guration Serial Port Select Enabled to enable the onboard serial port specifi ed by the user. The options are Disabled and Enabled. Change Port 1 Settings/Change Port 2 Settings This feature specifi...
  • Page 99 Chapter 4: AMI BIOS acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or more bytes. The options are VT100, VT100+, VT-UTF8, and ANSI. Bits per second Use this item to set the transmission speed for a serial port used in Console Redirection.
  • Page 100 X10DRG-O(T)+-CPU User’s Manual Resolution 100x31 Select Enabled for extended-terminal resolution support. The options are Dis- abled and Enabled. Legacy OS Redirection Resolution Use this item to select the number of rows and columns used in Console Redi- rection for legacy OS support. The options are 80x24 and 80x25. Putty KeyPad This feature selects Function Keys and KeyPad settings for Putty, which is a terminal emulator designed for the Windows OS.
  • Page 101 Chapter 4: AMI BIOS Bits Per second Use this feature to set the transmission speed for a serial port used in Console Redirection. Make sure that the same speed is used in the host computer and the client computer. A lower transmission speed may be required for long and busy lines.
  • Page 102 X10DRG-O(T)+-CPU User’s Manual Legacy OS Redirection Resolution Use this feature to select the number of rows and columns used in Console Redirection for legacy OS support. The options are 80x24 and 80x25. Putty KeyPad This feature selects Function Keys and KeyPad settings for Putty, which is a terminal emulator designed for the Windows OS.
  • Page 103 Chapter 4: AMI BIOS Out-of-Band Management Port The feature selects a serial port in a client server to be used by the Windows Emergency Management Services (EMS) to communicate with a remote host server. The options are COM1 (Console Redirection) and SOL (Console Re- direction)/COM2.
  • Page 104 Note: Your system will reboot to carry out a pending TPM operation. Current Status Information This item displays the status of the TPM support on this motherboard. Note: For more information on TPM, please refer to the TPM manual at http://www.supermicro.com/manuals/other/TPM.pdf. ACPI Settings  WHEA Support...
  • Page 105 Chapter 4: AMI BIOS iSCSI Confi guration This item displays iSCSI confi guration information: iSCSI Initiator Name This item displays the name of the iSCSI Initiator, which is a unique name used in the world. The name must use the IQN format. The following actions can also be performed: ...

  • Page 106: Event Logs

    X10DRG-O(T)+-CPU User’s Manual Event Logs Use this feature to confi gure Event Log settings. Change SMBIOS Event Log Settings  This feature allows the user to confi gure SMBIOS Event settings. Enabling/Disabling Options SMBIOS Event Log Select Enabled to enable SMBIOS (System Management BIOS) Event Logging during system boot.
  • Page 107 Chapter 4: AMI BIOS When Log is Full Select Erase Immediately to immediately erase all errors in the SMBIOS event log when the event log is full. Select Do Nothing for the system to do nothing when the SMBIOS event log is full. The options are Do Nothing and Erase Immediately. SMBIOS Event Log Standard Settings Log System Boot Event Select Enabled to log system boot events.

  • Page 108: Ipmi

    X10DRG-O(T)+-CPU User’s Manual IPMI Use this feature to confi gure Intelligent Platform Management Interface (IPMI) settings. IPMI Firmware Revision This item indicates the IPMI fi rmware revision used in your system. Status of BMC This item indicates the status of the onboard BMC (Baseboard Management Con- troller).
  • Page 109 Chapter 4: AMI BIOS Erasing Settings Erase SEL Select Yes, On next reset to erase all system event logs upon next system reboot. Select Yes, On every reset to erase all system event logs upon each system reboot. Select No to keep all system event logs after each system reboot. The options are No;...
  • Page 110 X10DRG-O(T)+-CPU User’s Manual Subnet Mask This item displays the sub-network that this computer belongs to. The value of each three-digit number is separated by dots and it should not exceed 255. Station MAC Address This item displays the Station MAC address for this computer. Mac addresses are 6 two-digit hexadecimal numbers.

  • Page 111: Security Settings

    Chapter 4: AMI BIOS Security Settings This menu allows the user to confi gure the following security settings for the system. Administrator Password Use this feature to set the administrator password which is required before the user entering the BIOS setup utility. The length of the password should be from 3 characters to 20 characters long.
  • Page 112 X10DRG-O(T)+-CPU User’s Manual Key Management Default Key Provision Select Enable to install all manufacture defaults for the following system security settings. The options are Disabled and Enabled. Enroll All Factory Default Keys This feature allows the user to store security-related boot data in a fi le of the same named in the system root folder of your computer.
  • Page 113 Chapter 4: AMI BIOS Authorized TimeStamps Delete DBT (DataBase Timer) Select <Yes> to confi rm deletion of the database timer from the NVRAM (Non- Volatile RAM). Set New DBT (DataBase Timer) Select <Yes> to confi rm that the new database timer will be set in the NVRAM (Non-Volatile RAM).

  • Page 114: Boot Settings

    X10DRG-O(T)+-CPU User’s Manual Boot Settings Use this feature to confi gure Boot settings: Boot Confi guration Boot Mode Select Use this item to select the type of device to be used for system boot. The options are LEGACY, UEFI, and DUAL. Fixed Boot Order Priorities This option prioritizes the order of bootable devices from which the system will boot.
  • Page 115 Chapter 4: AMI BIOS • Dual Boot Order #7 • Dual Boot Order #8 • Dual Boot Order #9 • Dual Boot Order #10 • Dual Boot Order #11 • Dual Boot Order #12 • Dual Boot Order #13 • Dual Boot Order #14 •...
  • Page 116 X10DRG-O(T)+-CPU User’s Manual Delete Driver Option Select the target driver to delete.  Hard Disk Drive BBS Priorities • Boot Option #1 • Boot Order #2 • Boot Order #3 • Boot Order #4 • Boot Order #5 • Boot Order #6 •...

  • Page 117: Save & Exit

    Chapter 4: AMI BIOS Save & Exit Select the Save & Exit tab from the BIOS setup screen to confi gure the settings below. Discard Changes and Exit Select this option to quit the BIOS setup without making any permanent changes to the system confi...
  • Page 118 X10DRG-O(T)+-CPU User’s Manual Restore Optimized Defaults To set this feature, select Restore Optimized Defaults from the Exit menu and press <Enter>. These are manufacture default settings designed for maximum system performance but not for maximum stability. Save as User Defaults To set this feature, select Save as User Defaults from the Exit menu and press <En- ter>.

  • Page 119: Appendix A Bios Post Error Beep Codes

    Appendix A: BIOS POST Error Codes Appendix A BIOS POST Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed at each system boot, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue to boot.

  • Page 120: Appendix B Software Installation Instructions

    Appendix B Software Installation Instructions B-1 Installing Software Programs The Supermicro website that contains drivers and utilities for your system is located at http://www.supermicro.com/wftp. Some of these must be installed, such as the chipset driver. After accessing the product drivers and utilities page, go into the CDR_Images directory and locate the ISO fi...

  • Page 121: Confi Guring Superdoctor 5

    SATA settings back to your original settings. B-2 Confi guring SuperDoctor 5 The Supermicro SuperDoctor® 5 is a hardware monitoring program that functions in a command-line or web-based interface. The program monitors system health information such as CPU temperature, system voltages, system power consump- tion, fan speed, and provides alerts via email or Simple Network Management Protocol (SNMP).

  • Page 122: Appendix C Uefi Bios Recovery Instructions

    Flashing the wrong BIOS can cause irreparable damage to the system. In no event shall Supermicro be liable for direct, indirect, special, incidental, or consequential damages arising from a BIOS update. If you need to update the BIOS, do not shut down or reset the system while the BIOS is updating to avoid possible boot failure.
  • Page 123 "\" directory of a USB device or a writeable CD/DVD. Note: If you cannot locate the "Super.ROM" fi le in your driver disk, visit our website at www.supermicro.com to download the BIOS image into a USB fl ash device and rename it "Super.ROM" for BIOS recovery use.
  • Page 124 Appendix C: UEFI BIOS Recovery 4. After locating the new BIOS binary image, the system will enter the BIOS recovery menu as shown below. Note: At this point, you may decide if you want to start with BIOS recovery. If you decide to proceed with BIOS recovery, follow the procedures below. 5.
  • Page 125 X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual 6. After the process of BIOS recovery is completed, press any key to reboot the system. 7. Using a different system, extract the BIOS package into a bootable USB fl ash drive. 8. When a DOS prompt appears, enter FLASH.BAT BIOSname.### at the prompt.

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