NXP Semiconductors MPC5606S Reference Manual

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MPC5606S Microcontroller Reference

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Supports MPC5602S, MPC5604S and MPC5606S

MPC5606S Microcontroller Reference Manual, Rev. 7

Freescale Semiconductor

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Page 1 MPC5606S Microcontroller Reference Manual Supports MPC5602S, MPC5604S and MPC5606S MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 2 The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.  © 2008–2012 Freescale Semiconductor, Inc. Document Number: MPC5606SRM Rev. 7 10/2012 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 3: Table Of Contents
1.7.1 The MPC5606S document set ........
Page 4 4.2.5.4 SWT Timeout Register (SWT_TO) ......124 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 5 5.4.5.1 Introduction ..........155 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 6 6.6.2 Interrupts ........... . . 179 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 7 8.8 FIRC digital interface ........... 214 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 8 9.1.4 MPC5606S family comparison ........
Page 9 10.3 Overview ............279 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 10 11.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) ....305 11.7.2.8 DSPI Transmit FIFO Registers 0–4 (DSPIx_TXFRn) ... . . 305 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 11 11.9.4 Calculation of FIFO pointer addresses ....... 330 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 12 12.3.4.26 PDI Status Register ........382 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 13 12.6.2 List of protected registers .........432 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 14 13.5.2.4 Switching the source of a DMA channel ..... . . 459 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 15 15.4.2 DMA basic data flow ..........506 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 16 16.4.2.14 Flash ECC Data Register (FEDR) ......537 16.4.2.15 RAM ECC Address Register (REAR) ......538 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 17 17.2.6.20 User Multiple Input Signature Register 2 (UMISR2) ... . . 578 17.2.6.21 User Multiple Input Signature Register 3 (UMISR3) ... . . 578 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 18 17.3.7.2 Double Word program ........623 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 19 18.2.2 Signal descriptions ..........672 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 20 18.5.1 FlexCAN initialization sequence ........712 18.5.2 FlexCAN Addressing and RAM size configurations ..... 713 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 21 20.1.3 Block diagram ..........729 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 22 21.1 Introduction ............751 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 23 21.7.8 Lowering priority within an ISR ........783 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 24 22.5.2 LCD clock and frame frequency ........813 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 25 23.7.1 Memory map ........... 835 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 26 24.1.2 Features ............883 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 27 25.3.2.15 Standby Mode Configuration Register (ME_STANDBY_MC) ..926 25.3.2.16 Peripheral Status Register 0 (ME_PS0) ..... . 928 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 28 25.4.5.3 Safe mode transition interrupt ....... 951 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 29 27.1.2 Features ............973 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 30 29.3.2.3 Power Domain #2 Configuration Register (PCU_PCONF2) ..988 29.3.2.4 Power Domain Status Register (PCU_PSTAT) ....989 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 31 30.4.3.1 Register write access ........1003 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 32 30.5.3.4 Byte Ordering of Serial Flash Data ......1051 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 33 31.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ..1081 31.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) ..1082 31.3.1.6 Destructive Event Alternate Request Register (RGM_DEAR) ..1083 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 34 33.8 Initialization and application information ........1108 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 35 35.3.2.5 Motor Controller Duty Cycle Register (MCDC0..11) ... . . 1129 35.3.2.6 Short-circuit Detector Timeout Register (MCSDTO) ... . . 1131 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 36 36.4.1 Main building blocks of the SSD ........1166 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 37 37.5.3.6 Interrupt Falling-Edge Event Enable Register (IFEER) ..1194 37.5.3.7 Interrupt Filter Enable Register (IFER) ..... . . 1195 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 38 39.2 External signal description ..........1221 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 39 41.4.2.5 Wakeup Request Enable Register (WRER) ....1243 41.4.2.6 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) . . 1243 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 40 C.7 Changes between revisions 0 and 1 ........1342 MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 41 This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MPC5606S device. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture.
Page 42 In addition to this reference manual, the following documents provide additional information on the operation of the MPC5606S: • IEEE-ISTO 5001-2003 Standard for a Global Embedded Processor Interface (Nexus) • IEEE 1149.1-2001 standard—IEEE Standard Test Access Port and Boundary-Scan Architecture • Power Architecture (http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 43: Introduction
Section 1.6, Developer environment, more information. The MPC5606S platform has a single level of memory hierarchy and supports a wide range of on-chip SRAM and internal flash memories. The 1 MB flash memory version (MPC5606S) outlined in detail within this document features 160 KB of on-chip graphics SRAM to buffer cost-effective color TFT displays driven via the on-chip Display Control Unit (DCU).
Page 44 — 32-bit data bus width • System Status and Configuration Module (SSCM) — Provides information for identification of the device, last boot mode, or debug status — Provides an entry point for censorship password mechanism MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 45: Mpc5606S Family Comparison
JTAG (IEEE 1149.1) Nexus port for application development with optional Nexus 2+ trace port. • The MPC5606S microcontroller is offered in the following packages: — 144-pin LQFP, 0.5mm pitch, 20 mm × 20 mm outline — 176-pin LQFP, 0.5mm pitch, 24 mm × 24 mm outline —...
Page 46 0x40000000 0x4000BFFF Table 1-3 provides a summary of the different members of the MPC5606S family. This information is intended to provide an understanding of the range of functionality offered by this family. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 47: Block Diagram
Overview Block diagram Figure 1-1 shows a top-level block diagram of the MPC5606S. Nexus Port JTAG Port Video SRAM Flash SRAM Test Controller Nexus Port Controller JTAG SRAM Flash SRAM Controller Controller Controller FIRC 16 MHz Instructions e200z0h SIRC Data...
Page 48 Stepper Motor Controller (SMC) module with high-current drivers for up to six instrument cluster gauges driven in full dual H-Bridge configuration including full diagnostics for short circuit detection • Stepper motor return-to-zero and stall detection module MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 49 Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 50: Feature Details
1.5.1 Low-power operation MPC5606S devices are designed for optimized low-power operation and dynamic power management of the core processor and peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes.
Page 51 It can be configured to provide more efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wakeup latency. The system returns to a Run mode as soon as an event or interrupt is pending. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 52 Overview Table 1-3 summarizes the operating modes of MPC5606S devices. Table 1-3. Operating mode summary Operating modes: Halt Stop Standby SoC features Core — Peripherals — Flash memory — SRAM 8 KB — Graphics RAM — Clock sources Main PLL —...
Page 53: E200Z0H Core Processor
PLL input clock source to provide fast startup, without external oscillator delay • MPC5606S devices include an internal voltage regulator that includes the following features: — Regulates input to generate all internal supplies — Manages power gating —...
Page 54 The CPU core is enhanced by an additional interrupt source, the Non-Maskable Interrupt (NMI). This interrupt source is routed directly from package pins, via edge detection logic in the SIU to the CPU, MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 55: Crossbar Switch (Xbar)
— e200z0h core instruction port — e200z0h core complex load/store data port — eDMA controller — Display control unit • Four slave ports: — One flash port dedicated to the CPU — Platform SRAM MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 56: Enhanced Direct Memory Access (Edma)
Software-programmable for one of 256 different serial clock frequencies • Software-selectable acknowledge bit • Interrupt-driven, byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 57: Interrupt Controller (Intc)
Automatic serial flash read command generation by CPU, DMA, or DCU read access on AHB bus • Supports single, dual, and quad serial flash read commands • Flexible buffering scheme to maximize read bandwidth of serial flash MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 58: System Integration Unit (Siu)
1.5.9 Flash memory The MPC5606S microcontroller has the following flash memory features: • As nuch as 1 MB of burst flash memory — Typical flash memory access time: 0 wait state for buffer hits, 2 wait states for page buffer miss at 64 MHz —...
Page 59: Sram
— Same data retention and program erase specification as main program flash memory array 1.5.10 SRAM The MPC5606S microcontrollers have as much as 48 KB general-purpose on-chip SRAM with the following features: • Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back with a read to same memory block •...
Page 60: Enhanced Modular Input/Output System (Emios)
Reset Configuration Halfword 1.5.14 Enhanced Modular Input/Output System (eMIOS) MPC5606S microcontrollers have two eMIOS modules—one with 16 channels and one with eight—with input/output channels supporting a range of 16-bit input capture, output compare, and Pulse Width Modulation functions. The modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output pulse width modulation/input compare/output compare.
Page 61: Analog-To-Digital Converter (Adc)
The ADC features the following: • 10-bit A/D resolution • 0 to 5 V common mode conversion range • Supports conversions speeds of up to 1 µs • 16 internal and eight external channel support MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 62: Deserial Serial Peripheral Interface (Dspi)
Optional support for DMA transfer of results 1.5.16 Deserial Serial Peripheral Interface (DSPI) The deserial serial peripheral interface (DSPI) modules provide a synchronous serial interface for communication between the MPC5606S MCU and external devices. The DSPI features the following: • As many as two DSPI modules •...
Page 63: Flexcan
• CAN Sampler — Can catch the first message sent on the CAN network while the MPC5606S is stopped; this guarantees a clean startup of the system without missing messages on the CAN network — CAN sampler is connected to one of the CAN RX pins MPC5606S Microcontroller Reference Manual, Rev.
Page 64: Serial Communication Interface Module (Linflex)
— Two receiver wakeup methods 1.5.19 System clocks and clock generation modules The system clock on the MPC5606S can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz oscillator. MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 65: Periodic Interrupt Timer Module (Pit)
— Automatic level control — PLL reference • MPC5606S includes a 32 KHz low-power external oscillator for slow execution, reduced power consumption, and Real Time Clock • Dedicated internal 128 kHz RC oscillator for low-power mode operation and self wakeup —...
Page 66: Real Time Counter (Rtc)
The internal memory resources of the Spectrum allow easy management of complex graphics contents (pictures, icons, languages, fonts) on a color TFT panel in up to WQVGA sizes. All the data fetches from MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 67: Parallel Data Interface (Pdi)
DCU to handle input data in formats as low as 1bpp, 2bpp, and 4bpp enables highly efficient use of internal memory resources of the MPC5606S. A special tiled mode can be enabled on any of the 16 layers to repeat a pattern, optimizing graphic memory usage.
Page 68: Liquid Crystal Display (Lcd) Driver
— Optimize data refresh without visual artifacts — Selectable number of frames between each interrupt • Contrast adjustment using programmable internal voltage reference • Remapping capability of four or six backplanes with frontplanes — Increases pin selection flexibility MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 69: Stepper Motor Controller (Smc)
— 8-bit amplitude resolution — Ability to mix any two eMIOS channels — Requires simple external RC lowpass filter • Digital sample mode for higher quality sound using one eMIOS channel and eDMA MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 70: Ieee 1149.1 Jtag Controller (Jtagc)
— Wide Auxiliary Nexus port supporting higher bandwidth trace, with four MDO pins Developer environment The MPC5606S MCU family uses tools and third-party developers that offer a widespread, established network of tool and software vendors. It also features a high-performance Nexus debug interface.
Page 71: How To Use The Mpc5606S Documents
This reference manual (provides information on the features of the logical blocks on the device and how they are integrated with each other) • The MPC5606S Microcontroller Data Sheet (specifies the electrical characteristics of the device) • The device product brief The following reference documents (available online at www.freescale.com) are also available to support...
Page 72 Voltage regulators and Power distribution to the MCU and in — power supplies particular to different I/O banks Wakeup Unit Allocation of inputs to the Wakeup Unit Operation of the wakeup feature MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 73: Using The Mpc5606S
Using the MPC5606S There are many different approaches to designing a system using the MPC5606S, so the guidance in this section is provided as an example of how the documents can be applied to this task.
Page 74: Software Design
Overview have different pad types. The electrical specification of the pads is described in the MPC5606S Microcontroller Data Sheet, dependent on the function enabled and the pad type. There are four modules that configure the various functions available: • System Integration Unit Lite (SIUL) •...
Page 75: Input/Output Pins
Register Protection module. The protected registers are shown in Appendix A, Registers Under Protection. Other integration functionality is provided by the System Status and Configuration Module (SSCM), described in Chapter 38, System Status and Configuration Module (SSCM). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 76 Overview MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 77: Chapter 2
Chapter 2  Memory Map Table 2-1 shows the system memory map for the MPC5606S. All addresses on the MPC5606S, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block.
Page 78: Memory Map
Memory Map Table 2-1. MPC5606S system memory map (continued) Size Region [KB] Start End Address Address On-chip Flash Memories (Data Flash) 0x00800000 0x00803FFF Data Flash Array 0 0x00804000 0x00807FFF Data Flash Array 0 0x00808000 0x0080BFFF Data Flash Array 0 0x0080C000...
Page 79: Memory Map
Memory Map Table 2-1. MPC5606S system memory map (continued) Size Region [KB] Start End Address Address 0xC3F8C000 0xC3F8FFFF Data Flash 0 Configuration (DFLASH0) 0xC3F90000 0xC3F93FFF System Integration Unit Lite (SIUL) 0xC3F94000 0xC3F97FFF WakeUp Unit (WKPU) 0xC3F98000 0xC3F9FFFF — — —...
Page 80: Memory Map
Memory Map Table 2-1. MPC5606S system memory map (continued) Size Region [KB] Start End Address Address 0xFFE34000 0xFFE37FFF Inter-IC Bus Interface Controller 1 0xFFE38000 0xFFE3BFFF Inter-IC Bus Interface Controller 2 0xFFE3C000 0xFFE3FFFF Inter-IC Bus Interface Controller 3 0xFFE40000 0xFFE43FFF LINFlex 0...
Page 81: Memory Map
Memory Map Table 2-1. MPC5606S system memory map (continued) Size Region [KB] Start End Address Address 0xFFF10000 0xFFF13FFF Memory Protection Unit (MPU) 0xFFF14000 0xFFF37FFF — — — Reserved 0xFFF38000 0xFFF3BFFF Software Watchdog (SWT0) 0xFFF3C000 0xFFF3FFFF System Timer Module (STM0) 0xFFF40000...
Page 82: Memory Map
Memory Map MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 83: Introduction
Signal Description Chapter 3  Signal Description Introduction The following sections provide signal descriptions and related information about functionality and configuration. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 84: Package Pinouts
VREG_BYPASS VDDMA FP4/eMIOSB21/DCU_B3/GPIO[89]/PG3 – TDI/GPIO[100]/PH1 PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20 FP3/eMIOSB17/DCU_B4/GPIO[90]/PG4 – TDO/GPIO[101]/PH2 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21 TMS/GPIO[102]/PH3 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22 TCK/GPIO[99]/PH0 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23 Figure 3-1. LQFP 144-pin configuration (top view) 1. Availability of port pin alternate functions depends on product selection. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 85 PDI15/MDO1/GPIO[128]/PK7 VDDMA BP1/DCU_HSYNC/GPIO[95]/PG9 – TMS/GPIO[102]/PH3 PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20 BP3/DCU_PCLK/GPIO[97]/PG11 – PDI16/MDO2/GPIO[129]/PK8 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21 TCK/GPIO[99]/PH0 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22 PDI17/MDO3/GPIO[130]/PK9 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23 Figure 3-2. LQFP 176-pin configuration (top view) 1. Availability of port pin alternate functions depends on product selection. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 86 PJ14 PF10 PF11 PF12 VDDE_A PJ15 VDDE_E PF13 VDDE_A PJ10 PJ12 VDDE_E PF14 VDD12 PJ11 PJ13 VDD12 PG12 VDD12 PF15 PA10 PA11 PA12 PA13 PA15 VDDMC VSSMC RESET PA14 PG10 XTAL VDDE_A PG11 PD13 VSSPLL VDDPLL NMI/PF2 MDO3 PD15 PD12 VDDMB VSSMB EXTAL...
Page 87: Pad Configuration During Reset Phases
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. There is a preferred startup sequence for devices in the MPC5606S family. That sequence is described in the next paragraphs.
Page 88: Pad Types
3. LV supply The reason for following this sequence is to ensure that when VREG releases its LVDs, the I/O and other HV segments are powered properly. This is important because the MPC5606S does not monitor LVDs on I/O HV supplies.
Page 89: System Pins
Table 3-3. Debug pin descriptions Pin number Debu directio RESET 208 MAPBGA Function config 176 LQFP 144 LQFP Dedi- debug Muxed cated JTAG test clock Input, Pullup — JTAG test data in Input, Pullup — MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 90: Functional Ports
This may cause high currents if the pins are tied to a supply/ground in the application. If not used, these pins may be left unconnected. Functional ports The functional port pins are listed in Table 3-4. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 91 Table 3-4. Port pin summary Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PA[0] PCR[0] Option 0 GPIO[0] FP23 SIUL None, Option 1 DCU_R0 None Option 2 eMIOSA[22] PWM/Timer Option 3 SOUND...
Page 92 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PA[8] PCR[8] Option 0 GPIO[8] FP15 SIUL None, Option 1 DCU_G0 None Option 2 eMIOSB[23] PWM/Timer Option 3...
Page 93 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PB[0] PCR[16] Option 0 GPIO[16] — SIUL None, Option 1 CANTX_0 FlexCAN_0 None Option 2 PDI1 Option 3 —...
Page 94 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PB[8] PCR[24] Option 0 GPIO[24] — SIUL None, Option 1 SOUT_0 DSPI_0 None Option 2 eMIOSB[21] PWM/Timer Option 3...
Page 95 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PC[1] PCR[31] Option 0 GPIO[31] ANS[1] SIUL None, Option 1 — — None Option 2 —...
Page 96 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PC[9] PCR[39] Option 0 GPIO[39] ANS[9] SIUL None, Option 1 — — None Option 2 —...
Page 97 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PD[1] PCR[47] Option 0 GPIO[47] — SIUL None, Option 1 M0C0P None Option 2 SSD0_1 Option 3 eMIOSB[22]...
Page 98 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PD[9] PCR[55] Option 0 GPIO[55] — SIUL None, Option 1 M2C0P None Option 2 SSD2_1 Option 3 —...
Page 99 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PE[1] PCR[63] Option 0 GPIO[63] — SIUL None, Option 1 M4C0P None Option 2 SSD4_1 Option 3 eMIOSA[14]...
Page 100 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PE[12] — — Reserved — — — — — — — — PE[13] — —...
Page 101 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PF[7] PCR[77] Option 0 GPIO[77] FP33 SIUL None, Option 1 SCL_0 None Option 2 PCS2_1 DSPI_1 Option 3...
Page 102 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PF[15] PCR[85] Option 0 GPIO[85] FP24 SIUL None, Option 1 SCK_2 QuadSPI None Option 2 —...
Page 103 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PG[7] PCR[93] Option 0 GPIO[93] SIUL None, Option 1 DCU_B7 None Option 2 — —...
Page 104 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PH[1] PCR[100] Option 0 GPIO[100] — SIUL Input, Option 1 JTAG Pullup Option 2 —...
Page 105 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PH[15] — — Reserved — — — — — — — — PJ[0] PCR[105] Option 0 GPIO[105] —...
Page 106 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PJ[8] PCR[113] Option 0 GPIO[113] — SIUL None, — Option 1 PDI[4] None Option 2 —...
Page 107 Table 3-4. Port pin summary (continued) Pin number Port Alternate Special RESET Function Peripheral register function function direction type config. 208 MAPBG 144 LQFP 176 LQFP PK[0] PCR[121] Option 0 GPIO[121] — SIUL None, — Option 1 PDI[12] None Option 2 eMIOSA[18] PWM/Timer Option 3...
Page 108 Out of reset, pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO, and TMS, respectively). It is up to the user to configure pins PH[0:3] when needed. This pin can be used for LCD supply pin VLCD. Refer to the voltage supply pin descriptions in the MPC5606S data sheet for details.
Page 109: Signal Details
Indicates when a tagged pixel is present in safety mode. DCU_VSYNC Vertical sync pulse for TFT-LCD display. PCS[0..2]_0, DSPI Peripheral chip selects when device is in Master mode; not used in PCS[0..2]_1 slave modes. SCK_0, DSPI SPI clock signal—bidirectional. SCK_1 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 110 TAP controller in the device. BP[0:3] Backplane signals from the LCD controlling the backplane reference voltage for the LCD display. FP[0:39] Frontplane signals for LCD segments. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 111 SSD[0:5]_1 SSD[0:5]_2 SSD[0:5]_3 M[0:5]C0M Controls stepper motors in various configurations. M[0:5]C0P M[0:5]C1M M[0:5]C1P CLKOUT MC_CGM Output clock—It can be selected from several internal clocks of the device from the clock generation module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 112 Signal Description MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 113: Register Protection
• Restrict write accesses for the module under protection to supervisor mode only • Lock registers for first 6 KB of memory-mapped address space • Address mirror automatically sets corresponding lock bit MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 114: Modes Of Operation
0x2000 + X will set the optional Soft Lock Bits for this address X in the same cycle as the register at address X is written. Not all registers in area 1 need to have protection defined by associated Soft Lock MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 115: Memory Map
Soft Lock Bit Register 1535 (SLBR1535): Soft Lock Bits 6140-6143 0x3E00–0x3FFB Reserved 0x3FFC Global Configuration Register (GCR) on page 115 NOTE Reserved registers in area #2 will be handled according to the protected IP (module under protection). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 116: Register Description
SLB2 can block accesses to MR[(n × 4) + 2] SLB3 SLB3 can block accesses to MR[(n × 4) + 3] 0 Associated MRn byte is unprotected and writable 1 Associated MRn byte is locked against write accesses MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 117 1 The registers in the module under protection can be accessed in the User mode without any additional restrictions. NOTE The GCR.UAA bit has no effect on the allowed access modes for the registers in the Register Protection module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 118: Functional Description
SLB0 to SLB1 to SLB2 to SLB3 SLBRn.WE[3:0] SLBRn.WE[3:0] change allowed change allowed SLB0 SLB1 SLB2 SLB3 SLB0 SLB1 SLB2 SLB3 SLBRn.SLB[3:0] SLBRn.SLB[3:0] Figure 4-5. Change lock settings directly via area #4 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 119 SLB1 to SLB2 to SLB3 SLBRn.WE[3:0] update lock bits SLB0 SLB1 SLB2 SLB3 SLBR.SLB[3:0] Figure 4-7. Change lock settings for 32-bit protected addresses Figure 4-8 shows an example that has a mixed protection size configuration: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 120 0 0 0 0 0 0 0 0 SLBR3 write access 0 0 0 0 0 0 1 1 SLBR3 SLB[3:0] WE[3:0] SLB[3:0] WE[3:0] Figure 4-10. Enable locking for protected and unprotected addresses MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 121: Access Errors
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 122: Features
Software watchdog is not available in Standby mode. As soon as out of Standby mode, the SWT behaves as in a usual “out of reset” situation. Figure 4-11 shows the operation timing diagram of the SWT. Table 4-5 describes the SWT operation after reset. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 123: External Signal Description
SWT generates a system reset on an invalid access. Otherwise, a bus error is generated. If either the HLK or SLK bits in the SWT_CR are set then the SWT_CR, SWT_TO, and SWT_WN registers are read-only. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 124: Memory Map
RIA = 1 (reset on invalid SWT access), SLK = 1 (soft lock), CSL = 1 (IRC clock source for counter), FRZ = 1 (freeze available while debugging), WEN = 0 or 1 (copied from configuration bit NVUSR0[WATCHDOG_EN]). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 125: Swt Interrupt Register (Swt_Ir)
1 SWT counter is stopped when the CPU is stopped by a debugger Watchdog Enabled. 0 SWT is disabled 1 SWT is enabled 4.2.5.3 SWT Interrupt Register (SWT_IR) The SWT_IR contains the timeout interrupt flag. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 126: Swt Timeout Register (Swt_To)
Watchdog timeout period in clock cycles. An internal 32-bit down counter is loaded with this value or 0x100, whichever is greater, when the service sequence is written or when the SWT is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 127: Swt Window Register (Swt_Wn)
(SWT_CR[SL]). To service the watchdog, the value 0xA602 followed by 0xB480 is written to the WSC field. To clear the soft lock bit (SWT_CR[SL]), the value 0xC520 followed by 0xD928 is written to the WSC field. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 128: Swt Counter Output Register (Swt_Co)
Service Key.This field is the previous (or initial) service key value used in keyed service mode. If SWT_CR[KEY] is set, the next key value to be written to the SWT_SR is (17 × SK + 3) mod 2 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 129: Functional Description
SWT_WN register. Outside of this window, service sequence writes are invalid accesses and generate a bus error or reset depending on the value of the SWT_CR[RIA] bit. For example, MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 130 Then the SWT can be disabled (SWT_CR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter is working properly. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 131: Overview
Two different Abort functions provide the ability to abort either single-channel conversion or chain conversion • Four programmable analog watchdogs with interrupt capability — Allows continuous hardware monitoring of as many as four analog input channels — Alternate analog thresholds • Auto-clock-off MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 132: Device-Specific Implementation
Several external decode signals MA[2:0] (multiplexer address) are provided for external channel selection and are available as alternate functions on GPIO. A conversion timing register for configuring different sampling and conversion times is associated to each channel type. Analog watchdogs allow continuous hardware monitoring. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 133: Functional Description
EDGE bit in the MCR. EDGE = 0 means that the start of conversion is enabled if the signal is low. If EDGE = 1, the start of conversion is enabled when the signal is high. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 134: Normal Conversion Operating Modes
In One Shot mode (MODE = 0) a sequential conversion specified in the NCMR registers is performed only once. At the end of each conversion, the digital result of the conversion is stored in the corresponding data register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 135: Injected Channel Conversion
After the last channel in the injected chain is converted, normal conversion resumes from the channel at which the normal conversion was stopped, as shown in Figure 5-3. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 136: Abort Conversion
MODE bit is set to 1, a new chain conversion is started. The EOC of the current aborted conversion is not generated but an ECH interrupt is generated to signal the end of the chain. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 137: Analog Clock Generator And Conversion Timings
 INPSAMP where ndelay is equal to 0.5 if INPSAMP is less than or equal to 0x06, otherwise it is 1. INPSAMP must be greater than or equal to 3 (hardware requirement). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 138 1 × Tck 44 × Tck 0000 1111 14 × Tck 30 × Tck 1 × Tck 45 × Tck 1111 1100 251 × Tck 30 × Tck 1 × Tck 282 × Tck MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 139: Programmable Analog Watchdog
The channel on which the analog watchdog is to be applied is selected by the THRCH field in the TRC registers. The analog watchdog is enabled by setting the corresponding THREN bit in the same register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 140: Dma Functionality
Registers) and IMR (Interrupt Mask Register) are provided in order to check and enable the interrupt request to EIC module. Interrupts can be individually enabled on a channel-by-channel basis by programming the CIMR (Channel Interrupt Mask Register). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 141: External Decode Signals Delay
“auto-clock-off” feature can be enabled by setting the ACKO bit in the MCR. When enabled, the analog clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed by the user. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 142: Register Descriptions
Threshold Control Register 3 (TRC3) 0x0000_0000 Threshold Register 0 (THRHLR0) 0x03FF_0000 Threshold Register 1 (THRHLR1) 0x03FF_0000 Threshold Register 2 (THRHLR2) 0x03FF_0000 Threshold Register 3 (THRHLR3) 0x03FF_0000 Reserved 070–094 — Conversion Timing Register 1 (CTR1) 0x0000_0203 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 143 1C0–1FC — Channel 64 Data Register (CDR64) 0x0000_0000 Channel 65 Data Register (CDR65) 0x0000_0000 Channel 66 Data Register (CDR66) 0x0000_0000 Channel 67 Data Register (CDR67) 0x0000_0000 Channel 68 Data Register (CDR68) 0x0000_0000 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 144 Reserved 220–2FC — The MPC5606S supports either 16 dedicated ADC channels (ch32 – ch47), or 15 dedicated channels (ch32 – ch41 plus ch43 – ch47) and 8 extended channels (ch64 – ch71).   When any of the extended channels is used, ch42 is irrelevant because the single pin PC[10] shares...
Page 145: Control Logic Registers
External trigger enable. This bit must be set to use external triggering to start a conversion. TRGEN 0 An external trigger cannot be used to start a conversion. 1 An external trigger can start a conversion. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 146 Analog clock frequency selector ADCLKSEL If this bit is set the AD_clk frequency is equal to ipg_clk frequency. Otherwise, it is half of ipg_clk frequency. This bit can be written in power-down only. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 147: Main Status Register (Msr)
PWDN, resetting this bit starts ADC transition to Idle mode. 0 ADC is in normal mode. 1 ADC has been requested to power down. 5.4.2.2 Main Status Register (MSR) The Main Status Register (MSR) provides status bits for the ADC. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 148 A write of any value has no effect. The read value is always 0. Auto-clock-off enable ACKO This status bit signals if the Auto-clock-off feature is on. 27–28 Reserved A write of any value has no effect. The read value is always 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 149: Interrupt Registers
End of Injected Channel Conversion interrupt (JEOC) flag JEOC It is the interrupt of the digital end of conversion for the injected channel; active when set. When this bit is set, a JEOC interrupt has occurred. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 150: Channel Pending Registers (Ceocfr[1..2])
CEOCFR2 = End of conversion pending interrupt for channel 64 to 95 (external channels) Address: Base + 0x0018 Access: User read/write W w1c Reset W w1c Reset Figure 5-8. Channel Pending Register 1 (CEOCFR1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 151: Interrupt Mask Register (Imr)
Interrupt Mask Register (IMR) The Interrupt Mask Register (IMR) contains the interrupt enable bits for the ADC. Address: Base + 0x0020 Access: User read/write Reset Reset Figure 5-10. Interrupt Mask Register (IMR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 152: Channel Interrupt Mask Register (Cimr[1..2])
CIMR2 = Enable bits for channels 64 to 95 (external channels) Address: Base + 0x0028 Access: User read/write R CIM Reset R CIM Reset Figure 5-11. Channel Interrupt Mask Register 1 (CIMR1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 153: Watchdog Threshold Interrupt Status Register (Wtisr)
0 Interrupt for channel n is disabled. 1 Interrupt for channel n is enabled. 5.4.3.5 Watchdog Threshold Interrupt Status Register (WTISR) Address: Base + 0x0030 Access: User read/write Reset Reset Figure 5-13. Watchdog Threshold Interrupt Status Register (WTISR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 154: Watchdog Threshold Interrupt Mask Register (Wtimr)
1 Interrupt is enabled. 28–31 Mask bit for the interrupt generated because the converted value is lower than the programmed MSKWDGxL lower threshold. 0 Interrupt is not enabled. 1 Interrupt is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 155: Dma Registers
0 DMA request cleared by Acknowledge from DMA controller. 1 DMA request cleared automatically before DMA occurs In this mode the DMA will not be performed. DMA global enable DMAEN 0 DMA feature disabled. 1 DMA feature enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 156: Dma Channel Select Register (Dmar[1..2])
Figure 5-17. DMA Channel Select Register 2 (DMAR2) Table 5-16. DMARn field descriptions Field Description DMAn DMA enable 0 DMA transfer for channel n is disabled. 1 Channel n is enabled to transfer data in DMA mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 157: Threshold Registers
Setting this bit inverts the behavior of the threshold output pin. Reserved Must be kept at 0. 19–24 Reserved A write of any value has no effect. The read value is always 0. 25–31 Choose the channel for threshold comparison. THRCH MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 158: Threshold Register (Thrhlr[0:3])
6–15 High threshold value for channel n. THRH 16–21 Reserved A write of any value has no effect. The read value is always 0. 22–31 Low threshold value for channel n. THRL MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 159: Conversion Timing Registers Ctr[1..2]
A write of any value has no effect. The read value is always 0. 21–22 Configuration bits for comparison phase duration. INPCMP[0:1] Reserved A write of any value has no effect. The read value is always 0. 24–31 Configuration bits for sampling phase duration. INPSAMP[0:7] MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 160: Mask Registers
CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32 Reset Figure 5-21. Normal Conversion Mask Register 1 (NCMR1) Table 5-20. Normal Conversion Mask Registers (NCMR[1..2]) field descriptions Field Description Sampling enable When set, sampling is enabled for channel n. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 161: Injected Conversion Mask Registers (Jcmr[1..2])
CH79 CH78 CH77 CH76 CH75 CH74 CH73 CH72 CH71 CH70 CH69 CH68 CH67 CH66 CH65 CH64 Reset Figure 5-23. Injected Conversion Mask Register 2 (JCMR2) Table 5-21. Injected Conversion Mask Registers (JCMR[1..2]) field descriptions Field Description Sampling enable When set, sampling is enabled for channel n. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 162: Delay Registers
0000 0 ADC clock cycle delay. 0010 1 ADC clock cycle delay. 0100 2 ADC clock cycle delay. 0110 3 ADC clock cycle delay. 5.4.8.2 Power-down Exit Delay Register (PDEDR) Reset value: 0x0000_0000 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 163 A write of any value has no effect. The read value is always 0. 24–31 Delay between the power-down bit reset and the start of conversion PDED[0:7 The power down delay is calculated as: PDED × 1/frequency of ADC clock. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 164: Data Registers
– When OWREN = 1, then OVERW flags the CDATA field overwrite status. 0 Converted data has not been overwritten. 1 Previous converted data has been overwritten before having been read. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 165 01 Data is a result of injected conversion mode. 10 Reserved. 11 Reserved. 16–21 Reserved A write of any value has no effect. The read value is always 0. 22–31 Channel 0-95 converted data. CDATA[0:9] MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 166 Analog-to-Digital Converter (ADC) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 167: Overview
The BAM provides the following features: • Locate and detect application boot code • MPC5606S in static mode if internal flash is not initialized or invalid • System can recover from Static mode only by Reset • Programmable 64-bit password protection for serial boot mode •...
Page 168: Memory Map
Functional description 6.5.1 Entering boot modes The MPC5606S detects the boot mode based on external pins and device status (see Figure 6-1). To boot either from FlexCAN or LINFlex, the device must be forced into an Alternate Boot Loader mode via the FAB (Force Alternate Boot mode) pin which must be asserted before initiating the reset sequence.
Page 169 Figure 6-1. Boot mode selection Table 6-2. Hardware configuration to select boot mode Standby-RAM Boot ID Boot mode boot flag — LINFlex — FlexCAN — valid SC (Single-chip) — not found Static mode MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 170: Reset Configuration Half Word Source (Rchw)
Boot Assist Module (BAM) 6.5.2 Reset Configuration Half Word Source (RCHW) MPC5606S flash memory is partitioned into boot sectors shown in Table 6-4. Each boot sector contains at offset 0x00 the Reset Configuration Half-Word (RCHW). Reserved BOOT_ID[0:7] RESET: Figure 6-2. Reset Configuration Half Word (RCHW) Table 6-3.
Page 171: Single-Chip Boot Mode
Boot information $0000 0008 Application start address $0000 0004 RCHW $0000 0000 Boot information $0000 0000 Internal flash memory Figure 6-3. MPC5606S flash memory partitioning and RCHW search Table 6-4. Flash boot sector Block Address 0x0000_0000 0x0000_8000 0x0000_C000 0x0001_0000 0x0001_8000 6.5.3...
Page 172: Boot And Alternate Boot
Then the device executes this startup code. A user application should have a valid instruction at the reset boot vector address. If a valid RCHW is not found, the BAM code is executed. In this case BAM moves the MPC5606S into static mode.
Page 173: Bam Software Flow
BAM pushes the device into static mode. In all other cases the code of the relative boot is called. Data is downloaded and saved into the proper SRAM location. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 174: Bam Resources
Table 6-6). Table 6-6. Serial Boot mode without autobaud—baud rates Crystal frequency LINFlex baud rate CAN bit rate (MHz) (baud) (bit/s) / 833 / 40 extal extal extal 9600 200K 14400 300K MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 175: Download And Execute The New Code
In case of flash memory with public access, the received password is compared with the public password 0xFEED_FACE_CAFE_BEEF. 1. Since this device supports only VLE code and it does not support Book E code, this flag is used only for backward compatibility. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 176: Download Start Address, Vle Bit And Code Size
The VLE bit (Variable Length Instruction) is used to indicate for which instruction set the code has been compiled. This device family supports only VLE = 1. This bit is used for backward compatibility. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 177: Download Data
Then it restores the initial MCU configuration and jumps to the loaded code at the start address received in step 2 of the protocol. At this point, the BAM has finished its tasks and the MCU is controlled by new code executing from SRAM. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 178: Boot From Uart
SRAM starting from the “Load address”. “Load address” increments until the amount of data received and stored matches the size as specified in the previous step. None None Branch to downloaded code. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 179: Bootstrap With Can
Time Segment 1 Time Segment 2 time quantum time quanta time quanta 1 Bit Time Sample Point Transmit Point 1 time quantum = 4 system clock periods Figure 6-8. FlexCAN Bit Timing MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 180: Protocol
When the chip uses the BAM to boot using FlexCAN or UART, the required flash memory password is different depending on whether the flash memory is secured or unsecured. This difference affects how you must program the NVPWD0, NVPWD1, NVSCI0, and NVSCI1 registers. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 181: Interrupts
NVSCI1 = 0x55AA55AA To download the code via serial boot, the provided password is 0x8765_4321_1234_5678 (NVPWD0 followed by NVPWD1). 6.6.2 Interrupts No interrupts are generated by or are enabled by the BAM. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 182 Boot Assist Module (BAM) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 183: Introduction
After completion, software has to process the sampled data in order to rebuild the 48 minimal bits. Base Identifier (11-bit) Extended Identifier (18-bit) Data Length Code RTR-bit IDE-bit Figure 7-1. Extended CAN data frame MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 184: Main Features
The initialization data is unknown. They will be filled only after first CAN sampling. 7.3.1 CAN Sampler Control Register Address Offset: 0x00 Reset value: 0000 0000h Activ PLET e_CK CAN_RX_SEL PLR_ Figure 7-2. Control Register (CR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 185: Can Sampler Sample Registers 0–11
CAN_SMPLER_EN = 1. 7.3.2 CAN Sampler Sample Registers 0–11 The CAN Sampler sample registers 0–11 have the same structure; Figure 7-3 Figure 7-4 show this structure for registers 0 and 11, respectively. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 186: Functional Description
It then waits for the first low pulse on the Rx line, taking it as a valid Start of Frame (SOF) of the second frame. The sampler takes 384 samples (48 bytes × 8) using the RC clock (configuring 8 samples per MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 187: Enabling/Disabling The Can Sampler
One Rx port can be selected per sampling routine; the port to be sampled is selected by CAN_RX_SEL. Table 7-3. Internal multiplexer correspondence CAN_RX_SEL Rx selected CANRX_0 PB[1] CANRX_1 PB[10] CANRX_2 PF[13] CANRX_3 PJ[4] CANRX_4 PJ[6] Reserved Reserved Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 188: Baud Rate Generation
= 8 µs Eqn. 7-1 To achieve 8 samples per bit: Sample period= 8/8 µs = 1 µs BRP = 1 µs/62.5 ns = 16. Thus in this case, BRP = 01111. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 189: Clock Architecture
Clock Description Chapter 8  Clock Description This chapter describes the clock architectural implementation for MPC5606S. Clock architecture System clocks are generated from three sources: • External oscillator FXOSC (4–16 MHz) • High speed internal RC (16 MHz) • FMPLL0 clocked by FXOSC, still one of system clock sources Additionally, there are two low-power oscillators: •...
Page 190: Auxiliary Clocks
PLL1_Clk Figure 8-1. MPC5606S system clock generation Auxiliary clocks This device has four auxiliary clocks configurable using the MC_CGM registers. These auxiliary clocks allow the associated peripherals to operate at clock speeds independent of the system clock (sys_clk). The peripherals also use the undivided system clock to synchronously interface with the rest of the device.
Page 191: Clock Gating
• Auxiliary Clock 3: QuadSPI (uses undivided system clock when in DSPI mode) Clock gating The MPC5606S provides the user with the possibility of gating the clock to certain peripherals. See Section 25.4.6, Peripheral clock gating, for details. Peripherals sets 1, 2, and 3, and the DCU, eMIOS, and QuadSPI peripherals can be configured to use specific clocks.
Page 192: Clock Generation Module (Mc_Cgm)
The memory spaces of system and peripheral clock sources that have addressable memory spaces are accessed through the MC_CGM memory space. The MC_CGM also selects and generates an output clock. Figure 8-2 depicts the MC_CGM block diagram. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 193: Features
Contains a set of registers to control clock dividers for divided clock generation • Contains a set of registers to control peripheral clock selection • Supports multiple clock sources and maps their address spaces to its memory map • Generates an output clock MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 194: Modes Of Operation
Aux Clock 3 Select Control word read/write NOTE Any access to unused registers as well as write accesses to read-only registers will: • Not change register content • Cause a transfer error MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 195 FMPLL1 registers 0xC3FE_00DC 0xC3FE_00E0 … Reserved 0xC3FE_00FC 0xC3FE_0100 … CMU0 registers 0xC3FE_011C 0xC3FE_0120 … Reserved 0xC3FE_013C 0xC3FE_0140 … Reserved 0xC3FE_015C 0xC3FE_0160 … Reserved 0xC3FE_017C 0xC3FE_0180 … Reserved 0xC3FE_019C 0xC3FE_01A0 … Reserved 0xC3FE_01BC MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 196 0xC3FE_0280 … Reserved 0xC3FE_029C 0xC3FE_02A0 … Reserved 0xC3FE_02BC 0xC3FE_02C0 … Reserved 0xC3FE_02DC 0xC3FE_02E0 … Reserved 0xC3FE_02FC 0xC3FE_0300 … Reserved 0xC3FE_031C 0xC3FE_0320 … Reserved 0xC3FE_033C 0xC3FE_0340 … Reserved 0xC3FE_035C 0xC3FE_0360 … Reserved 0xC3FE_036C MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 197 Table 8-3. MC_CGM Memory map (continued) Address Name 0xC3FE_0370 CGM_OC_EN 0xC3FE_0374 CGM_OCDS_SC SELDIV SELCTL 0xC3FE_0378 CGM_SC_SS SELSTAT 0xC3FE_037C CGM_SC_DC0…2 DIV0 DIV1 DIV2 0xC3FE_0380 CGM_AC0_SC SELCTL 0xC3FE_0384 Reserved 0xC3FE_0388 CGM_AC1_SC SELCTL 0xC3FE_038C CGM_AC1_DC0 DIV0 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 198: Register Descriptions
Output Clock Enable Register (CGM_OC_EN) Address 0xC3FE_0370 Access: Supervisor read/write, User read-only Reset Reset Figure 8-3. Output Clock Enable Register (CGM_OC_EN) This register is used to enable and disable the output clock. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 199 000 16 MHz internal RC oscillator 001 4–16 MHz external oscillator 010 Primary FMPLL 011 Secondary FMPLL 100 128 kHz internal RC oscillator 101 32 kHz external oscillator 110 reserved 111 reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 200 1111 System clock is disabled 8.4.3.1.4 System Clock Divider Configuration Registers (CGM_SC_DC0…2) Address 0xC3FE_037C Access: Supervisor read/write, User read-only DIV0 DIV1 Reset DIV2 Reset Figure 8-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 201 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Address 0xC3FE_0380 Access: Supervisor read/write, User read-only SELCTL Reset Reset Figure 8-7. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) This register is used to select the current auxiliary clock 0 sources. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 202 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Address 0xC3FE_0388 Access: Supervisor read/write, User read-only SELCTL Reset Reset Figure 8-8. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) This register is used to select the current auxiliary clock 1 sources. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 203 Divider 0 Division Value — The resultant eMIOS0 clock will have a period DIV0 + 1 times that of auxiliary clock 1. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV 0 field is ignored and the eMIOS0 clock remains disabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 204 1101 reserved 1110 reserved 1111 reserved 8.4.3.1.9 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Address 0xC3FE_0394 Access: Supervisor read/write, User read-only DIV0 Reset Reset Figure 8-11. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 205 0010 Secondary FMPLL 0011 Secondary FMPLL / 2 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 206: Functional Description
Section 8.4.3.1.6, Auxiliary Clock 1 Select Control Register (CGM_AC1_SC), Section 8.4.3.1.8, Auxiliary Clock 2 Select Control Register (CGM_AC2_SC), and Section 8.4.3.1.10, Auxiliary Clock 3 Select Control Register (CGM_AC3_SC), for auxiliary clock selection control. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 207 MC_RGM safe clock request MC_ME clock select CGM_SC_DC1 Register CGM_SC_SS Register peripheral set 2 clock clock divider CGM_SC_DC2 Register peripheral set 3 clock clock divider Figure 8-13. MC_CGM System Clock Generation Overview MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 208 4–16 MHz external oscillator div. 16 MHz int. RC osc. Secondary FMPLL Primary FMPLL unused CGM_AC1_DC0 Register clock divider eMIOS0 clock CGM_AC1_SC Register Figure 8-15. MC_CGM Auxiliary Clock 1 Generation Overview MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 209 Auxiliary Clock Source Selection During normal operation, the auxiliary clock selection is done via the CGM_AC0…3_SC registers. If software selects an unavailable source, the old selection remains, and the register content does not change. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 210: Output Clock Multiplexing
The non-divided signal is not guaranteed to be 50% duty cycle by the MC_CGM. • The MC_CGM also has an output clock enable register (see Section 8.4.3.1.1, Output Clock Enable Register (CGM_OC_EN)), which contains the output clock enable/disable control bit. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 211: Fxosc External Oscillator
CK_OSCM OSC MODE No crystal, No crystal, Power down, high high IDDQ impedance impedance Ext clock EXTAL Bypass, OSC disabled Crystal Crystal EXTAL Normal, OSC enabled Ext clock EXTAL Normal, OSC enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 212: Register Description
This bit is set by hardware when OSCCNT counter reaches the count value EOCV[7:0] × 512. It is cleared by software by writing 1. 0 No oscillator clock interrupt occurred. 1 Oscillator clock interrupt pending. Note: OSC_CTL register is writable only in supervisor mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 213: Khz Osc Digital Interface
CK_OSCM OSC MODE No crystal, No crystal, Power down, IDDQ high Z high Z Ext clock EXTAL32 Bypass, OSC disabled Crystal Crystal EXTAL32 Normal, OSC enabled Ext clock EXTAL32 Normal, OSC enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 214: Register Description
This bit is set by hardware when the OSCCNT counter reaches the count value of EOCV[7:0] × 512. It is cleared by writing a 1. 0 No oscillator clock interrupt occurred. 1 Oscillator clock interrupt pending. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 215: Sirc Digital Interface
These bits can be programmed to modify an internal capacitor/resistor. After power-on reset, the trimming bits are provided by the flash options. After the first write access, only the value specified by the LPRCTRIM[4:0] bits will control the trimming. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 216: Register Description
Low-power RC trimming bits 11–15 LPRCTRIM[4:0] Note: Not all configurations can be used. Please refer to the MPC5606S . Low-power RC clock division factor 19–23 These bits specify the low-power RC oscillator output clock division factor. The output clock is LPRCDIV[4:0] divided by the factor LPRCDIV + 1.
Page 217: Register Description
Description 10–15 Low-power RC trimming bits RCTRIM[5:0 Note: Not all configurations can be used. Please refer to the MPC5606S . 19–23 Low-power RC clock division factor RCDIV[4:0] These bits specify the low-power RC oscillator output clock division factor. The output clock is divided by the factor LPRCDIV + 1.
Page 218: Overview
— Programmable modulation frequency dependent on reference frequency • Self-clocked mode (SCM) operation • Five available modes — Normal mode — Progressive clock switching — Normal mode with FM — Power-down mode — 1:1 mode (FMPLL0 only) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 219: Memory Map
Offset 0x0000 Access: User read/write NDIV Reset unloc pll_fa i_loc s_loc pll_fa k_on il_fla en_pl il_ma l_sw Reset 1 Reset value is determined by the SoC integration. Figure 8-24. Control Register (CR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 220 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 221 Divide by 16 Table 8-24. Loop divide ratios NDIV[6:0] loop divide ratios 0000000–0011111 0100000 Divide by 32 0100001 Divide by 33 0100010 Divide by 34 1011111 Divide by 95 1100000 Divide by 96 1100001–1111111 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 222: Modulation Register (Mr)
The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following formula: ------------------- - modperiod  where: : represents the frequency of the feedback divider : represents the modulation frequency The maximum value of MOD_PERIOD is 0x1000. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 223: Functional Description
Table 8-26 Figure 8-26. Table 8-26. Progressive clock switching on pll_select rising edge Number of PLL output clock cycles ck_pll_frequency (PLL output clock frequency) (ck_pll_out frequency)/8 (ck_pll_out frequency)/4 (ck_pll_out frequency)/2 onward (ck_pll_out frequency) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 224: Normal Mode With Frequency Modulation
  MDF  – NOTE You must ensure that the value of MODPERIOD does not exceed 0x1000 and that the product of INCTEP and MODPERIOD is less than (2 – 1). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 225: Powerdown Mode
FM modulated mode. Then strobe has to be generated to enable the new settings. If STRB_BYP is set to 1 then MOD_PERIOD, INC_STEP and SPREAD_SEL can be modified only when PLL is in power-down mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 226: Clock Monitor Unit (Cmu)
Figure 8-28. CMU component interaction 8.10.2 Main features • RC oscillator frequency measurement • External oscillator clock monitoring with respect to CK_FIRC/n clock • PLL clock frequency monitoring with respect to CK_FIRC/4 clock MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 227: Block Diagram
CK_PLL: clock from the PLL • FOSC: frequency of external crystal oscillator clock • FRCslow: frequency of low-frequency internal RC oscillator • FRCfast: frequency of high-frequency internal RC oscillator • FPLL: frequency of FMPLL clock MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 228: Crystal Clock Monitor
20 bits. The SFM bit is reset to 0 by the hardware once the frequency measurement is done and the count is loaded in the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 229: Memory Map And Register Description
0 1 2 3 4 5 6 7 8 9 Offset Name CMU_ Reserved Reserved Reserved CMU_ Reserved FD[12:31] CMU_ Reserved HFREF HFREFR CMU_ Reserved LFREF LFREFR CMU_ISR Reserved Reserved Reserved CMU_ Reserved MD[12:31] Table 8-28. CMU register map MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 230: Control Status Register (Cmu_Csr)
00 Clock divided by 1 (No division) 01 Clock divided by 2 10 Clock divided by 4 11 Clock divided by 8 FMPLL0 clock monitor enable CME_A 0 FMPLL0 monitor is disabled. 1 FMPLL0 monitor is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 231: Frequency Display Register (Cmu_Fdr)
Table 8-31. High Frequency Reference Register FMPLL0 field descriptions Field Description 20–31 High Frequency reference value HFREF These bits determine the high reference value for the FMPLL0 clock. The reference value is given by: (HFREF[11:0]/16) × (FRC /4). fast MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 232: Low Frequency Reference Register Fmpll0 (Cmu_Lfrefr)
This bit is set by hardware when CK_FMPLL frequency becomes higher than HFREF value and CK_FMPLL is on as signaled by the MC_ME. It can be cleared by software by writing 1. 0 No FHH event. 1 FHH event is pending. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 233: Measurement Duration Register (Cmu_Mdr)
This register displays the measured duration in terms of IRC clock cycles. This value is loaded in the frequency meter down counter. When SFM bit is set to 1, down counter starts counting. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 234 Clock Description MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 235: Device-Specific Information
— Unified Channels 9–15 do not have their own time base • For eMIOS200_1: — Counter bus A is driven by Unified Channel #23 — Counter bus D is driven by Unified Channel #16 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 236: Emios Clocking Configuration
Non-modulated clock Figure 9-1. eMIOS clocking configuration 9.1.4 MPC5606S family comparison The following table shows the required split of eMIOS channel functionality across the MPC5606S family as a function of flash memory size. Table 9-1. eMIOS total channel summary 256 KB...
Page 237 Counter GPIO General Purpose Input/Output SAIC Single Action Input Capture SAOC Single Action Output Compare Modulus Counter Buffered OPWFMB Output Pulse Width and Frequency Modulation Buffered OPWMB Output Pulse Width Modulation Buffered MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 238: Unified Channel Block
2. Goes to the FSM of the UC[n-1]. These signals are used for QDEC mode. Figure 9-2. Unified Channel block 9.1.6.1 Channel mode selection The following is a portion of eMIOS200 UC Control Register (EMIOSC[n]). Please see Section 9.4.2.8, eMIOS200 UC Control Register (EMIOSC[n]). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 239: Introduction
1111111 b = adjust parameters for the mode of operation. Refer to Section 9.5.1.1, UC modes of operation, for details. Introduction Figure 9-4 shows the block diagram of the configurable eMIOS200 block. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 240 QDEC mode Input[0:3] Figure 9-4. eMIOS200 block diagram 1.This diagram shows a 24-channel eMIOS200. On MPC5606S, eMIOS200_0 has 16 channels (8–23) and eMIOS200_1 has 8 channels (16–23). Thus, not all channels shown are available. MPC5606S Microcontroller Reference Manual, Rev. 7...
Page 241: Overview
Single Action Input Capture (SAIC) • Single Action Output Compare (SAOC) • Modulus Counter Buffered (MCB) • Output Pulse Width and Frequency Modulation Buffered (OPWFMB) • Output Pulse Width Modulation Buffered (OPWMP) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 242: External Signal Description
— eMIOS200 Channel Flag Signal emios_flag_out[n] outputs the state of F[n] bit of the EMIOSGFLAG register. Memory map and register description 9.4.1 Memory map The overall address map organization is shown in Table 9-7. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 243: Unified Channel Memory Map
Table 9-8. Unified Channel memory map UC[n] base address Description A register (EMIOSA[n]) 0x00 B register (EMIOSB[n]) 0x04 Counter register (EMIOSCNT[n]) 0x08 0x0C Control register (EMIOSC[n]) 0x10 Status register (EMIOSS[n]) 0x14 Alternate A register (EMIOSALTA[n]) 0x18–0x1F Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 244: Register Description
0 Prescaler disabled (no clock) and prescaler counter is cleared 1 Prescaler enabled GPRE Global Prescaler The GPRE[0:7] bits select the clock divider value for the global prescaler, as shown in Table 9-10. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 245: Emios200 Global Flag Register (Emiosgflag)
For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register. Address: eMIOS0 base address +0x04 Access: User read-only Reset R F15 Reset Figure 9-6. eMIOS200 Global FLAG Register (EMIOSGFLAG) for EMIOS0 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 246: Emios200 Output Update Disable (Emiosoudis)
The two modules on this device, EMIOS0 and EMIOS1, have different structures for this register as shown Figure 9-8 Figure 9-9. Address: eMIOS0 base address +0x08 Access: User read/write Reset R OU Reset Figure 9-8. eMIOS200 Output Update Disable Register (EMIOSOUDIS) for EMIOS0 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 247: Emios200 Disable Channel (Emiosucdis)
Address: eMIOS0 base address +0x0C Access: User read/write CHDI CHDI CHDI CHDI CHDI CHDI CHDI CHDI Reset R CHDI CHDI CHDI CHDI CHDI CHDI CHDI CHDI Reset Figure 9-10. eMIOS200 Enable Channel Register (EMIOSUCDIS) for EMIOS200_0 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 248: Emios200 Uc A Register (Emiosa[N])
EMIOSA[n]. Both A1 and A2 are cleared by reset. Table 9-14 summarizes the EMIOSA[n] read and write accesses for all operation modes. For more information, see section Section 9.5.1.1, UC modes of operation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 249: Emios200 Uc B Register (Emiosb[N])
A1, A2 B1, B2 SAIC — — — SAOC — — — — OPWFMB — — OPWMB — — In these modes, the EMIOSB[n] register is not used, but B2 can be accessed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 250: Emios200 Uc Counter Register (Emioscnt[N])
UC Control Register (EMIOSC[n]) The Control register gathers bits reflecting the status of the UC input/output signals and the overflow condition of the internal counter, as well as several read/write control bits. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 251 The IF[0:3] bits control the programmable input filter, selecting the minimum input pulse width that can pass through the filter, as shown in Table 9-18. For output modes, these bits have no meaning. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 252 For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 0 The EDPOL value is transferred to the output flip-flop 1 The output flip-flop is toggled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 253 Output Disable Input 0 emios_flag_out[9] emios_flag_out[17] Output Disable Input 1 emios_flag_out[10] emios_flag_out[18] Output Disable Input 2 emios_flag_out[11] emios_flag_out[19] Output Disable Input 3 Table 9-17. UC internal prescaler clock divider UCPRE[0:1] Divide ratio MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 254 Reserved 10111b1 Reserved 11000b0 Output Pulse Width Modulation Buffered 1100001 through 1111111 Reserved b = adjust parameters for the mode of operation. Refer to Section 9.5.1.1, UC modes of operation, for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 255: Emios200 Uc Status Register (Emioss[N])
FLAG bit value. When DMA bit is set, the FLAG bit can be cleared by the DMA controller. 9.4.2.10 eMIOS200 UC Alternate A Register (EMIOSALTA[n]) EMIOSALTA[n] address: UC[n] base address + 0x14 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 256: Functional Description
32 Unified Channels. Note that the Red Line is also present. Note also that independent of the configuration the channels are fixed in their slots. Thus MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 257 EMIOS[16] bus [C] channel[15] EMIOS[15] channel[8] EMIOS[8] bus [B] Global system clock Prescaler channels channel[7] EMIOS[7] channel[0] EMIOS[0] output disable inputs[3:0] Figure 9-18. eMIOS200 full channel configuration using Unified Channels only MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 258: Unified Channel (Uc)
The unused gates are removed during the synthesis phase. Targeting the logic optimization, a set of registers is shared by the modes, thus providing sequential events to be stored. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 259: Uc Modes Of Operation
EMIOSC[n] register (see Figure 9-20 for details). When entering an output mode (except for GPIO mode), the output flip-flop is set to the disabled state according to the ODIS bit in the EMIOSC[n] register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 260 The input capture is triggered by a rising, falling, or either edge on the input pin, as configured by the EDPOL and EDSEL bits in the EMIOSC[n] register. Figure 9-21 Figure 9-22 show how the Unified Channel can be used for input capture. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 261 A1 must be written before the mode is entered. A1 register can be updated at any time, thus modifying the match value which will be reflected in the output signal generated by the channel. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 262 Register A1 is double-buffered, thus allowing smooth transitions between cycles when changing the value of the A2 register on the fly. The A1 register is updated at the cycle boundary, which is defined as when the internal counter transitions to 0x1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 263 0x1 in cycle n + 1. Note that the FLAG is generated at the cycle boundary and has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 264 + 1, and the new value is used for match at cycle n + 1. The update disable bits OU[n] of the EMIOSOUDIS register can be used to control the update of this register, thus allowing delay of the A1 register update for synchronization purposes. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 265 0% and 100% duty cycles are supported. At OPWFMB mode entry, the output flip-flop is set to the value of the EDPOL bit in the EMIOSC[n] register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 266 B1 negative edge match signal from cycle n. This allows using the A1 positive edge match to mask the B1 negative edge match when they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 267 B2 data written on cycle n were loaded to A1 or B1, respectively, thus generating matches in cycle n + 1. Note that the FLAG has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 268 A1 match. In this case, EDPOL should be set to 0. Note that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 269 A1 match; thus the output flip-flop is set to the complement of the EDPOL bit. This cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater than or equal to B1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 270 Any value written to A2 or B2 on cycle n is loaded to the A1 and B1 registers at the following cycle boundary (assuming the OU[n] bit of EMIOSOUDIS register is not asserted). Thus, the new values will be used for A1 and B1 matches in cycle n + 1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 271 B1 = 0x8 negative edge signal. In this case, the A1 match has precedence over the B1 match, causing the output pin to remain at the EDPOL bit value, thus generating a 0% duty cycle signal. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 272 Disable allows the output pin to transition at the next A1 or B1 match. Note that the Output Disable does not modify the FLAG bit behavior. Note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to EDPOL. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 273: Input Programmable Filter (Ipf)
Input Programmable Filter (IPF) The IPF ensures that only valid input pin transitions are received by the Unified Channel edge detector. A block diagram of the IPF is shown in Figure 9-38. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 274: Clock Prescaler (Cp)
In order to ensure safe operation and avoid glitches, the following steps must be performed whenever any update in the prescaling rate is desired: 1. Write 0 at both the GPREN bit in the EMIOSMCR register and the UCPREN bit in the EMIOSC[n] register, thus disabling prescalers. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 275: Effect Of Freeze On The Unified Channel
2. Write the desired value for the prescaling rate to the GPRE[0:7] bits in the EMIOSMCR register. 3. Enable global prescaler by writing 1 to the GPREN bit in the EMIOSMCR register. The prescaler is not disabled during freeze state. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 276: Effect Of Freeze On The Gcp
For the OPWFM with internal clock source operation mode, the internal counter rate can be modified by configuring the clock prescaler ratio. Figure 9-40 shows an example of a time base with prescaler ratio equal to one. NOTE MCB and OPWFMB modes have different behavior. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 277 Note 1: When a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge of prescaler clock enable the counter will start counting. Figure 9-41. Time base generation with external clock and clear on match start MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 278: Coherent Accesses
GPIO mode: 1. [global] Disable the Global Prescaler. 2. [timebase channel] Disable the Channel Prescaler. 3. [timebase channel] Write the initial value to the internal counter. 4. [timebase channel] Set A/B register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 279 The timebase channel and the output channel may be the same for some applications such as in OPWFM(B) mode or whenever the output channel is intended to run the timebase itself. The flags can be configured at any time. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 280 Configurable Enhanced Modular IO Subsystem (eMIOS200) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 281: Introduction
This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections between four master ports and four slave ports. A port splitter allows three of the MPC5606S slaves to be consolidated on one slave port. XBAR supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports.
Page 282: Features
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep arbitration delays to a minimum. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 283: General Operation
If the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 284: Slave Ports
(if any). The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 285 When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. All other masters pay a one clock penalty. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 286 Crossbar Switch (XBAR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 287: Introduction
DMA and interrupt control TX FIFO RX FIFO TX data RX data Shift register SOUT_x SIN_x SCK_x SPI baud rate, CS0_x delay and transfer CS1:4_x control CS5_x Figure 11-1. DSPI block diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 288: Overview
Buffered transmit and receive operation using the TX and RX FIFOs, with depths of five entries • Visibility into TX and RX FIFOs for ease of debugging • FIFO bypass mode for low-latency updates to SPI queues MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 289: Modes Of Operation
Master mode allows the DSPI to initiate and control serial communication. In this mode, the SCK and CSn signals are controlled by the DSPI and configured as outputs. (SOUT is always an output.) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 290: Slave Mode
FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by the module-specific mode and configuration of the DSPI. For more information, refer to Section 11.8.1.5, Debug mode. 11.6 External signal description 11.6.1 Signal overview Table 11-1 lists off-chip DSPI signals. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 291: Signal Names And Descriptions
SOUT_x is a serial data output signal. 11.6.2.5 Serial Clock (SCK_x) SCK_x is a serial communication clock signal. In Master mode, the DSPI generates the SCK. In Slave mode, SCK_x is an input from an external bus master. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 292: Memory Map And Register Description
Base + 0x0084 DSPIx_RXFR2 DSPI Receive FIFO Register 2 on page 306 Base + 0x0088 DSPIx_RXFR3 DSPI Receive FIFO Register 3 on page 306 Base + 0x008C– — Reserved — Base + 0x00CC MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 293: Register Description
Modified timing format enable. Enables a modified transfer format to be used. Refer to MTFE Section 11.8.5.4, Modified SPI transfer format (MTFE = 1, CPHA = 1), for more information. 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 294 00 DSPI samples SIN at driving SCK edge. [0:1] 01 DSPI samples SIN one system clock after driving SCK edge. 10 DSPI samples SIN two system clocks after driving SCK edge. 11 Reserved. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 295: Dspi Transfer Count Register (Dspix_Tcr)
The DSPI modules each contain eight clock and transfer attribute registers (DSPIx_CTARn) which are used to define different transfer attribute configurations. Each DSPIx_CTAR controls: • Frame size • Baud rate and transfer delay values MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 296 Enable nor the Modified Timing Format Enable bits should be set. 0 The baud rate is computed normally with a 50/50 duty cycle 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 297 PCS and the first edge of the SCK. This field is used only in Master mode. The table below lists the prescaler values. See the CSSCK[0:3] field description for details on how to compute the PCS to SCK Delay. PCSSCK PCS to SCK delay prescaler value MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 298 PCS to SCK Delay is a multiple of the system clock period and it is computed according to the following equation:   Eqn. 11-1 ---------- - PCSSCK CSSCK MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 299 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 Table 11-7. DSPI Transfer frame size FMSZ Frame size FMSZ Frame size 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 300 32768 0111 1111 65536 Table 11-10. DSPI delay after transfer scaler Delay after transfer scaler value Delay after transfer scaler value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 301: Dspi Status Register (Dspix_Sr)
DSPIx_SR by writing a 1 to clear (w1c). Writing a 0 to a flag bit has no effect. Address: Base + 0x002C Access: User read/write TXRX TFFF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset DSPI Status Register (DSPIx_SR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 302 RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred Reserved. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 303 Do not write to the DSPIx_RSER while the DSPI is running. Address: Base + 0x0030 Access: User read/write TFFF RFDF TCF_ TFFF DIRS DIRS Reset Reset Figure 11-6. DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 304 RFDF_RE The RFDF_DIRS bit selects between generating an interrupt request or a DMA request. 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 305: Dspi Push Tx Fifo Register (Dspix_Pushr)
Write accesses of 8 or 16 bits to the DSPIx_PUSHR transfer 32 bits to the TX FIFO. NOTE TXDATA is used in Master and Slave modes. Address: Base + 0x0034 Access: User read/write R CON CTAS Reset TXDATA Reset Figure 11-7. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 306 1 Assert the CSx signal Note: Use in SPI Master mode only. 16–31 Transmit data. Holds SPI data for transfer according to the associated SPI command. TXDATA Note: Use TXDATA in Master and Slave modes. [0:15] MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 307: Dspi Pop Rx Fifo Register (Dspix_Popr)
TX FIFO. The registers are read-only and cannot be modified. Reading the DSPIx_TXFRn registers does not alter the state of the TX FIFO. The MCU uses four registers to implement the TX FIFO: DSPIx_TXFR0–DSPIx_TXFR3. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 308: Dspi Receive Fifo Registers 0–4 (Dspix_Rxfrn)
RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO: DSPIx_RXFR0–DSPIx_RXFR3. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 309: Functional Description
Because the registers are linked, data is exchanged between the master and the slave; the data that was in the master’s shift register is now in the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 310: Modes Of Operation
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPIx_CTARs are used to set the transfer attributes. Transfer attribute control is on a frame-by-frame basis. Refer to Section 11.8.3, Serial Peripheral Interface (SPI) configuration, for more details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 311: Slave Mode
DSPIx_SR is cleared in this state. In the Running state, serial transfers take place. The TXRXS bit in the DSPIx_SR is set in the Running state. Figure 11-12 shows a state diagram of the start and stop mechanism. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 312: Serial Peripheral Interface (Spi) Configuration
The SPI configuration supports two module-specific modes; Master mode and Slave mode. The FIFO operations are similar for the Master mode and Slave mode. The main difference is that in Master mode MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 313: Spi Master Mode
SPI commands and data are added to the TX FIFO by writing to the DSPI push TX FIFO register (DSPIx_PUSHR). For more information on MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 314: Receive First In First Out (Rx Fifo) Buffering Mechanism
RX FIFO. SPI data is removed (popped) from the RX FIFO by reading the DSPIx_POPR register. RX FIFO entries can only be removed from the RX FIFO by reading the DSPIx_POPR or by flushing the RX FIFO. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 315: Dspi Baud Rate And Clock Delay Generation
Figure 11-13 shows conceptually how the SCK signal is generated. 1 + DBR System Clock SCK_x Prescaler Scaler Figure 11-13. Communications clock prescalers and scalers MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 316: Baud Rate Generator
SCK_x delay. The PASC and ASC fields in the DSPIx_CTARn registers select the after SCK delay. The relationship between these variables is given in the following formula:   PASC MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 317 Table 11-23 shows an example of how to compute the delay after transfer with the clock period of SCK defined as T . The values calculated assume 1 TSCK period = 4 ipg_clk. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 318: Transfer Formats
Even though the bus slave does not control the SCK signal, the clock polarity, clock phase, and number of bits to transfer must be identical for the master device and the slave device to ensure proper transmission. The DSPI supports four different transfer formats: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 319 Section 11.8.5.4, Modified SPI transfer format (MTFE = 1, CPHA = In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames. Refer to Section 11.8.5.5, Continuous selection format, for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 320: Classic Spi Transfer Format (Cpha = 0)
For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 11-14. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 321: Classic Spi Transfer Format (Cpha = 1)
For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of Figure 11-15. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 322: Modified Spi Transfer Format (Mtfe = 1, Cpha = 0)
Table 11-24. Delayed master sample point Number of system clock cycles between SMPL_PT odd-numbered edge of SCK and sampling of SIN Invalid value MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 323: Modified Spi Transfer Format (Mtfe = 1, Cpha = 1)
SCK. No clock edge is visible on the master SCK pin during the sampling of the last bit. The SCK to CS delay must be greater or equal to half of the SCK period. NOTE For the modified transfer format to operate correctly, analyze the SPI link timing budget thoroughly. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 324: Continuous Selection Format
Master SOUT Master SIN = CS to SCK delay. = After SCK delay. = Delay after transfer (minimum CS negation time). Figure 11-18. Example of non-continuous format (CPHA = 1, CONT = 0) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 325: Clock Polarity Switching Between Dspi Transfers
TX FIFO is completely transmitted (that is, the corresponding TCF flag is asserted and TX FIFO is empty), the slave should be de-selected for any further serial communication. Otherwise, an underflow error occurs. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 326: Continuous Serial Communications Clock
DSPIx_CTARn changes between frames except DSPIx_CTARn[PBR]. • When in Continuous SCK mode, CTAR0 should always be used for the SPI transfer, and the TX FIFO must be clear using the MCR[CLR_TXF] field before initiating transfer. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 327 SCK format with continuous selection enabled. (CPOL = 0) (CPOL = 1) Master SOUT Master SIN Transfer 1 Transfer 2 Figure 11-22. Continuous SCK timing diagram (CONT=1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 328: Interrupts/Dma Requests
TCF_RE bit is set in the DSPIx_RSER. Refer to the TCF bit description in Section 11.7.2.4, DSPI Status Register (DSPIx_SR). Refer to Figure 11-14 Figure 11-15 that illustrate when TCF is set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 329: Transmit Fifo Underflow Interrupt Request (Tfuf)
The states of the interrupt and DMA request signals cannot be changed while in External Stop mode. Implementation of IPI Green Line Stop mode in an SoC is optional. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 330: Module Disable Mode
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPIx_MCR register and flush the RX FIFO by writing a 1 to the CLR_RXF bit in the DSPIx_MCR register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 331: Baud Rate Settings
3.12 kHz 2.23 kHz 4096 3.90 kHz 2.60 kHz 1.56 kHz 1.11 kHz 8192 1.95 kHz 1.31 kHz 781 Hz 558 Hz 16384 979 Hz 653 Hz 390 Hz 279 Hz 32768 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 332: Delay Settings
The pointer to the first-in entry in each FIFO is memory-mapped. For the TX FIFO the first-in pointer is the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer (POPNXTPTR). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 333 Last-in entry address = RXFIFO base + 4 [(RXCTR + POPNXTPTR – 1) modulo RXFIFO depth] where: RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter POPNXTPTR = pop next pointer MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 334 Deserial Serial Peripheral Interface (DSPI) RX FIFO depth = receive FIFO depth, implementation specific MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 335: Introduction
CPU intervention. Graphics may be encoded in a variety of formats to optimize memory usage. The DCU also has the capability of displaying real-time video from an external video source. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 336: Overview
DCU that fetch the graphic and video content and drive the TFT LCD panel. The upper section describes the user interface through which the user configures the graphical content of the TFT LCD panel. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 337: Features
Programmable panel size up to a maximum of Wide VGA (800 x 480) • Gamma correction with 8-bit resolution on each color component • Safety mode for tagging pixels on highest priority layers MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 338: Modes Of Operation
The DCU has up to 22 input signals and up to 30 output signals. See Figure 12-2. The choice of signals used depends on the configuration of the DCU. All active signals must be enabled by configuring the appropriate PCR registers in the SIUL module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 339: Detailed Signal Descriptions
When high, this signal indicates that the pixel is tagged and an application can calculate CRC externally on this pixel. dcu_de Data Enable. Qualifies the data output (dcu_ld) dcu_r[7:0], Red, green and blue data output. dcu_g[7:0], dcu_b[7:0] MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 340: Memory Map And Register Definition
0x00000000 on page 355 0x028 CtrlDescL1_4 Register 0x00000000 on page 356 0x02C CtrlDescL1_5 Register 0x00000000 on page 358 0x030 CtrlDescL1_6 Register 0x00000000 on page 359 0x034 CtrlDescL1_7 Register 0x00000000 on page 361 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 341 0x00000000 on page 353 0x0AC CtrlDescL6_2 Register 0x00000000 on page 354 0x0B0 CtrlDescL6_3 Register 0x00000000 on page 355 0x0B4 CtrlDescL6_4 Register 0x00000000 on page 356 0x0B8 CtrlDescL6_5 Register 0x00000000 on page 358 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 342 0x00000000 on page 359 0x130 CtrlDescL10_7 Register 0x00000000 on page 361 0x134 CtrlDescL11_1 Register 0x00000000 on page 353 0x138 CtrlDescL11_2 Register 0x00000000 on page 354 0x13C CtrlDescL11_3 Register 0x00000000 on page 355 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 343 0x00000000 on page 356 0x1B4 CtrlDescL15_5 Register 0x00000000 on page 358 0x1B8 CtrlDescL15_6 Register 0x00000000 on page 359 0x1BC CtrlDescL15_7 Register 0x00000000 on page 361 0x1C0 CtrlDescCursor_1 Register 0x00000000 on page 361 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 344 0xFF00FF00 on page 389 0x238 THRESHOLD_INP_BUF_2 Register 0xFF00FF00 on page 389 0x23C LUMA_COMP Register 0x9512A254 on page 390 0x240 CHROMA_RED Register 0x03310000 on page 391 0x244 CHROMA_GREEN Register 0x06600F38 on page 391 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 345 0x00000000 on page 393 0x2BC FG13_bcolor Register 0x00000000 on page 394 0x2C0 FG14_fcolor Register 0x00000000 on page 393 0x2C4 FG14_bcolor Register 0x00000000 on page 394 0x2C8 FG15_fcolor Register 0x00000000 on page 393 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 346: Register Summary
Soft Lock Bit Register L1_TRANSP 0x00000000 on page 402 12.3.3 Register summary Table 12-4. Register descriptions Name HEIGHT CtrlDescL0_1 0x000 WIDTH POSY CtrlDescL0_2 0x004 POSX CtrlDescL0_3 ADDR 0x008 TRANS CtrlDescL0_4 0x00C LUOFFS MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 347 CKMAX_B CKMIN_R CtrlDescL0_6 0x014 CKMIN_G CKMIN_B TILE_VER_SIZE CtrlDescL0_7 0x018 TILE_HOR_SIZE HEIGHT CtrlDescCurs or_1 0x1C0 WIDTH POSY CtrlDescCurs or_2 0x1C4 POSX R CU DEFAULT_CURSOR_COLOR[0:7] CtrlDescCurs or_3 0x1C8 DEFAULT_CURSOR_COLOR[8:23] HWC_BLINK_OFF CtrlDescCurs or_4 0x1CC HWC_BLINK_ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 348 Table 12-4. Register descriptions (continued) Name BLEND_ITER PDI_SYNC_LOCK DCU_MODE 0x1D0 BGND_R BGND 0x1D4 BGND_G BGND_B DELTA_Y DISP_SIZE 0x1D8 DELTA_X BP_H PW_H[0:3] HSYN_PARA 0x1DC PW_H[4:8] FP_H BP_V PW_V[0:3] VSYN_PARA 0x1E0 PW_V[4:8] FP_V SYN_POL 0x1E4 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 349 Table 12-4. Register descriptions (continued) Name LS_BF_VS THRESHOLD 0x1E8 OUT_BUF_HIGH OUT_BUF_LOW w1c w1c w1c w1c INT_STATUS 0x1EC w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c INT_MASK 0x1F0 COLBAR_1_R COLBAR_1 0x1F4 COLBAR_1_G COLBAR_1_B MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 350 COLBAR_3 0x1FC COLBAR_3_G COLBAR_3_B COLBAR_4_R COLBAR_4 0x200 COLBAR_4_G COLBAR_4_B COLBAR_5_R COLBAR_5 0x204 COLBAR_5_G COLBAR_5_B COLBAR_6_R COLBAR_6 0x208 COLBAR_6_G COLBAR_6_B COLBAR_7_R COLBAR_7 0x20C COLBAR_7_G COLBAR_7_B COLBAR_8_R COLBAR_8 0x210 COLBAR_8_G COLBAR_8_B DIV_RATIO 0x214 DIV_RATIO MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 351 Table 12-4. Register descriptions (continued) Name SIG_VER_SIZE SIGN_CALC_ 0x218 SIG_HOR_SIZE SIG_VER_POS SIGN_CALC_ 0x21C SIG_HOR_POS CRC_VAL CRC_VAL 0x220 PDI_STATUS 0x224 w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Mask_PDI_S TATUS 0x228 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 352 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Mask_PARR_ ERR_STATUS 0x230 INP_BUF_P2_HI INP_BUF_P2_LO THRESHOLD _INP_BUF 0x234 INP_BUF_P1_HI INP_BUF_P1_LO INP_BUF_P4_HI INP_BUF_P4_LO THRESHOLD _INP_BUF 0x238 INP_BUF_P3_HI INP_BUF_P3_LO Y_RED Y_GREEN[0:4] LUMA_COMP 0x23C Y_GREEN[5:9] Y_BLUE MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 353 Table 12-4. Register descriptions (continued) Name Cr_RED CHROMA_RE 0x240 Cb_RED Cr_GREEN CHROMA_G REEN 0x244 Cb_GREEN Cr_BLUE CHROMA_BL 0x248 Cb_BLUE CRC_POS CRC_POS 0x24c FGX_FCOLOR[0:7] FGx_fcolor 0x250 FGX_FCOLOR[8:23] FGX_BCOLOR[0:7] FGx_bcolor 0x254 FGX_BCOLOR[8:23] Global_protec tion 0x300 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 354 Display Control Unit (DCU) Table 12-4. Register descriptions (continued) Name Soft_Lock_Bit 0x304 Soft_Lock_Bit 0x308 Soft_Lock_DI SP_SIZE 0x30c Soft_Lock_HS YNC/VSYNC PARA 0x310 Soft_Lock_P 0x314 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 355: Register Descriptions
This section describes the DCU registers. 12.3.4.1 Control Descriptor L0_1 Register (CtrlDescL0_1) Figure 12-3 represents the control descriptor L0_1 register. This register sets the height and width of the layer associated with the register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 356: Control Descriptor L0_2 Register
Section 12.4.5.3, Layer size and positioning. 12.3.4.2 Control Descriptor L0_2 Register Figure 12-4 represents the control descriptor L0_2 register. This register sets the origin (top/left) of the layer associated with the register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 357: Control Descriptor L0_3 Register
Amount of pixels from the left of display frame POSX 12.3.4.3 Control Descriptor L0_3 Register Figure 12-5 represents the control descriptor L0_3 register. This register sets the beginning address of layer data. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 358: Control Descriptor L0_4 Register
Address of layer data in the memory. The address programmed should be 32-bit aligned. ADDR 12.3.4.4 Control Descriptor L0_4 Register Figure 12-6 represents the control descriptor L0_4 register. This register controls various graphics options and whether the layer is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 359 Transparency Level. Specifies the alpha value for the layer. This value may be used by the TRANS blending engine to blend pixels on this layer. Value can vary between 0-255 where 0 is completely transparent and 255 is completely opaque. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 360: Control Descriptor L0_5 Register
Figure 12-7 represents the control Descriptor L0_5 register. This register sets the maximum Chroma Keying values for RGB. Refer to Section 12.4.5.5, Alpha and Chroma-key blending, for a description of Chroma Keying. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 361: Control Descriptor L0_6 Register
Figure 12-8 represents the control descriptor L0_6 register. This register sets the minimum Chroma Keying values for RGB. Refer to Section 12.4.5.5, Alpha and Chroma-key blending, for a description of Chroma Keying. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 362 Figure 12-8. CtrlDescL0_6 Register Table 12-10. CtrlDescL0_6 field descriptions Field Description 8–15 Chroma Keying Minimum Red Component CKMIN_R 16–23 Chroma Keying Minimum Green Component CKMIN_G 24–31 Chroma Keying Minimum Blue Component CKMIN_B MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 363: Control Descriptor L0_7 Register
Width of the TILE (in multiples of 16 pixels) TILE_HOR_SIZE For the other 16 layers, the Control Descriptor Register set is identical. 12.3.4.8 Control Descriptor Cursor 1 Register (CtrlDescCursor_1) Figure 12-10 represents the Control Descriptor Cursor 1 register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 364: Control Descriptor Cursor 2 Register (Ctrldesccursor_2)
Control Descriptor Cursor 2 Register (CtrlDescCursor_2) Figure 12-11 represents the Control descriptor Cursor 2 register. Offset: 0x1C4 Access: User read/write POSY Reset POSX Reset Figure 12-11. Control Descriptor Cursor 2 Register (CtrlDescCursor_2) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 365: Control Descriptor Cursor 3 Register (Ctrldesccursor_3)
Default pixel color value for the cursor. In the DCU, the pixel value for the cursor is fixed for a DEFAULT_CURSO particular frame. R_COLOR 12.3.4.11 Control Descriptor Cursor 4 Register (CtrlDescCursor_4) Figure 12-13 represents the Control Descriptor Cursor 4 register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 366: Dcu Mode Register (Dcu_Mode)
HWC blink register. Loads the counter value (number of frames) for which the cursor will remain HWC_BLINK_ON turned ON. 12.3.4.12 DCU Mode Register (DCU_MODE) Figure 12-14 represents the DCU_MODE register.This register sets the mode in which DCU is operating. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 367 For correct operation RASTER_EN should only be changed when DCU_MODE is configured to off. Changes to this bit take effect after the completion of the current frame. 0 Disabled 1 Enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 368: Bgnd Register
10 Test mode. Panel content fetched from CLUT/Tile memory 11 Color Bar Generation. Pixel clock active and panel content controlled by color bar registers. 12.3.4.13 BGND Register Figure 12-15 represents the BGND register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 369: Disp_Size Register
Blue component of the default color displayed in the sectors where no layer is active BGND_B 12.3.4.14 DISP_SIZE Register Figure 12-16 represents the DISP_SIZE register Offset: 0x1D8 Access: User read/write DELTA_Y Reset DELTA_X Reset Figure 12-16. DISP_SIZE Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 370: Hsyn_Para Register
VSYN_PARA register. VSYN_PARA register sets timing parameters related to the vertical synchronization signal generation. The fields FP_V, BP_V, and PW_V stand for VSYNC signal front-porch, back-porch, and active pulse width, respectively. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 371: Syn_Pol Register
SYN_POL register. SYN_POL register selects polarity for corresponding synchronize signals (HSYNC, VSYNC, CSYNC), and controls the bypass of HSYNC or VSYNC with CSYNC signal. Offset: 0x1E4 Access: User read/write Reset Reset Figure 12-19. SYN_POL Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 372: Threshold Register
1 Invert VSYNC signal, active LOW Invert Horizontal Synchronize Signal. INV_HS 0 Do not invert HSYNC signal, active HIGH 1 Invert HSYNC signal, active LOW 12.3.4.18 Threshold Register Figure 12-20 represents the Threshold Register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 373: Interrupt Status Register (Int_Status)
(UNDRUN in INT_STATUS). 12.3.4.19 Interrupt Status Register (INT_STATUS) Figure 12-21 indicates the interrupt status register. See Section 12.5.4, Interrupt generation, for a description of how the DCU collects interrupt events into different source groups. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 374 Interrupt signal that indicates that the duration for programming of DCU registers and PROG_END internal memories is finished Interrupt signal that indicates the High threshold has been reached for plane 2 (FGplane) P2_FIFO_HI_FLAG input buffer MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 375: Interrupt Mask Register (Int_Mask)
Vertical Synchronize Interrupt. If enabled, an interrupt is generated at the beginning of a VSYNC frame. 12.3.4.20 Interrupt Mask Register (INT_MASK) Figure 12-22 represents the interrupt mask register.This register enables or masks corresponding interrupt. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 376 0 Interrupt is not masked 1 Interrupt is masked DMA_TRANS_FINISH interrupt mask M_DMA_TRANS_FINISH 0 Interrupt is not masked 1 Interrupt is masked IPM_ERROR interrupt mask M_IPM_ERROR 0 Interrupt is not masked 1 Interrupt is masked MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 377: Colbar Registers
The COLBAR registers are used to generate color bars in functional test mode. Eight different pixel values are taken as input data, to display 8 color bars on the display. Table 12-25. COLBAR_n register field descriptions Field Name Description COLBAR_n_R Red component value MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 378 Offset: 0x1F4 Access: User read/write COLBAR_1_R Reset COLBAR_1_G COLBAR_1_B Reset Figure 12-23. COLBAR_1 Register (Black) 12.3.4.21.2 COLBAR_2 Register Offset: 0x1F8 Access: User read/write COLBAR_2_R Reset COLBAR_2_G COLBAR_2_B Reset Figure 12-24. COLBAR_2 Register (Blue) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 379 Offset: 0x1FC Access: User read/write COLBAR_3_R Reset COLBAR_3_G COLBAR_3_B Reset Figure 12-25. COLBAR_3 Register (Cyan) 12.3.4.21.4 COLBAR_4 Register Offset: 0x200 Access: User read/write COLBAR_4_R Reset COLBAR_4_G COLBAR_4_B Reset Figure 12-26. COLBAR_4 Register (Green) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 380 Offset: 0x204 Access: User read/write COLBAR_5_R Reset COLBAR_5_G COLBAR_5_B Reset Figure 12-27. COLBAR_5 Register (Yellow) 12.3.4.21.6 COLBAR_6 Register Offset: 0x208 Access: User read/write COLBAR_6_R Reset COLBAR_6_G COLBAR_6_B Reset Figure 12-28. COLBAR_6 Register (Red) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 381: Divide Ratio (Div_Ratio) Register
Figure 12-29. COLBAR_7 Register (Purple) 12.3.4.21.8 COLBAR_8 Register Offset: 0x210 Access: User read/write COLBAR_8_R Reset COLBAR_8_G COLBAR_8_B Reset Figure 12-30. COLBAR_8 Register (White) 12.3.4.22 Divide Ratio (DIV_RATIO) register Figure 12-31 shows the Divide Ratio register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 382: Sign_Calc_1 Register
Description 6–15 Vertical size of the window of interest of pixels for CRC calculation (in pixels) SIG_VER_SIZE 22–31 Horizontal size of window of interest of pixels for CRC calculations (in pixels) SIG_HOR_SIZE MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 383: Sign_Calc_2 Register
Horizontal position of window of interest of pixels for CRC calculation (in pixels) SIG_HOR_POS 12.3.4.25 CRC_VAL Register Figure 12-34 represents the register presenting the CRC value to the software for comparison. Offset: 0x220 Access: User read/write CRC_VAL[0:15] Reset CRC_VAL[16:31] Reset Figure 12-34. CRC_VAL Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 384: Pdi Status Register
0 One bit ECC error is not detected 1 One bit ECC error detected Status bit to inform the software that frame lock is lost. pdi_lock_lost 0 Frame is locked 1 Frame lock is lost MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 385: Pdi Status Mask Register
0 pdi_clk not detected 1 pdi_clk is detected 12.3.4.27 PDI Status Mask Register Figure 12-36 represents the Mask PDI status register Offset: 0x228 Access: User read/write Reset Reset Figure 12-36. PDI status mask register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 386: Parameter Error Status (Parr_Err) Register
Section 12.4.5.3, Layer size and positioning, for details. These errors are grouped into a single bit error for each layer. The parameter error specific to each layer is signaled only when the layer is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 387 0. 0 DISP_ERR is not set 1 DISP_ERR is set Interrupt occurs whenever there is an error in layer 15. L15_PARR_ERR 0 Parameter error is not set 1 Parameter error is set MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 388 0 Parameter error is not set 1 Parameter error is set Interrupt occurs whenever there is an error in layer 2. L2_PARR_ERR 0 Parameter error is not set 1 Parameter error is set MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 389: Mask Parr_Err Status Register
1 Mask the interrupt M_DISP_ERR interrupt mask M_DISP_ERR 0 Do not mask the interrupt 1 Mask the interrupt M_L15_parr_err interrupt mask M_L15_parr_err 0 Do not mask the interrupt 1 Mask the interrupt MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 390 1 Mask the interrupt M_L3_parr_err interrupt mask M_L3_parr_err 0 Do not mask the interrupt 1 Mask the interrupt M_L2_parr_err interrupt mask M_L2_parr_err 0 Do not mask the interrupt 1 Mask the interrupt MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 391: Threshold_Inp_Buf_1 Register
INP_BUF_p1_hi 24–31 Low Threshold for input buffer for blend stage 1 (background plane). INP_BUF_p1_lo 12.3.4.31 THRESHOLD_INP_BUF_2 Register Figure 12-40 represents the threshold register for input buffer for plane 3 and plane 4. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 392: Luma Component Register
Low Threshold for input buffer for blend stage 3. INP_BUF_p3_lo 12.3.4.32 LUMA Component Register Figure 12-41 represents the LUMA component register. Offset: 0x23C Access: User read/write Y_RED Y_GREEN[0:4] Reset Y_GREEN[5:9] Y_BLUE Reset Figure 12-41. LUMA Component Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 393: Red Chroma Components
Table 12-37. Red Chroma Component Register field descriptions Field Description 5–15 Cr Coefficient for Red Matrix Cr_RED 20–31 Cb Coefficient for Red Matrix Cb_GREEN 12.3.4.34 Green Chroma Component Register Figure 12-43 represents the Green Chroma component register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 394: Blue Chroma Component Register
Cb Coefficient for Green Matrix Cb_GREEN 12.3.4.35 Blue Chroma Component Register Figure 12-44 represents the Blue Chroma component register. Offset: 0x248 Access: User read/write Cr_BLUE Reset Cb_BLUE Reset Figure 12-44. BLUE Chroma component register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 395: Crc_Pos Register
Table 12-40. CRC_POS field descriptions Field Description 0–31 CRC position value calculated for safety enabled layers to be presented to the software for CRC_POS comparison 12.3.4.37 FG0_FCOLOR Register Figure 12-46 represents the FG0_fcolor register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 396: Fg0_Bcolor
Reset FG0_FCOLOR[8:23] Reset Figure 12-46. FG0_fcolor Register Table 12-41. FG0_fcolor field descriptions Field Description 8–31 Foreground color for layer FG0 for pre-blending engine FG0_FCOLOR 12.3.4.38 FG0_bcolor Figure 12-47 represents the FG0_bcolor register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 397: Global Protection Register
Background color for layer FG0 for pre-blending engine FG0_BCOLOR 12.3.4.39 Global Protection Register Figure 12-48 represents the Global Protection register. Offset: 0x300 Access: User read/write Reset Reset Figure 12-48. Global Protection Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 398: Soft Lock Bit Register L0
1 Value is written to SLB Soft Lock Bit for Control Desc L0_1 Register. SLB_L0_1 0 Associated protected register is not locked and writeable 1 Associated protected register is locked for write access MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 399: Soft Lock Bit Register L1
1 Associated protected register is locked for write access 12.3.4.41 Soft Lock Bit Register L1 Figure 12-50 represents the Soft Lock Bit Register for Layer1. This is used to protect the seven control descriptor layer registers for Layer1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 400 0 Associated protected register is not locked and writeable 1 Associated protected register is locked for write access Write Enable for Soft Lock Bit SLB_L1_5 WEN_L1_5 0 SLB is not modified 1 Value is written to SLB MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 401: Soft Lock Disp_Size Register
1 Associated protected register is locked for write access 12.3.4.42 Soft Lock DISP_SIZE Register Figure 12-51 represents the Soft Lock DISP_SIZE register. Offset: 0x30C Access: User read/write Reset Reset Figure 12-51. Soft Lock DISP_SIZE Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 402: Soft Lock Hsync/Vsync Para Register
1 Associated protected register is locked for write access Soft Lock Bit for VSYNC Register. SLB_VSYNC 0 Associated protected register is not locked and writeable 1 Associated protected register is locked for write access MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 403: Soft Lock Pol Register
SLB_POL 0 Associated protected register is not locked and writeable 1 Associated protected register is locked for write access 12.3.4.45 Soft Lock L0_TRANSP Register Figure 12-54 represents the Soft Lock L0_TRANSP register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 404: Soft Lock L1_Transp Register
SLB_L0_BCOLOR 0 Associated protected register is not locked and writeable 1 Associated protected register is locked for write access 12.3.4.46 Soft Lock L1_TRANSP Register Figure 12-55 represents the Soft Lock L1_TRANSP register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 405: Functional Description
This includes all on-chip flash, all on-chip RAM, and any slave capable of providing high enough data rates, such as, for example an expanded bus interface or a QuadSPI module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 406: Tft Lcd Panel Configuration
Both of these values are defined in the DISP_SIZE register (DELTA_X, DELTA_Y). The width of the panel must always be defined as a multiple of 16. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 407 PW_V is the vsync active pulse width (in pixel clock cycles) Pixel Clock = (DCU Clock) / PRESCALE VALUE Eqn. 12-2 where PRESCALE VALUE is an integer value that can range from 2–32. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 408: Dcu Mode Selection And Background Color
PDI Slave mode allows the DCU to synchronize with the external timing signals on the PDI input. 12.4.4 Proper sequence for enabling and disabling the DCU It is important to follow a correct sequence when enabling and disabling the DCU. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 409: Layer Configuration And Blending
DCU clock cycles than three-pixel blending, and three-pixel blending takes more DCU clock cycles than two-pixel blending. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 410 Layer 2 is visible where layer 1 does not overlap it. Layer 3 is overlapped by layers 0 and 1 and so is only partially visible. Layer 4 is partially obscured by all of the other layers. Note that layer 4 is higher priority than the background color. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 411 4 and the background color are not included in this blend. This is because the DCU is configured to blend three layers only, and so the blend setting for layer 2 is ignored for those pixels in region B. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 412: Control Descriptors
1 bit per pixel to 32 bits per pixel and so there is a range of multiples from 1 to 32. Figure 12-52 shows the multiples for the WIDTH bit field and some correct values. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 413: Graphics And Data Format
ARGB1555 where the data defines 5-bit values for the red, green, and blue components, and a 1-bit value for the alpha channel of the image. • ARGB4444, where the data defines 4-bit values for the red, green, blue, and alpha components of the image. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 414 For 16 bpp, data expected is in the form of RGB565, ARGB1555 or ARGB4444. Table 12-55. Data Layout for 16 bpp Address offset [7:0] [15:8] [23:16] [31:24] 0x00 pixel0[15:8] pixel0[7:0] pixel1[15:8] pixel1[7:0] 0x04 pixel2[15:8] pixel2[7:0] pixel3[15:8] pixel3[7:0] 0x08 pixel4[15:8] pixel4[7:0] pixel5[15:8] pixel5[7:0] MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 415: Alpha And Chroma-Key Blending
(CTRLDESCLn_4, where n is the layer number). The pixels affected by the blending configuration can be further selected by registers 5 and 6 in the control descriptor (CTRLDESCLn_4 and CTRLDESCLn_5). Depending on the priority and placement of the layer (see MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 416 The output value for each of the RGB components is therefore obtained by right-shifting A by 8 and then adding 1 to the result. The blend can apply to pixels with no alpha channel (RGB) or with an alpha channel (ARGB) in different ways. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 417 ARGB Reserved ARGB Reserved Figure 12-60 Figure 12-68 illustrate the effect of the cases identified in Table 12-61. In all cases there is a single active layer and a white background color. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 418: 16 Freescale Semiconductor
Display Control Unit (DCU) Figure 12-60. Case 1 example (no blend) Figure 12-61. Case 2 example (remove selected pixels) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 419 Display Control Unit (DCU) Figure 12-62. Case 3 example (all pixels transparent) Figure 12-63. Case 4 example (selected pixels transparent) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 420 Display Control Unit (DCU) Figure 12-64. Case 6 example (selected pixels removed, others transparent) Figure 12-65. Case 9 example (no blend, pixel alpha ignored) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 421 Display Control Unit (DCU) Figure 12-66. Case 10 example (selected pixels removed, pixel alpha ignored) Figure 12-67. Case 13 example (pixel and layer alpha used in blend) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 422: Transparency Mode And Blending
RGB888 graphic and blended in a similar way to previously described, or it can be treated as a special case of ARGB with only the foreground color visible in the final blend. Table 12-62 describes the blend options for transparency mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 423 Table 12-62. In all cases there is a single active transparency layer and a white background color. Panel Foreground Color Transparency Background graphic Color Figure 12-69. Case 1 example (no blend) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 424 Display Control Unit (DCU) Figure 12-70. Case 3 example (all pixels transparent) Figure 12-71. Case 4 example (selected pixels transparent) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 425: Luminance Mode
In this mode the layer size register (CTRLDESCLn_1, where n is the layer number) defines the size of the layer; however, the size of the graphic is defined in control register 7 (CTRLDESCLn_7, where n is the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 426: Hardware Cursor
(CTRLDESCCURSOR_1). The register contains two bit fields, HEIGHT and WIDTH, which determine the size and shape of the layer. Both fields are expressed in terms of the number of pixels in each MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 427 The cursor RAM may be written at any time when the TFT LCD panel is not being driven with data. This means that the RAM can be modified when the DCU is not enabled and during the vertical blanking period. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 428: Clut/Tile Ram
The CLUT/Tile RAM may be written at any time when the TFT LCD panel is not being driven with data. This means that the RAM can be modified when the DCU is not enabled and during the vertical blanking period. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 429: Gamma Correction
12.5 Timing, error and interrupt management The DCU can detect and raise status and error flags when the status of the system changes and when configuration or operational errors are detected. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 430: Synchronizing To Panel Frame Rate
The FIFO thresholds are set in the THRESHOLD_INPUT_BUF_1/2 registers. The upper thresholds are set by the INP_BUF_Pm_HI bit fields (where m is the position of the pixel in the blend stack) and these MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 431 DCU clock must be twice the TFT pixel clock. For three-pixel blending, the minimum DCU clock must be three times the TFT pixel clock. For four-pixel blending, the minimum DCU clock must be four times the TFT pixel clock. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 432: Error Detection
There are four interrupt status lines defined.These lines are grouped as follows • Timing based interrupts: — VSYNC — LS_BF_VS — VS_BLANK — PROG_END — DMA_TRANS_FINISH • Functional interrupts: — UNDRUN — CRC_READY MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 433: Register Protection
If a write is made to a register whose SLB is set then a transfer error occurs that generates an IVOR2 exception on the CPU. Similarly if the HLB is set then any write to the SLB registers causes a transfer error. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 434: List Of Protected Registers
CRC for the next frame. If the interrupt is not processed within one frame time period, then CRC overflow interrupt is issued. The signature calculator calculates the content signature and position signature. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 435: Crc Area Description
DCU and flow along the data path) is set low. Data enable is coming for green color portion given in Figure 12-77. Data enable is not affected by chroma keying. TAG_EN register bit is low in this case. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 436 Figure 12-78 Data enable is controlled by the region shown in green color and tag is controlled by the pink region. CRC is calculated over region in dark pink. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 437: Features
BG layer and Layer 0 as a FG Layer.CRC would be calculated over a single L0 Layer. Table 12-64. Supported Area Area Tag Value Note Full StartX = 0 StartY = 0 LenX = Screen Size LenY = Screen Height MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 438: Programming For Debug Mode
5. Check the CRC when CRC calculation interrupt is raised fora particular screen. 12.8 Parallel Data Interface (Camera Interface) Digital Digital Video Display source RGB/Mono/YCbCr CCIR656 Digital Digital Display FPGA Proprietary RGB/Mono/YCbCr LVDS Figure 12-79. Camera interface block diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 439: Itu-R Bt.656 Sync Information Extraction
For more information, please see EB736, Limitations of the PDI Module on the MPC560xS. Table 12-65. Control byte sequence for 8-bit video First word Second word Third word Fourth word Data Bit (FF) (00) (00) D9(MSB) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 440: Pdi Interface Description
TFT/LCD screen. It can also be used in the Slave mode; that is, it takes only timing info from external chip/FPGA and display pixel info from memory to TFT screen at the timing provided. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 441: Pdi Interaction With Other Modules
In all cases, the resolution of the incoming stream and the Hsync and Vsync frequency must be the same as that of the TFT screen. All the horizontal parameter (Front Porch width, Back Porch width, Pulse width) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 442: Features
External sync (with data En) Hsync, Vsync, Pclk, DE 12.8.2.4 Normal and Narrow mode In normal mode, PDI support maximum input frequency of 32 MHz. In narrow mode, PDI supports maximum input frequency of 64 MHz. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 443 In first clock cycle, PDI[7:0] = { Cb[7:0] } In second clock cycle, PDI[7:0] = { Y0[7:0] } In third clock cycle, PDI[7:0] = { Cr[7:0] } In forth clock cycle, PDI[7:0] = { Y1[7:0] } MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 444: Modes Of Operation Based On Sync Extraction
(vertical front porch) (no of hsync) (vertical Back porch) Value = 2 (no of hsync) Value = 2 (no of hsync) Vertical blanking period Figure 12-85. Relation between Hsync and Vsync in external synchronization MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 445 Always 1'b1. This is checked while decoding sync preamble Not considered in the state machine logic 1'b1 during vertical blanking 1'b0 elsewhere 1'b0 for start of active video 1'b1 for end of active video MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 446 YCbCr422 muxed mode. ECC error is only detected not corrected. It would be calculated using protection bits in Table 12-68 Same as External sync mode, value of front and back porches can be zero but pulse width and TFT screen parameter cannot be zero. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 447 Note that the first multiplication (i.e (y-16)*ycoeff) is unsigned. The other two others signed. The register values after reset are as follows: Yred = 10’h254 (596/512 = 1.16) Crred = 11’h331 (817/512 = 1.6) Cbred = 12’h000 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 448: Mode Of Operation Depending On Pdi_Datain
16-bit—RGB565 (8-bit input data, each pixel info is coming in 2 clocks) • 16-bit—YCbCr422 (8-bit input data, info for 2 co-sited pixels coming in 4 clocks) Data info extraction is given in Table 12-69. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 449: Pdi-Related Interrupts
1. After reset configure the DCU peripheral to be active using the mode entry module and configure the DCU clock source in the MC_CGM. 2. Configure the output ports in the SIUL as required. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 450: Glossary
DCU supports different variations of this format where different numbers of bits can be used to represent each of the components Vertical blanking period A time during the TFT LCD panel refresh cycle when no data is being written to the panel MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 451: Introduction
The DMACHMUX provides these features: • 48 peripheral slots + four always-on slots can be routed to 16 channels • 16 independently selectable DMA channel routers — First four channels additionally provide a trigger functionality MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 452: Modes Of Operation
Channel #1 Configuration (CHCONFIG1) on page 451 Base + 0x#n – 1 Channel #n Configuration (CHCONFIG#n – 1) on page 451 In the table n refers to the number of channels – 1 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 453: Register Descriptions
Table 13-3. Channel and trigger enabling ENBL TRIG Function Mode DMA channel is disabled Disabled mode DMA channel is enabled with no triggering (transparent) Normal mode DMA channel is enabled with triggering Periodic Trigger mode MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 454 DSPI_0 TX DSPI_0 RX DSPI_1 TX DSPI_1 RX QuadSPI_0 TFFF QuadSPI_0 RFDF / RBDF I2C_0_TX I2C_0_RX I2C_1_TX I2C_1_RX I2C_2_TX I2C_2_RX I2C_3_TX I2C_3_RX eMIOS200_0_FLAG_F0 eMIOS200_0_FLAG_F1 eMIOS200_0_FLAG_F2 eMIOS200_0_FLAG_F3 eMIOS200_0_FLAG_F4 eMIOS200_0_FLAG_F5 eMIOS200_0_FLAG_F6 eMIOS200_0_FLAG_F7 eMIOS200_0_FLAG_F8 eMIOS200_0_FLAG_F9 eMIOS200_0_FLAG_F10 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 455 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIU_EISR_EIF1 SIU_EISR_EIF2 SIU_EISR_EIF3 SIU_EISR_EIF4 Reserved Reserved Reserved Reserved ALWAYS requestors ALWAYS requestors MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 456: Functional Description
Table 13-5 shows the mapping of PIT channels to DMA channels for triggering. Table 13-5. PIT-DMA channel mapping DMACHMUX channel number PIT channel number for triggering MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 457 DMA until a trigger event occurs. This is illustrated in Figure 13-4. Peripheral request Trigger DMA request Figure 13-4. DMA mux channel triggering: normal operation MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 458: Dma Channels With No Triggering Capability
Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the always enabled sources provide no such throttling of the data transfers. These sources are most useful in the following cases: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 459: Initialization/Application Information
Enabling and configuring sources 13.5.2.1 Enabling a source with periodic triggering 1. Determine with which DMA channel the source will be associated. Note that only the first four DMA channels have periodic triggering capability. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 460: Enabling A Source Without Periodic Triggering
2. Clear the ENBL and TRIG bits of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 461: Disabling A Source
2. Clear the ENBL and TRIG bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG register, ensuring that the ENBL and TRIG bits are set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 462 *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87; MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 463: Overview
SRAM and flash memory via independent Instruction and Data bus interface units (BIUs). • Load/store unit — 1 cycle load latency — Fully pipelined — Big- and Little-endian support — Misaligned access support — Zero load-to-use pipeline bubbles for aligned transfers • Power management MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 464: Microarchitecture Summary
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 465: Block Diagram
32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or up to two 16-bit VLE instructions per clock • Instruction buffer with 4 entries in e200zh0, each holding a single 32-bit instruction, or a pair of 16-bit instructions MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 466: Integer Unit Features
PowerPC Book E architecture, highlighting differences in how these registers are implemented in the e200 core, and provides a detailed description of e200-specific registers. Full descriptions of the architecture-defined register set are provided in the Power Architecture Book E Specification. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 467 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 468 1—These e200-specific registers may not be supported DVC2 SPR 319 by other PowerPC processors 2—Optional registers defined by the PowerPC Book-E architecture 3—Read-only registers Figure 14-2. e200z0h SUPERVISOR mode program model SPRs MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 469: Unimplemented Sprs And Read-Only Sprs
(MSR[PR=0]), an illegal instruction exception is generated. 14.4 Instruction summary e200z0h supports all VLE instructions described in the PowerPC™ VLE APU Definition version 1.2 together with the additional instructions for context save/restore. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 470 Core MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 471: Information Specific To This Device
(TCD) for the channels. This SRAM-based implementation is used to minimize the overall module size. Figure 15-1 is a block diagram of the DMA module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 472: Overview
— Parameterized support for 32- and 64-bit AMBA-AHB datapath widths • 32-byte transfer control descriptor per channel stored in local memory • 32 bytes of data registers, used as temporary storage to support burst transfers MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 473: Features
/* channel link at end of the minor loop */ struct { /* citer.e_link = 0 */ unsigned short citer:15; /* current (“major”) iteration count */ } minor_link_disabled; /* no linking at end of the minor loop */ } t_minor_link_citer; MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 474 The number of iterations in the minor loop is automatically calculated by the DMA engine. The number of iterations within the minor loop is a function of the number MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 475 /* 32-byte burst transfer */ src_xfr_size = 32; break; /* convert the destination transfer size into a byte count */ switch (dma_engine.dsize) { case 0: /* 8-bit transfer */ dest_xfr_size = 1; break; MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 476 /* if the dsize < ssize, do multiple writes to equal the ssize */ /* if the dsize => ssize, do a single write of dest data */ number_of_dest_writes = xfer_size / dest_xfer_size; MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 477 /* check for interrupt assertion if half of the major iterations are done */ if (dma_engine.int_half && (dma_engine.citer == (dma_engine.biter >> 1))) generate_interrupt (channel); dma_engine.active = 0; /* clear the channel busy flag */ else { /* major loop is complete, dma_engine.citer == 0 */ MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 478: Memory Map/Register Definition
16, 32, or 64 bits in size. Registers associated with a 64-channel design are implemented as two 32-bit registers, and include an “H” and “L” suffixes, signaling the “high” and “low” portions of MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 479 DMA Channel 31 Priority (DCHPRI28) Priority (DCHPRI29) Priority (DCHPRI30) Priority (DCHPRI31) 0x0120 DMA Channel 32 DMA Channel 33 DMA Channel 34 DMA Channel 35 Priority (DCHPRI32) Priority (DCHPRI33) Priority (DCHPRI34) Priority (DCHPRI35) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 480: Register Descriptions
Unused group priority registers, per configuration, are unimplemented in the DMACR. In group round-robin mode, the group priorities are ignored and the groups are cycled through without regard to priority. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 481 In addition to cancelling the transfer, the ECX treats the cancel as an error condition; thus updating the DMAES register and generating an optional error interrupt (see Section 15.3.1.2, DMA Error Status (DMAES) register). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 482 0 The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes. 1 The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the last write sequence. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 483: Dma Error Status (Dmaes) Register
ERRCHN field and the ECX and VLD bits are set are set in the DMAES register. In addition, an error interrupt may be generated if enabled. Section 15.3.1.14, DMA Error (DMAERRH, DMAERRL) registers, for error interrupt details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 484 1 The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff is inconsistent with TCD.ssize. Destination Address Error 0 No destination address configuration error. 1 The last recorded error was a configuration error detected in the TCD.daddr field. TCD.daddr is inconsistent with TCD.dsize. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 485: Dma Enable Request (Dmaerqh, Dmaerql) Registers
See Figure 15-4, Figure 15-5, Table 15-4 for the DMAERQ definition. Address: Base + 0x0008 Access: User read/write R ERQ Reset R ERQ Reset Figure 15-4. DMA Enable Request High (DMAERQH) register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 486: Dma Enable Error Interrupt (Dmaeeih, Dmaeeil) Registers
Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. See Figure 15-6, Figure 15-7, and Table 15-5 for the DMAEEI definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 487: Dma Set Enable Request (Dmaserq) Register
DMAERQ{H,L} to be asserted. If bit 0 (NOP) is set, the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See Figure 15-8 Table 15-6 for the DMASERQ definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 488: Dma Clear Enable Request (Dmacerq) Register
DMAEEI{H,L} registers to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the DMAEEI{H,L} register to be set. A data value of 64 to 127 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 489: Dma Clear Enable Error Interrupt (Dmaceei) Register
Table 15-9. DMA Clear Enable Error Interrupt (DMACEEI) field descriptions Name Description No Operation 0 Normal operation. 1 No operation, ignore bits 6–0 CEEI[0:6] Clear Enable Error Interrupt 0–63 Clear corresponding bit in DMAEEI{H,L} 64–127 Clear all bits in DMAEEI{H,L} MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 490: Dma Clear Interrupt Request (Dmacint) Register
This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See Figure 15-13 Table 15-11 for the DMACERR definition. Address: Base + 0x001D Access: User write-only CERR[0:6] Reset Figure 15-13. DMA Clear Error (DMACERR) register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 491: Dma Set Start Bit (Dmassrt) Register
This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See Table 15-28 for the TCD DONE bit definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 492: Dma Interrupt Request (Dmainth, Dmaintl) Registers
Figure 15-16, Figure 15-17, and Table 15-14 for the DMAINT definition. Address: Base + 0x0020 Access: User read/write R INT Reset R INT Reset Figure 15-16. DMA Interrupt Request High (DMAINTH) register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 493: Dma Error (Dmaerrh, Dmaerrl) Registers
The DMACERR register is provided so the error indicator for a single channel can easily be cleared. See Figure 15-18, Figure 15-19, Table 15-15 for the DMAERR definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 494: Dma Hardware Request Status (Dmahrsh, Dmahrsl) Registers
DMAERQ field) ipd_req lines as seen by the DMA2’s arbitration logic. This view into the hardware request signals may be used for debug purposes. Figure 15-20, Figure 15-21, and Figure 15-16 for the DMAHRS definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 495: Dma General Purpose Output Register (Dmagpor) Register
The DMAGPOR performs no functions within the DMA2. This general purpose register is enabled when SPP_DMA2_ENABLE_GPOR is defined. This register may be used by the SoC integrator to define and display configuration information. Figure 15-22 Table 15-17 for the DMAGPOR definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 496: Dma Channel N Priority (Dchprin), N = 0,..., {15,31,63} Registers
These low-priority channels can be configured to not preempt each other, thus preventing a low-priority channel from consuming the preempt slot normally available to a true, high-priority channel. See Figure 15-23 Table 15-18 for the DCHPRIn definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 497: Transfer Control Descriptor (Tcd)
0x1000 + (32 x n) + 0x1C Beginning “Major” Iteration Count (biter) Channel Control/Status (bwc, major.linkch, done, active, major.e_link, e_sg, d_req, int_half, int_maj, start) Figure 15-24 Table define word 0 of the TCDn structure, the saddr field. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 498 0 selects the original register value for the corresponding address bit location. For this application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0-modulo-size range. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 499 — — — — nbytes[16:31] Reset — — — — — — — — — — — — — — — — Figure 15-27. TCDn Word 2 (TCDn.nbytes) field (DMACR[EMLM] = 0) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 500 This flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 The minor loop offset is not applied to the daddr. 1 The minor loop offset is applied to the daddr. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 501 This value can be applied to “restore” the source address to the initial value, or adjust the address to reference the next data structure. Figure 15-30 Table 15-25 define word 4 of the TCDn structure, the daddr field. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 502 Note: This bit must be equal to the biter.e_link bit . Otherwise, a configuration error will be reported. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 503 — — — — — — — dlast_sga[16:31] Reset — — — — — — — — — — — — — — — — Figure 15-32. TCDn Word 6 (TCDn.dlast_sga) field MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 504 Note: This bit must be equal to the citer.e_link bit. Otherwise, a configuration error will be reported. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 505 AHB bus cycles. 00 No DMA engine stalls 01 Dynamic priority elevation 10 DMA engine stalls for 4 cycles after each r/w 11 DMA engine stalls for 8 cycles after each r/w MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 506 If this flag is set, the DMA hardware automatically clears the corresponding DMAERQ bit when the current major iteration count reaches zero. 0 The channel’s DMAERQ bit is not affected. 1 The channel’s DMAERQ bit is cleared when the outer major loop is complete. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 507: Functional Description
When any other channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other addr_path.channel_{x,y}. Once the inner minor loop completes execution, the addr_path hardware writes the new values for the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 508: Dma Basic Data Flow
(addr_path) and converted into the required address to access the TCD local memory. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the dma_engine.addr_path.channel_{x,y} registers. The TCD memory MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 509 AMBA-AHB bus during the destination write. This source read/destination write processing continues until the inner minor byte count has been transferred. The dma_ipd_done[n] signal is asserted at the end of the minor byte count transfer. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 510 TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 15-36. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 511: Dma Performance
The peak transfer rates for several different source and destination transfers are shown in Table 15-29. The following assumptions apply to Table 15-29 Table 15-30: • Platform SRAM can be accessed with zero wait-states when viewed from the AMBA-AHB data phase MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 512 In this case of an IPS read and a platform SRAM write, the combined data phase time is 4 cycles. For an SRAM read and IPS write, it is 5 cycles. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 513 (3 cycles) For example: consider a platform with the following characteristics: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 514: Initialization/Application Information
4. Write the 32 byte TCD for each channel that may request service. 5. Enable any hardware service requests via the DMAERQ register. 6. Request channel service by either software (setting the TCD.start bit) or by hardware (slave device asserting its ipd_req signal). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 515: Dma Programming Errors
(channel/group) with that priority will be selected by arbitration and executed by the DMA engine. The hardware service request handshake signals, error interrupts and error reporting will be associated with the selected channel. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 516: Dma Arbitration Mode Considerations
Because channels are serviced in round robin manner, any channel that generates DMA requests faster than a combination of the group round robin service rate and the channel service rate for its group will not MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 517: Fixed Group Arbitration, Round-Robin Channel Arbitration
The final source and destination addresses are adjusted to return to their beginning values. TCD.citer = TCD.biter = 1 TCD.nbytes = 16 TCD.saddr = 0x1000 TCD.soff TCD.ssize TCD.slast = -16 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 518: Multiple Requests
The DMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s hardware requests is enabled in the DMAERQ register, channel service requests are initiated by the slave device. TCD.citer = TCD.biter . MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 519  second iteration of the minor loop read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b) write_word(0x2018)  third iteration of the minor loop read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f) write_word(0x201c)  last iteration of the minor loop  major loop complete MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 520: Tcd Status
The 'true' values of the saddr, daddr, and nbytes are the values the DMA engine is currently using in its internal register file and not the values in the TCD local memory for that channel. The MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 521: Preemption Status
TCD.citer value = 0x4 TCD.major.e_link = 1 TCD.major.linkch = 0x7 will execute as: 1. minor loop done  set channel 12 TCD.start bit 2. minor loop done  set channel 12 TCD.start bit MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 522: Dynamic Programming
The following coherency model is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. Set the TCD.major.e_link bit. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 523: Hardware Request Release Timing
AHB_AP AHB_DP hwrite ipd_req ipd_ack ipd_done done_lw ipd_complete Note: ipd_req must de-assert in this cycle unless another service request is intended Figure 15-37. ipd_req hardware handshake MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 524 Enhanced Direct Memory Access (eDMA) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 525: Introduction
The Error Correction Status Module does not include any logic which provides access control. Rather, this function is supported using the standard access control logic provided by the IPS controller. Table 16-1 is a 32-bit view of the ECSM memory map. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 526: Register Description
Register description Attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 527: Processor Core Type (Pct) Register
The MRSR contains a bit for each of the reset sources to the device. An asserted bit indicates the last type of reset that occurred. Only one bit is set at any time in the MRSR, reflecting the cause of the most recent MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 528: Miscellaneous Wakeup Control Register (Mwcr)
4. Once the appropriately high interrupt request level arrives, the interrupt controller signals its presence, and the ECSM responds by asserting an exit_low_power_mode signal. 5. The external logic senses the assertion of the exit signal, and re-enables the appropriate clock signals. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 529: Miscellaneous Interrupt Register (Mir)
During the appropriate interrupt service routine handling these requests, the interrupt source contained in the MIR must be explicitly cleared. See Figure 16-5 Table 16-6. Address: Base + 0x001F Access: User read/write FB0AI FB0SI FB1AI FB1SI Reset Figure 16-5. Miscellaneous Interrupt Register (MIR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 530: Miscellaneous User-Defined Control Register (Mudcr)
Table 16-7. Miscellaneous User-Defined Control Register (MUDCR) field descriptions Name Description MUDCR User-Defined Control Register 0 The control associated with this MUDCR bit is disabled. 1 The control associated with this MUDCR bit is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 531: Ecc Registers
In addition to the interrupt generation, the ECSM captures specific information (memory address, attributes and data, bus master number, etc.) which may be useful for subsequent failure analysis. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 532: Ecc Status Register (Esr)
The ECC Status Register is an 8-bit control register for signaling which types of properly enabled ECC events have been detected. The ESR signals the last properly enabled memory event to be detected. ECC interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection, MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 533 4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request. Figure 16-8 Table 16-9 for the ECC Status Register definition. Address: Base + 0x0047 Access: User read/write R1BC F1BC RNCE FNCE Reset Figure 16-8. ECC Status Register (ESR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 534: Ecc Error Generation Register (Eegr)
It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash memory. The ability to program the non-volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 535 Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 536 Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 537: Flash Ecc Address Register (Fear)
— — FEAR[16:31] Reset — — — — — — — — — — — — — — — — Figure 16-10. Flash ECC Address Register (FEAR) Value is undefined at reset. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 538: Flash Ecc Master Number Register (Femr)
Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored. See Figure 16-12 Table 16-13 for the Flash ECC Attributes Register definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 539: Flash Ecc Data Register (Fedr)
— — — — — — — FEDR[16:31] Reset — — — — — — — — — — — — — — — — Figure 16-13. Flash ECC Data Register (FEDR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 540: Ram Ecc Address Register (Rear)
REMR, REAT, and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored. See Figure 16-15 Table 16-16 for the RAM ECC Syndrome Register definition. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 541 0x20 ECC ODD[5] 0x4A DATA ODD BANK[1] 0x22 DATA ODD BANK[20] 0x4C DATA ODD BANK[0] 0x24 DATA ODD BANK[19] 0x03,0x05..0x4D Multiple bit error 0x26 DATA ODD BANK[18] > 0x4D Multiple bit error MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 542: Ram Ecc Master Number Register (Remr)
RAM ECC Attributes Register definition. Address: Base + 0x0067 Access: User read-only Write Size[0:2] Protection[0:3] Reset — — — — — — — — Figure 16-17. RAM ECC Attributes (REAT) Register Value is undefined at reset. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 543: Ram Ecc Data Register (Redr)
REDR[0:31] This 32-bit register contains the data associated with the faulting access of the last properly enabled RAM ECC event. The register contains the data value taken directly from the data bus. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 544: High-Priority Enables
Identical logic is replicated for each of the five targeted slave modules. A block diagram of the spp_ips_reg_protection module is shown in Figure 16-19. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 545 Error Correction Status Module (ECSM) ips_xfr_wait[0] ips_xfr_err[0] INTC qual_ips_mod_en[0] ips_supervisor_access ips_xfr_wait[1] ips_xfr_err[1] ECSM qual_ips_mod_en[1] ips_module_en[4:0] final_ips_xfr_wait[4:0] ips_xfr_wait[2] ips_xfr_err[2] PBRIDGE SPP_IPS_REG_PROTECTION final_ips_xfr_err[4:0] qual_ips_mod_en[2] _LITE ips_xfr_wait[3] ips_xfr_err[3] qual_ips_mod_en[3] ips_xfr_wait[4] ips_xfr_err[4] qual_ips_mod_en[4] Figure 16-19. Spp_Ips_Reg_Protection Block Diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 546 Error Correction Status Module (ECSM) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 547: Introduction
Array 0 Array 1 (Bank 0) (Bank 1) (Bank 2) Figure 17-1. MPC5606S flash memory architecture 17.2 Program flash memory (code flash 0 and code flash 1) 17.2.1 Introduction The primary function of the program flash module is to serve as electrically programmable and erasable non-volatile memory.
Page 548: Main Features
The read data bus is 128 bits wide, while the flash memory registers are on a separate 32-bit bus addressed in the user memory map. The high voltages needed for program/erase operations are internally generated. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 549: Functional Description
A programmed bit in the flash module reads as logic level 0 (or low). An erased bit in the flash module reads as logic level 1 (or high). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 550: Flash Module Sectorization
Reserved On-chip Flash Memories (Shadow for Code Flash) 0x00200000 0x00203FFF — Code Flash Array 0 Shadow block 0x00204000 0x003FFFFF 2032 — — — — Reserved On-chip Flash Memories (Test for Code Flash) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 551 Table 17-2. Test flash structure for Code flash 0 (block 0) Name Description Addresses Size User OTP Area 0x400000 to 0x401FFF 8192 byte Reserved 0x402000 to 0x403CFF 7424 byte User Reserved 0x403D00 to 0x403DE7 232 byte MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 552 Erase of Test flash block is always locked. Program of the Test flash block has similar restriction as the array in terms of how ECC is calculated. Only one program is allowed per 64-bit ECC segment. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 553: User Mode Operation
8 byte — Reserved 0x203E20 to 0x203FFF 480 byte 17.2.5 User mode operation In User mode, the flash module may be read and written (register writes and interlock writes), programmed, or erased. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 554: Reset
Software executing from flash must not write to registers that control flash behavior, e.g., wait state settings or prefetch enable/disable. Doing so can cause data corruption. On MPC5606S devices these registers include PFCR0, BIU1, and BIU2. Further, flash configuration registers should be written only with 32-bit write operations to avoid any issues associated with register “incoherency”...
Page 555: Power-Down Mode
When exiting from Low-Power mode the flash memory module returns to its previous state in all cases unless it was in the process of executing an erase high-voltage operation at the time of entering Low-Power mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 556: Register Description
User Multiple Input Signature Register 2 (UMISR2) 0x0050 on page 578 User Multiple Input Signature Register 3 (UMISR3) 0x0054 on page 578 User Multiple Input Signature Register 4 (UMISR4) 0x0058 on page 579 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 557: Module Configuration Register (Mcr)
PGM PSUS ERS ESUS EHV rc/0 rc/0 rw/0 rw/0 rw/0 rw/0 rw/0 Figure 17-3. Module Configuration Register (MCR) The Module Configuration Register is used to enable and monitor all the modify operations of the flash module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 558 Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0 will have no effect. 0: Reads are occurring normally. 1: An ECC double Error occurred during a previous read. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 559 , time equals to Erase Suspend Latency) after a 0 to 1 transition of ESUS, ESUS which suspends an erase operation. 0: Flash is executing a high voltage operation. 1: Flash is not executing a high voltage operation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 560 ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0: Flash is not executing an Erase sequence. 1: Flash is executing an Erase sequence. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 561 0: Flash is not enabled to perform an high voltage operation. 1: Flash is enabled to perform an high voltage operation. Table 17-9. Array Space Size SIZE2-0 Array Space Size 128KB 256KB 512KB Reserved (1024KB) Reserved (1536KB) Reserved (2048KB) 64KB Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 562: Low/Mid Address Space Block Locking Register (Lml)
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level will be written. 17.2.6.2 Low/Mid Address Space Block Locking Register (LML) Address Offset: 0x0004 Reset value: 0x00XXXXXX, initially determined by NVLML value from test sector. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 563: 17.2.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (Nvlml
0: Low Address Locks are disabled: TSLK, MLK1-0 and LLK15-0 cannot be written. 1: Low Address Locks are enabled: TSLK, MLK1-0 and LLK15-0 can be written. Reserved (Read Only).  1:10 Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 564 MLK is not writable unless LME is high. 0: Mid Address Space Block is unlocked and can be modified (if also SLL.SMLK=0). 1: Mid Address Space Block is locked and cannot be modified. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 565: High Address Space Block Locking Register (Hbl)
The HBL register has a related Non-Volatile High Address Space Block Locking register located in Test flash that contains the default reset value for HBL: The NVHBL register is read during the reset phase of the flash module and loaded into the HBL. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 566: Secondary Low/Mid Address Space Block Locking Register (Sll)
1: High Address Space Block is locked and cannot be modified. 17.2.6.6 Secondary Low/Mid Address Space Block Locking Register (SLL) Address Offset: 0x000C Reset value: 0x00XXXXXX, initially determined by NVSLL, located in test sector. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 567 1: Secondary Low/Mid Address Locks are enabled: STSLK, SMK1-0 and SLK15-0 can be written. Reserved (Read Only).  1:10 Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 568 SMK is not writable unless SLE is high. 0: Mid Address Space Block is unlocked and can be modified (if also LML.MLK=0). 1: Mid Address Space Block is locked and cannot be modified. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 569: Low/Mid Address Space Block Select Register (Lms)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on during erase. Table 17-16. LMS field descriptions Field Description Reserved (Read Only).  0:13 Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 570: High Address Space Block Select Register (Hbs)
Figure 17-8. High Address Space Block Select Register (HBS) The High Address Space Block Select register provides a means to select blocks to be operated on during erase. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 571: Address Register (Adr)
ECC single error correction occurs. Table 17-18. ADR field descriptions Field Description Reserved (Read Only).  Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 572 Address of first ECC Double Error MCR.RWE = 1 Address of first RWW Error MCR.PEG = 0 Address of first FPEC Error MCR.EDC = 1 Address of first ECC Single Error Correction MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 573: Bus Interface Unit 0 Register (Biu0)
The Bus Interface Unit 1 Register provides a mean for BIU specific information, or BIU configuration information to be stored. Please see Section 17.4.3.2.2, Platform Flash Configuration Register 1 (PFCR1), for more information about register description. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 574: Bus Interface Unit 2 Register (Biu2)
BIU2. The NVBIU2 register is a 64-bit register, the 32 most significant bits of which (bits 63-32) are ‘don’t care’ and eventually used to manage ECC codes. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 575: User Test 0 Register (Ut0)
For UTE the password 0xF9F99999 must be written to the UT0 register. Reserved (Read Only).  Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 576 This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: Array Integrity sequence is proprietary sequence. 1: Array Integrity sequence or Margin mode sequence is sequential. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 577: User Test 1 Register (Ut1)
These bits represent the input of even word of ECC logic used in the ECC Logic Check. The DAI31-00 correspond to the 32 array bits representing Word 0 within the double word. 0: The array bit is forced at 0. 1: The array bit is forced at 1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 578: User Test 2 Register (Ut2)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity. The User Multiple Input Signature Register 0 represents the bits 31-0 of the whole 144 bits word (2 Double Words including ECC). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 579: User Multiple Input Signature Register 1 (Umisr1)
These bits represent the MISR value obtained accumulating the bits 63-32 of all the pages read from the flash memory.  The MS can be seeded to any value by writing the UMISR1 register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 580: User Multiple Input Signature Register 2 (Umisr2)
Figure 17-19. User Multiple Input Signature Register 3 (UMISR3) The Multiple Input Signature Register provides a mean to evaluate the Array Integrity. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 581: User Multiple Input Signature Register 4 (Umisr4)
Double Word; bits 4-5 and 20-21 of MISR are respectively the double and single ECC error detection for odd and even Double Word. The UMISR4 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 582: Non-Volatile Private Censorship Password 0 Register (Nvpwd0)
Censorship information contained in NVSCI0–1 registers. Table 17-31. NVPWD0 field descriptions Field Description 0:31 PWD31-00: PassWorD 31-00 (Read/Write) The PWD31-00 registers represent the 32 LSB of the Private Censorship Password. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 583: Non-Volatile Private Censorship Password 1 Register (Nvpwd1)
The NVSCI0 is a non-volatile register located in Shadow block: it is read during the reset phase of the flash module and the protection mechanisms are activated consequently. The parts are delivered uncensored to the user. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 584: Non-Volatile System Censoring Information 1 Register (Nvsci1)
These bits represent the 16 MSB of the Censorship Control Word (CCW). If CW15-0 = 0x55AA and NVSCI1 = NVSCI0 the Censored mode is disabled. If CW15-0  0x55AA or NVSCI1  NVSCI0 the Censored mode is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 585: Non-Volatile User Options Register (Nvusro)
If the device undergoes a non-destructive reset, the behavior of SWT after reset will again be controlled by this field. Any change in the value of this field will take effect only after the device goes through a Phase 0 (destructive reset sequence). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 586: Programming Considerations
1. Wait for operation completion: wait for bit MCR.DONE (or UT0.AID) to go high. 2. Check operation result: check bit MCR.PEG (or compare UMISR0-4 with expected value). 3. Switch-Off FPEC by resetting MCR.EHV (or UT0.AIE). 4. Deselect current operation by clearing MCR.PGM/ERS (or UT0.MRE/EIE). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 587 5. Wait until the MCR.DONE bit goes high. 6. Confirm MCR.PEG=1. 7. Write a logic 0 to the MCR.EHV bit. 8. If more addresses are to be programmed, return to step 2. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 588 The erase sequence is fully automated within the flash memory. The user only needs to select the blocks to be erased and initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are selected for erase during an erase sequence, no specific operation order must be assumed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 589 /* Reset EHV in MCR: Operation End */ = 0x00000000; /* Reset ERS in MCR: Deselect Operation */ Erase suspend/resume The erase sequence may be suspended to allow read access to the flash core. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 590 Array Integrity is checked using a predefined address sequence (proprietary), and this operation is executed on selected and unlocked blocks. Once the operation is completed, the results of the reads can be MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 591 While UT0.AID is low and UT0.AIE is high, the user may clear AIE, resulting in a Array Integrity Check abort. UT0.AID must be checked to know when the aborting command has completed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 592 8. Compare UMISR0-4 content with the expected result. 9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits. 10. If more blocks are to be checked, return to step 2. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 593 5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check. 6. Wait until the UT0.AID bit goes high. 7. Compare UMISR0-4 content with the expected result. 8. Write a logic 0 to the UT0.AIE bit. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 594: Error Correction Code (Ecc)
The reset state of all the Volatile Modify Protection Registers is the protected state. All the non-volatile Modify Protection registers can be programmed through a normal Double Word Program operation at the related locations in Test flash. The non-volatile Modify Protection registers cannot be erased. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 595 If bits SC15-0 of NVSCI0 are programmed at 0x55AA and NVSC1 = NVSCI0 the Public Access is disabled, while all the other possible values enable the Public Access. The parts are delivered to the user with Censored mode and Public Access disabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 596: Introduction
A BIU connects the flash module to a system bus, and contains all system-level customization required for the SoC application. 17.3.2 Main features • High Read parallelism (128 bits) • Error Correction Code (SEC-DED) to enhance Data Retention • Double Word Program (64 bits) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 597: Block Diagram
The high voltages needed for Program/Erase operations are internally generated addressed in user memory map. HV generator Flash Program/Erase Controller Flash Bank 0 64 KB + 16KB Test Flash Flash Registers Registers Matrix Interface Interface Figure 17-26. Flash macrocell structure MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 598: Functional Description
17-38. Table 17-38. 80 KB flash module sectorization Bank Sector Addresses Size Address Space B1F0 0x00800000 to 0x00803FFF 16 KB Low Address Space B1F1 0x00804000 to 0x00807FFF 16 KB Low Address Space MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 599 User mode program of the test block are enabled only when MCR.PEAS is high, also if the Shadow block is available. The Test flash block may be locked/unlocked against program by using the LML.TSLK and SLL.STSLK registers. Erase of the Test flash block is always locked in user mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 600: User Mode Operation
On the contrary, register read/write accesses simultaneous to a flash memory matrix interlock write are forbidden. 17.3.5.1 Reset A reset is the highest priority operation for the flash module and terminates all other operations. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 601: Power-Down Mode
The wakeup time from Low-Power mode is faster than the wakeup time from Power-Down mode. The user may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Low-Power mode is exited. Write access is locked on all the registers in Low-Power mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 602: Register Description
During the flash memory initialization phase, the FPEC reads these non-volatile registers and update their related Volatile Registers. When the FPEC detects ECC double errors in these special locations, it behaves in the following way: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 603: Module Configuration Register (Mcr)
The function of this bit is SoC dependent and it can be configured to be disabled. 0: Reads are occurring normally. 1: An ECC Single Error occurred and was corrected during a previous read. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 604 0: Reads are occurring normally. 1: A RWW Error occurred during a previous read. 18:19 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 605 0 Program or Erase operation failed. 1 Program or Erase operation successful. 23:26 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 606 Erase. The flash module cannot exit Erase Suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0: Erase sequence is not suspended. 1: Erase sequence is suspended. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 607: Low/Mid Address Space Block Locking Register (Lml)
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level will be written. 17.3.6.2 Low/Mid Address Space Block Locking Register (LML) Address Offset: 0x0004 Reset value: 0x00XXXXXX, initially determined by NVLML value from test sector. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 608: 17.3.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (Nvlml
0: Low Address Locks are disabled: TSLK, MLK1-0 and LLK15-0 cannot be written. 1: Low Address Locks are enabled: TSLK, MLK1-0 and LLK15-0 can be written. Reserved (Read Only).  1:10 Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 609 MLK is not writable unless LME is high. 0: Mid Address Space Block is unlocked and can be modified (if also SLL.SMLK=0). 1: Mid Address Space Block is locked and cannot be modified. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 610: High Address Space Block Locking Register (Hbl)
HBL. The NVHBL register is a 64-bit register, the 32 most significant bits of which (bits 63-32) are ‘don’t care’ and eventually used to manage ECC codes. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 611: Secondary Low/Mid Address Space Block Locking Register (Sll)
1: High Address Space Block is locked and cannot be modified. 17.3.6.6 Secondary Low/Mid Address Space Block Locking Register (SLL) Address Offset: 0x000C Reset value: 0x00XXXXXX, initially determined by NVSLL, located in test sector MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 612 1: Secondary Low/Mid Address Locks are enabled: STSLK, SMK1-0 and SLK15-0 can be written. Reserved (Read Only).  1:10 Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 613 SMK is not writable unless SLE is high. 0: Mid Address Space Block is unlocked and can be modified (if also LML.MLK=0). 1: Mid Address Space Block is locked and cannot be modified. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 614: Low/Mid Address Space Block Select Register (Lms)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on during erase. Table 17-47. LMS field descriptions Field Description Reserved (Read Only).  0:13 Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 615: High Address Space Block Select Register (Hbs)
Figure 17-32. High Address Space Block Select Register (HBS) The High Address Space Block Select register provides a means to select blocks to be operated on during erase. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 616: Address Register (Adr)
ECC single error correction occurs. Table 17-49. ADR field descriptions Field Description Reserved (Read Only).  Write these bits has no effect and read these bits always outputs 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 617 Address of first ECC Double Error MCR.RWE = 1 Address of first RWW Error MCR.PEG = 0 Address of first FPEC Error MCR.EDC = 1 Address of first ECC Single Error Correction MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 618: User Test 0 Register (Ut0)
This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 619 Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the MISR (UMISR0-4) can be checked. 0: Array Integrity Check is on-going. 1: Array Integrity Check is done. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 620: User Test 1 Register (Ut1)
The User Test 2 Register allows to enable the checks on the ECC logic related to the 32 MSB of the Double Word. The User Test 2 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 621: User Multiple Input Signature Register 0 (Umisr0)
These bits represent the MISR value obtained accumulating the bits 31-0 of all the pages read from the flash memory.  The MS can be seeded to any value by writing the UMISR0 register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 622: User Multiple Input Signature Register 1 (Umisr1)
MS07 MS06 MS06 MS06 MS06 MS06 MS06 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 Figure 17-39. User Multiple Input Signature Register 2 (UMISR2) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 623: User Multiple Input Signature Register 3 (Umisr3)
These bits represent the MISR value obtained accumulating the bits 127-96 of all the pages read from the flash memory.  The MS can be seeded to any value by writing the UMISR3 register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 624: User Multiple Input Signature Register 4 (Umisr4)
All the sectors of the flash module belong to the same partition (Bank), therefore when a Modify operation is active on some sectors no read access is possible on any other sector (Read-While-Modify is not supported). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 625: Double Word Program
Double Word program A flash memory program sequence operates on any double word within the flash core. As many as two words within the Double word may be altered in a single program operation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 626 MCR.PEAS to be set/cleared. An interlock write must be performed before setting MCR.EHV. The user may terminate a program sequence by clearing MCR.PGM prior to setting MCR.EHV. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 627: Sector Erase
3. Write to any address in flash memory. This is referred to as an erase interlock write. 4. Write a logic 1 to the MCR.EHV bit to start the internal erase sequence or skip to step 9 to terminate. 5. Wait until the MCR.DONE bit goes high. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 628 MCR.DONE will go high no more than t after MCR.ESUS is set to 1. ESUS Once suspended, the array may be read. flash core reads while MCR.ESUS = 1 from the block(s) being erased return indeterminate data. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 629: User Test Mode
1. The first pass will scan only bits 31-0 of each page. 2. The second pass will scan only bits 63-32 of each page. 3. The third pass will scan only bits 95-64 of each page. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 630 = UMISR2; /* Read UMISR2 content*/ data3 = UMISR3; /* Read UMISR3 content*/ data4 = UMISR4; /* Read UMISR4 content*/ = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */ MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 631 /* Set UTE in UT0: Enable User Test */ = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */ = 0x80000004; /* Set AIS in UT0: Select Operation */ = 0x80000024; /* Set MRE in UT0: Select Operation */ MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 632 = UMISR3; /* Read UMISR3 content (expected 0xAAAAAAAA) */ data4 = UMISR4; /* Read UMISR4 content (expected 0x00FF00FF) */ = 0x00000000; /* Reset UTE, AIE and EIE in UT0: Operation End */ MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 633: Error Correction Code (Ecc)
As an example the ECC algorithm allows to start from an All 1s Double Word value and rewrite whichever of its four 16-bits Half-Words to an All 0s content by keeping the same ECC value. Table 17-60 shows a set of Double Words sharing the same ECC value. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 634: Eeprom Emulation
The non-volatile modify protection registers cannot be erased. • The non-volatile modify protection registers are physically located in Test flash, their bits can be programmed to 0 only once and they can no more be restored to 1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 635: Censored Mode
A block diagram of the e200z0h Power Architecture reduced product platform (RPP) reference design is shown below in Figure 17-42 with the PFLASH2P_LCA module and its attached off-platform flash memory arrays highlighted. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 636 Platform RAM memory controller (PRAM) • AHB-to-{IPS/APB} bus controller (PBRIDGE-Lite) for access to on- and off-platform slave modules • Interrupt Controller (INTC) • 4-channel System Timers (STM) • Software Watchdog Timer (SWT) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 637 Finally since the page buffers and temporary holding registers are associated with both an AHB input port and a flash bank, they use a bx_py nomenclature. For example, the b0_p0 page buffer refers to the bank0, port 0 storage elements. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 638: Overview
— Programmable arbitration allows the user to select fixed priority or round-robin • Total flash page storage in the PFLASH2P_LCA includes four 4-entry page buffers (b0_p0, b0_p1, b2_p0, b2_p1) and two 128-bit temporary holding registers (b1_p0, b1_p1). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 639 Support for reporting of single- and multi-bit flash ECC events • Typical operating configuration loaded into programming model by system reset Figure 17-43 shows a simplified block diagram of the PFLASH2P_LCA memory controller. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 640 Triple-Bank b0_p1 4x128 Flash Interface p0_hrdata bk0_fl_rdata b0_p0 4x128 p0_hwdata config control bk0_fl_wdata p0_haddr+hattr bk0_fl_addr, control array0_biu0_regout[31:0] array0_biu1_regout[31:0] array0_biu2_regout[31:0] array0_biu3_regout[31:0] h d t Figure 17-43. PFLASH2P_LCA memory controller block diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 641: Modes Of Operation
4 Mbyte spaces for bank0 and bank2 and an 8 Mbyte space for bank1. In addition to the actual flash memory regions, there are shadow and test sectors included in the system memory map. The MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 642 Reserved for Data flash array 3: test sector 0x00E0_0000 0x00FF_FFFF 2048 Reserved 0x0100_0000 0x1FFF_FFFF 507904 Emulation Mapping 0xFFE8_8000 0xFFE8_BFFF Code flash array 0 configuration 0xFFE8_C000 0xFFE8_FFFF Data flash array 0 configuration 0xFFEB_0000 0xFFEB_3FFF Code flash array 1 configuration MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 643: Register Descriptions
647 + 0x024 17.4.3.2 Register descriptions This section details the individual registers of the PFLASH2P_LCA. To be consistent with the flash documentation, this description uses a LSB=0 vector bit numbering convention. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 644 Platform Flash Configuration Register 0 (PFCR0) This register defines the configuration associated with flash memory banks 0 and 2. Collectively, this corresponds to the “code flash” and the operating configuration defined by certain fields applies to both MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 645 This field is set to 0b00010 by hardware reset. 00000 No additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added 111111 31 additional wait-states are added MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 646 This field is cleared by hardware reset. 0 No prefetching is triggered by an instruction fetch read access 1 If page buffers are enabled (B02_P1_BFE = 1), prefetching is triggered by any instruction fetch read access MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 647 0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 648 No additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added 111111 31 additional wait-states are added This field is ignored in single bank flash configurations. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 649 Prefetching capabilities are defined on a per master basis. This register also defines the arbitration mode between the 2 AHB ports for the PFLASH2P_LCA. The register is described below in Figure 17-46 Table 17-66. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 650: Functional Description
Figure 17-43 will assist in understanding much of the discussion in this section. The PFLASH2P_LCA interfaces between 2 AHB-Lite 2.v6 system bus master ports and three banks of low-cost flash memory arrays. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 651: Access Protections
If the flash access was the result of a speculative prefetch to the next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not changed to most-recently-used until a subsequent buffer hit occurs. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 652: Read Cycles—Buffer Hit
While this circumstance should not occur, this does not result in an error condition being reported, as this behavior is initiated by the AHB master. In this circumstance, the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 653: Access Pipelining
Subsequent flash accesses that “hit” the buffer, that is, the current access address matches the address stored in the buffer, can be serviced in 0 AHB wait-states as the stored read data is routed from the given page buffer back to the requesting bus master. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 654 In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be non-zero and either instruction prefetching (Bx_Py_IPFE) or data prefetching (Bx_Py_DPFE) enabled. Recall the prefetch MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 655 In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ECC event. Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on haddr[28:24] to support wait-state emulation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 656: Bank1 Temporary Holding Registers
17.4.4.10 Input port arbitration For maximum system performance, the PFLASH2P_LCA fully supports concurrent flash accesses from the two AHB input ports when the references are targeted to different flash banks. This is expected to be MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 657: Read-While-Write Functionality
For this setting, the read request is captured and retried as described for the basic stall-while-write, plus the program/erase operation is aborted by the PFLASH2P_LCA’s assertion of the bkn_fl_abort signal. The MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 658: Wait-State Emulation
These wait-states are applied to the initial access of a burst fetch or to single-beat read accesses on the AHB system bus. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 659: Timing Diagrams
(PFLASH, PRAM) are designed to provide a zero wait-state data phase response to maximize processor performance. The following diagrams illustrate operation of various cycle types and responses referenced earlier in this chapter including stall-while-read (Figure 17-51) and abort-while-read (Figure 17-52) diagrams. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 660 C(y) C(y+4) C(y+8) C(y+12) Figure 17-47. 1-cycle access, no buffering, no prefetch MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 661 C(y) bkn_fl_rdata C(y+4) bkn_fl_xfr_err Figure 17-48. 3-cycle access, no prefetch, buffering disabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 662 C(y) C(y+4) C(y+8) C(y+12) hrdata hwdata hready_out okay okay okay okay okay okay okay okay hresp bkn_fl_addr bkn_fl_rd_en addr y bkn_fl_wr_en bkn_fl_rdata C(y) bkn_fl_xfr_err Figure 17-49. 3-cycle access, no prefetch, buffering enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 663 C(y) bkn_fl_rdata C(y+16) bkn_fl_xfr_err Figure 17-50. 3-cycle access, prefetch and buffering enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 664 Bn_RWWC control field, the hardware may also signal a stall notification interrupt (if Bn_RWWC = 110). The stall notification interrupt is shown as the optional assertion of ECSM’s MIR[FBnSI] (flash bank n stall interrupt). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 665: Initialization / Application Information
For example, if the core is accessing sequential instructions starting at location 0, the first 32 bits (one line) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 666: Flash Memory Setting Recommendations
(such as for graphics) which are larger than a line buffer, so prefetching data would make sense. If graphic data were not in the internal flash, then prefetching data on port 1 would not be expected to be a benefit. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 667 Prefetch Limit B0_P1_PFLIM = 1 Prefetch on miss — — only (allows more bandwidth for core) Page Buffer B0_P1_BCFG = 0 All 4 line buffers — — Configuration available for any access MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 668 1 for core instructions, write access (3) for the core data bus, but read access only eDMA and DCU (1) for core instructions, eDMA and DCU. Result value for recommendations in PFAPR = 0x03F2 005D MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 669 Flash Memory MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 670 Flash Memory MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 671: Introduction
EMI environment of a vehicle, cost-effectiveness, and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B [Ref. 1], which supports both standard and extended MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 672: Flexcan Module Features
Global network time, synchronized by a specific message • Maskable interrupts • Independent of the transmission medium (an external transceiver is assumed) • Short latency time due to an arbitration scheme for high-priority messages MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 673: Modes Of Operation
External signal description 18.2.1 Overview The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in Table 18-1 and described in more detail in the next subsections. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 674: Signal Descriptions
These two ranges are completely occupied by RAM (1056 and 256 bytes, respectively) only when FlexCAN is configured with 64 MBs. When it is configured with 16 MBs, the memory sizes are 288 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 675 Base + Rx Individual Mask Registers on page 696 0x0880–0x08BF RXIMR0–RXIMR15 Base + Rx Individual Mask Registers on page 696 0x08C0–0x08FF RXIMR16–RXIMR31 Base + Rx Individual Mask Registers on page 696 0x0900–0x097F RXIMR32–RXIMR63 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 676: Message Buffer Structure
1 Recessive value is compulsory for transmission in Extended Format frames ID Extended Bit This bit identifies whether the frame format is standard or extended. 0 Frame format is standard 1 Frame format is extended MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 677 MB does not participate in the matching process. 0100 EMPTY: MB is active and 0010 MB participates in the matching process. When empty. a frame is received successfully, the code is automatically updated to FULL. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 678 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. 1100 0100 Transmit remote frame unconditionally once. After transmission, the MB automatically becomes an Rx MB with the same ID. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 679: Rx Fifo Structure
ID table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have the same format. See Section 18.4.7, Rx FIFO for more information. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 680 (Standard =2-12, Extended = 2-15) (Standard = 18-28, Extended = 18-31) RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3 (Std/Ext = 0-7) (Std/Ext = 8-15) (Std/Ext = 16-23) (Std/Ext = 24-31) Figure 18-4. ID Table 0–7 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 681: Register Descriptions
Most of the fields in this register can be accessed at any time, except the MAXMB field, which should only be changed while the module is in Freeze mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 682 (0x80–0xFF) is used by the FIFO engine. See Section 18.3.3, Rx FIFO Structure, and Section 18.4.7, Rx FIFO, for more information. 0 FIFO not enabled 1 FIFO enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 683 0 Affected registers are in Unrestricted memory space 1 Affected registers are in Supervisor memory space—any access without supervisor permission behaves as though the access was done to an unimplemented register location MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 684 This bit is supplied for backwards compatibility reasons. When asserted, it enables the Tx abort feature. This feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in the CAN bus without notification. 0 Abort disabled 1 Abort enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 685: Control Register (Ctrl)
Freeze mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK, and BOFF_REC bits, which can be accessed at any time. Address: Base + 0x0004 Access: User read/write PRESDIV PSEG1 PSEG2 Reset PROPSEG Reset Figure 18-6. Control Register (CTRL) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 686 Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is negated. 0 Tx Warning Interrupt disabled 1 Tx Warning Interrupt enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 687 This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the LPRIO_EN bit does not affect the priority arbitration. 0 Buffer with highest priority is transmitted first 1 Lowest number buffer is transmitted first MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 688: Free Running Timer (Timer)
If desired, software can poll the register to discover when the data was actually written. Address: Base + 0x0008 Access: User read/write Reset TIMER Reset Figure 18-7. Free Running Timer (TIMER) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 689: Rx Global Mask (Rxgmask)
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 Reset MI15 MI14 MI13 MI12 MI11 MI10 MI9 Reset Figure 18-8. Rx Global Mask Register (RXGMASK) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 690: Rx 14 Mask (Rx14Mask)
CAN protocol and are completely implemented in the FlexCAN module. Both counters are read-only, except in Freeze mode where they can be written by the CPU. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 691 119 and 127 to resume the Error Active state. Address: Base + 0x001C Access: User read/write Reset Rx_Err_Counter Tx_Err_Counter Reset Figure 18-9. Error Counter Register (ECR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 692: Error And Status Register (Esr)
Control Register (RWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing 1 to it. Writing 0 has no effect. 0 No such occurrence 1 The Rx error counter transitioned from < 96 to  96 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 693 0 No such occurrence 1 Rx_Err_Counter 96 IDLE CAN bus Idle state This bit indicates when CAN bus is in Idle state. 0 No such occurrence 1 CAN bus is now idle MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 694: Interrupt Mask Register High (Imrh)
CPU to determine which buffer generates an interrupt after a successful transmission or reception (for example, when the corresponding IFRH bit is set). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 695: Interrupt Mask Register Low (Imrl)
(for example, when the corresponding IFRL bit is set). Address: Base + 0x0028 Access: User read/write Reset Reset Figure 18-12. Interrupt Mask Register Low (IMRL) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 696: Interrupt Flag Register High (Ifrh)
When the AEN bit in the MCR is set (Abort enabled), while the IFRL bit is set for an MB configured as Tx, the writing access done by the CPU into the corresponding MB will be blocked. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 697 If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these flags are not used and must be considered as reserved locations. 0 No such occurrence 1 Corresponding MB completed transmission/reception MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 698: Rx Individual Mask Registers (Rximr0–Rximr63)
Base + 0x0888 RXIMR2 Base + 0x08C8 RXIMR18 Base + 0x088C RXIMR3 Base + 0x08CC RXIMR19 Base + 0x0890 RXIMR4 Base + 0x08D0 RXIMR20 Base + 0x0894 RXIMR5 Base + 0x08D4 RXIMR21 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 699: Functional Description
1000, or 1001 will be temporarily deactivated (will not participate in the current arbitration or matching run) when the CPU writes to the Control and Status field of that MB (see Section 18.4.6.2, Message Buffer deactivation). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 700: Transmit Process
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 701: Receive Process
Table 18-6 Section 18.3.2, Message Buffer structure). 4. A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 702: Matching Process
The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 703 RAM, so they are not initialized out of reset. Also, they can only be programmed if the BCC bit is asserted and while the module is in Freeze mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 704: Data Coherence
If the CODE field that was read is different from the value that was written, the CPU must read the corresponding interrupt flag to check if the frame was transmitted or is currently being transmitted. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 705: Message Buffer Deactivation
The lock is released when the CPU reads the Free Running Timer (global unlock operation), or when it reads the Control and Status word of another MB. The MB locking is done to prevent a new frame to be written into the MB while the CPU is reading it. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 706: Rx Fifo
CPU and subsequent frames are not accepted until the CPU creates space in the 1. In previous FlexCAN versions, reading the Control and Status word locked the MB even if it was EMPTY. This behavior will be honored when the BCC bit is negated. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 707: Can Protocol Related Features
Remote Request frames that match the FIFO filtering criteria. If the remote frame matches one of the target IDs, it will be stored in the FIFO and presented to the CPU. Note that for filtering formats A and B, it is MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 708: Overload Frames
MCU may not have a PLL, in which case it would have only the oscillator clock, or it may use only the PLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit in the CTRL Register has no effect on the module operation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 709 Time Þ Quanta 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. See also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 710 1 .. 3 5 .. 12 1 .. 4 6 .. 13 1 .. 4 7 .. 14 1 .. 4 8 .. 15 1 .. 4 9 .. 16 1 .. 4 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 711: Arbitration And Matching Timing
CAN bit timing is programmed to have eight time quanta per bit, then the prescaler factor (PRESDIV + 1) should be at least two. For a prescaler factor MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 712: Modes Of Operation: Details
Sets the NOT_RDY and LPM_ACK bits in MCR The Bus Interface Unit continues to operate, enabling the CPU to access memory-mapped registers, except the Free Running Timer, the Error Counter Register, and the Message Buffers, which cannot be accessed MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 713: Interrupts
MCR. 18.4.11 Bus interface CPU access to FlexCAN registers is subject to the following rules: • Read and write access to supervisor registers in User mode results in access error. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 714: Initialization/Application Information
MCR Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected by reset, so they are not automatically initialized. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 715: Flexcan Addressing And Ram Size Configurations
MAXMB field in the MCR Register. For 16 MB configuration, MAXMB can be any number between 0–15. For 32 MB configuration, MAXMB can be any number between 0–31. For 64 MB configuration, MAXMB can be any number between 0 – MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 716 FlexCAN MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 717: Introduction
IEEE 1149.1-2001 standard. In addition, instructions can be executed that allow the Test Access Port (TAP) to be shared with other modules on the MCU. All data input to and output from the JTAGC is communicated in serial format. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 718: Features
The boundary scan register is external to JTAGC but can be accessed by JTAGC TAP through the EXTEST, SAMPLE, and SAMPLE/PRELOAD instructions. The functionality of each test mode is explained in more detail in Section 19.8.4, JTAGC instructions. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 719: Bypass Mode
JTAGC regains control of the JTAG port during the Update-DR state if the PAUSE-DR state was entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive. For more information on the TAP controllers refer to Chapter 26, Nexus Development Interface (NDI). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 720: External Signal Description
NOTE The JTAG Clock (TCK) typically operates at a frequency well below the system clock frequency, as specified in the MPC5606S Microcontroller Data Sheet. In some cases, however, the system clock frequency may be lowered significantly from the normal operating range. If the system clock...
Page 721: Instruction Register
IR[4:0]: 0_0001 (IDCODE) Access: R/O 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset Figure 19-3. Device Identification Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 722: Boundary Scan Register
Data is shifted between TDI and TDO through the selected register starting with the least significant bit, as illustrated in Figure 19-4. This applies for the instruction register, test data registers, and the bypass register. Selected register Figure 19-4. Shifting Data Through a Register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 723: Tap Controller State Machine
TMS signal sampled on the rising edge of the TCK signal. Figure 19-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the Test-Logic-Reset state. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 724 NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 19-5. IEEE 1149.1-2001 TAP Controller finite state machine MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 725: Selecting An Ieee 1149.1-2001 Register
By mistake, the Access to Nexus Port Controller is not using the standard PowerPC instruction. For silicon cut2, the instruction coding will be changed to be 100% compatible with existing PowerPC. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 726: Bypass Instruction
Typically, the preloaded data is loaded into the boundary scan register using the SAMPLE/PRELOAD instruction before the selection of EXTEST. EXTEST asserts the MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 727: Idcode Instruction
The boundary scan register consists of this shift-register chain, and is connected between TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register chain contains a serial input and serial output, as well as clock and control signals. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 728: E200Z0 Once Controller
19.9.2.1 Enabling the TAP controller To access the e200z0 OnCE controller, the proper JTAGC instruction needs to be loaded in the JTAGC instruction register, as discussed in Section 19.5.2.2, TAP sharing mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 729: E200Z0 Once Controller Register Description
Instruction Address Compare 3 (IAC3) 010 0011 Instruction Address Compare 4 (IAC4) 010 0100 Data Address Compare 1 (DAC1) 010 0101 Data Address Compare 2 (DAC2) 010 0110 Data Value Compare 1 (DVC1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 730: Initialization/Application Information
To initialize the JTAGC module and enable access to registers, the following sequence is required: 1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS. 2. Load the appropriate instruction for the test or action to be performed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 731: Introduction
Features currently not supported: • No support for general call address • Not compliant to ten-bit addressing 20.1.3 Block diagram The block diagram of the I C module is shown in Figure 20-1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 732: Modes Of Operation
This is the bidirectional Serial Clock Line (SCL) of the module, compatible with the I C-Bus specification. 20.3.2.2 This is the bidirectional Serial Data line (SDA) of the module, compatible with the I C-Bus specification. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 733: Memory Map And Register Description
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 734 0–1 select the prescaled shift register (see Table 20-4) 2–4 select the prescaler divider (see Table 20-5) 5–7 select the shift register tap point (see Table 20-6) Table 20-4. I-Bus Multiplier Factor IBC[0:1] RESERVED MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 735 20-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to the change of state of SDA; that is, the SDA hold time. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 736 The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL × [scl2start + (SCL_Tap – 1) × tap2tap] Eqn. 20-3 SCL Hold(stop) = MUL × [scl2stop + (SCL_Tap – 1) × tap2tap] Eqn. 20-4 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 737 SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 738 1276 1282 3072 1532 1538 3840 1916 1922 2560 1276 1282 3072 1532 1538 3584 1788 1794 4096 2044 2050 4608 2300 2306 5120 2556 2562 6144 3068 3074 7680 3836 3842 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 739 3832 3844 5120 2552 2564 6144 3064 3076 7168 1028 3576 3588 8192 1028 4088 4100 9216 1540 4600 4612 10240 1540 5112 5124 12288 2052 6136 6148 15360 2052 7672 7684 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 740 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 741 Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a stop signal is detected, IBB is cleared and the bus enters idle state. 0 Bus is Idle 1 Bus is busy MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 742 Slave modes for the transmission to begin. For instance, if the I C is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 743: Functional Description
Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and stop signal. They are described briefly in the following sections and illustrated in Figure 20-10. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 744: Start Signal
(each data transfer may contain several bytes of data) and brings all slaves out of their idle states. Start condition Stop condition Figure 20-11. Start and stop conditions MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 745: Slave Address Transmission
This is called repeated START. A stop signal is defined as a low-to-high transition of SDA while SCL is at logical “1” (see Figure 20-10). The master can generate a stop even if the slave has generated an acknowledge, at which point the slave must release the bus. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 746: Repeated Start Signal
The first device to complete its high period pulls the SCL line low again. Start Counting High Period WAIT SCL1 SCL2 Internal Counter Reset Figure 20-12. I C Bus Clock Synchronization MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 747: Handshaking
C Control Register. It must be cleared by writing 1 to the IBIF bit in the interrupt service routine. The Bus Going Idle interrupt needs to be additionally enabled by the BIIE bit in the IBIC register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 748: Initialization/Application Information
The TCF bit will be cleared to indicate data transfer in progress by reading the IBDR data register in receive mode or writing the IBDR in transmit mode. The TCF bit should not be used as a data transfer MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 749: Generation Of Stop
(rx_count ==1)// 2nd last byte to be read ? bit 3, IBCR = 1// disable ACK if (rx_count == 0)// last byte to be read ? bit 1, IBCR = 0// generate stop signal else MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 750: Generation Of Repeated Start
CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 751 Rx Mode Mode Read Data Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 20-13. Flow-Chart of Typical I C Interrupt Routine MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 752: Dma Application Information
DMA controller, depending on the setting of the DMAEN bit. All error conditions will trigger an interrupt and require CPU intervention. The address match condition will not occur in DMA mode as the I C should never be configured for slave operation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 753: Introduction
— Ability to modify the ISR or task priority; modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. • Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 754 Display Control Unit (DCU) Stepper Motor Driver (SMD0) Stepper Stall Detect 0 (SSD0) Stepper Stall Detect 1 (SSD1) Stepper Stall Detect 2 (SSD2) Stepper Stall Detect3 (SSD3) Stepper Stall Detect 4 (SSD4) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 755: Block Diagram
The total number of interrupt sources is 122, which includes 16 reserved sources and 8 software sources. Figure 21-1. INTC block diagram 21.4 Modes of operation 21.4.1 Normal mode In normal mode, the INTC has two handshaking modes with the processor: software vector mode and hardware vector mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 756: Software Vector Mode
In this case, PRI in the associated INTC_CPR is updated with the new priority, and the associated LIFO is neither pushed or popped. 21.4.1.3 Debug mode The INTC operation in debug mode is identical to its operation in normal mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 757: Stop Mode
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination of accessing the four bytes of a register with a single access is supported, provided that the access does not MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 758: Intc Module Configuration Register (Intc_Mcr)
Section 21.4, Modes of operation, for the details of the handshaking with the processor in each mode. 0 Software vector mode. 1 Hardware vector mode. 21.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 759 Table 21-5. PRI Values Meaning 1111 Priority 15—highest priority 1110 Priority 14 1101 Priority 13 1100 Priority 12 1011 Priority 11 1010 Priority 10 1001 Priority 9 1000 Priority 8 0111 Priority 7 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 760: Intc Interrupt Acknowledge Register (Intc_Iackr)
INTVEC is updated, whether the INTC is in software or hardware vector mode. INTVEC Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28. VTBA is then shortened by one bit to bits 0–19. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 761: Intc End-Of-Interrupt Register (Intc_Eoir)
Reading the INTC_EOIR has no effect on the LIFO. 21.5.2.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) Offset: 0x0020 Access: User read/write CLR0 CLR1 SET0 SET1 Reset CLR2 CLR3 SET2 SET3 Reset Figure 21-6. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3]) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 762 CLRx is the flag bit. Writing a 1 to CLRx clears it. Writing a 0 to CLRx has no effect. If a 1 is written simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was asserted before the write. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 763 Section 21.6, Functional 20–23, 28–31 description. PRI[0:3]– PRI204:206 Table 21-9. INTC Priority Select Register Address Offsets INTC_PSRx_x Offset Address INTC_PSRx_x Offset Address INTC_PSR0_3 0x0040 INTC_PSR104_107 0x00A8 INTC_PSR4_7 0x0044 INTC_PSR108_111 0x00AC INTC_PSR8_11 0x0048 INTC_PSR112_115 0x00B0 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 764: Functional Description
INTC_PSR92_95 0x009C INTC_PSR196_199 0x0104 INTC_PSR96_99 0x00A0 INTC_PSR200_203 0x0108 INTC_PSR100_103 0x00A4 INTC_PSR204_207 0x010C 21.6 Functional description The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 765 Core (INTC software vector mode) 0x0050 Alignment Core 0x0060 Program Core 0x0070 Reserved Core 0x0080 System call Core 0x0090 Unused Core 0x00F0 Debug Core 0x0100 1792 Unused Core Section B (On-Platform Peripherals) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 766 0x0838 Channel 3 DMA2x 0x083C Channel 4 DMA2x 0x0840 Channel 5 DMA2x 0x0844 Channel 6 DMA2x 0x0848 Channel 7 DMA2x 0x084C Channel 8 DMA2x 0x0850 Channel 9 DMA2x 0x0854 Channel 10 DMA2x MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 767 Real Time Counter (RTC/API) 0x089C Real Time Counter (RTC/API) 0x08A0 Reserved 0x08A4 SIU External IRQ_0 System Integration Unit Lite (SIUL) 0x08A8 SIU External IRQ_1 System Integration Unit Lite (SIUL) 0x08AC Reserved 0x08B0 Reserved 0x08B4 Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 768 0x08FC ADC_ER Analog to Digital Converter 0 (ADC0) 0x0900 ADC_WD Analog to Digital Converter 0 (ADC0) 0x0904 FLEXCAN_ESR[ERR_INT] FlexCAN 0 (CAN0) 0x0908 FLEXCAN_ESR_BOFF | FlexCAN 0 (CAN0) FLEXCAN_Transmit_Warning | FLEXCAN_Receive_Warning 0x090C Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 769 FlexCAN 1 (CAN1) 0x0958 FLEXCAN_ESR_BOFF | FlexCAN 1 (CAN1) FLEXCAN_Transmit_Warning | FLEXCAN_Receive_Warning 0x095C Reserved 0x0960 FLEXCAN_BUF_00_03 FlexCAN 1 (CAN1) 0x0964 FLEXCAN_BUF_04_07 FlexCAN 1 (CAN1) 0x0968 FLEXCAN_BUF_08_11 FlexCAN 1 (CAN1) 0x096C FLEXCAN_BUF_12_15 FlexCAN 1 (CAN1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 770 0x0998 Reserved 0x099C Reserved 0x09A0 Reserved 0x09A4 Reserved 0x09A8 Reserved 0x09AC Reserved 0x09B0 Reserved 0x09B4 Reserved 0x09B8 Reserved 0x09BC Reserved 0x09C0 Reserved 0x09C4 Reserved 0x09C8 Reserved 0x09CC Reserved 0x09D0 Reserved 0x09D4 Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 771 0x0A04 Reserved 0x0A08 Reserved 0x0A0C Reserved 0x0A10 Reserved 0x0A14 Reserved 0x0A18 Reserved 0x0A1C Reserved 0x0A20 Reserved 0x0A24 Reserved 0x0A28 Reserved 0x0A2C Reserved 0x0A30 Reserved 0x0A34 EMIOS_GFR[F8,F9] Enhanced Modular I/O Subsystem 0 (eMIOS0) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 772 0x0A74 EMIOS_GFR[F16,F17] Enhanced Modular I/O Subsystem 1 (eMIOS1) 0x0A78 EMIOS_GFR[F18,F19] Enhanced Modular I/O Subsystem 1 (eMIOS1) 0x0A7C EMIOS_GFR[F20,F21] Enhanced Modular I/O Subsystem 1 (eMIOS1) 0x0A80 EMIOS_GFR[F22,F23] Enhanced Modular I/O Subsystem 1 (eMIOS1) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 773 0x0AC4 Reserved 0x0AC8 Reserved 0x0ACC Reserved 0x0AD0 Reserved 0x0AD4 Reserved 0x0AD8 Reserved 0x0ADC SDCI Sound Generation Logic (SGL) 0x0AE0 VS_BLANK, LS_BF_VS, VSYNC Display Control Unit (DCU0) 0x0AE4 UNDRUN Display Control Unit (DCU0) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 774: Interrupt Request Sources
QuadSPI 0 0x0B38 IPAEF, IPIEF, ICEF QuadSPI 0 21.6.1 Interrupt Request Sources The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt requests can assert on any clock cycle. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 775: Peripheral Interrupt Requests
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt requests assigned to that processor, both peripheral and software configurable. The output of the priority arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 776: Last-In First-Out (Lifo)
0s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory-mapped. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 777: Handshaking With Processor
This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 778: Hardware Vector Mode Handshaking
The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 21.6.3.1.2, End of interrupt exception handler. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 779: Initialization/Application Information
PRI in INTC_CPR to zero enable processor recognition of interrupts 21.7.2 Interrupt Exception Handler These example interrupt exception handlers use Power Architecture assembly code. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 780: Software Vector Mode
This example assumes that each interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 781: Isr, Rtos, And Task Hierarchy
Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 782: Order Of Execution
ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute. ISR308 completes. Interrupt exception handler writes to INTC_EOIR. ISR108 completes. Interrupt exception handler writes to INTC_EOIR. RTOS continues execution. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 783: Priority Ceiling Protocol
(DMS). In RMS, the ISRs which have higher request rates have higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 784: Software Configurable Interrupt Requests
ISR completes. The lower priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the completion of the lower priority ISR. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 785: Scheduling An Isr On Another Processor
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 786: Proper Setting Of Interrupt Request Priority
When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 787: Information Specific To This Device
LCDCR[LCDRCS] = 1 • LCDCR[LCDOCS] = 0 or 1 — If this field is 0, the LCD driver operates from SIRC. — If this field is 1, the LCD driver operates from SXOSC. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 788: Introduction
Backplane drivers – consists of m backplane drivers. • Voltage generator – Based on reference voltage, i.e. applied to VLCD, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 789: Features
Selectable LCD frame frequency interrupt event • On-chip generation of four different output voltage levels • Two contrast adjustment options: — Using VLCD voltage (if available at pin) — Using contrast adjustment phases MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 790: Modes Of Operation
VLCD Positive reference supply voltage for the LCD waveform generation. VDDX Positive supply voltage for the LCD waveform generation. VSSX Ground supply voltage for the LCD waveform generation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 791: Memory Map And Register Definition
End of implemented RAM for 36 FPs End of implemented RAM for 40 FPs End of implemented RAM for 44 FPs End of implemented RAM for 48 FPs End of implemented RAM for 52 FPs MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 792: Register Descriptions
1 LCD Driver System is enabled. All FP[n-1:0] pins with FP[n-1]EN set, will output an LCD driver waveform. The BP[m-1:0] pins will output an LCD Driver waveform based on the settings of DUTY. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 793 The BST bit sets the multiplier for the output current boost. If the BSTEN bit is set, the output current is boosted during transitions in the following way: 0 8 times boosting. 1 16 times boosting. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 794 0 No additional backplanes will be mapped on frontplanes. 1 Additional backplanes will be mapped on frontplanes. 29:31 LCDBPS: Backplane Shifting Using these bits, backplanes will be swapped with frontplanes as shown in Table 22-28. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 795: Lcd Prescaler Control Register (Lcdpcr)
LCD Clock Prescaler bits and the divider value please refer Table 22-27. LCD Clock Prescaler bits should be changed only when LCD Driver is disabled, LCDEN is not set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 796: Lcd Contrast Control Register (Lcdccr)
LCC. LCD Contrast Control. The Contrast Control bits determine the width of the contrast phase. 0x000 Contrast Phase has no duration what results in highest contrast. 0x7FF Contrast Phase lasts the whole duty cycle. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 797: Lcd Frontplane Enable Register 0 (Fpenr0)
The FP[31:0]EN bits enable the frontplane driver outputs. If LCDEN = 0, these bits have no effect on the state of the I/O pins. It is recommended to set FP[31:0]EN bits before LCDEN is set. 0 Frontplane driver output disabled on FP[31:0]. 1 Frontplane driver output enabled on FP[31:0]. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 798: Lcd Frontplane Enable Register 1 (Fpenr1)
I/O pins. It is recommended to set FP[63:32]EN bits before LCDEN is set. 0 Frontplane driver output disabled on FP[63:32]. 1 Frontplane driver output enabled on FP[63:32]. Note: The implemented FP[n-1]EN bits depend on the number of implemented frontplanes. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 799: Lcdram (Location 0)
Table 22-11. LCDRAM (Location 0) field descriptions Field Description 0:31 FP[0:3]BP[5:0]. LCD segment ON. The FP[0:3]BP[5:0] bit displays (turns on) the LCD segment connected between FP[0:3] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 800: Lcdram (Location 1)
Table 22-12. LCDRAM (Location 1) field descriptions Field Description 0:31 FP[4:7]BP[5:0]. LCD segment ON. The FP[4:7]BP[5:0] bit displays (turns on) the LCD segment connected between FP[4:7] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 801: Lcdram (Location 2)
Table 22-13. LCDRAM (Location 2) field descriptions Field Description 0:31 FP[8:11]BP[5:0]. LCD segment ON. The FP[8:11]BP[5:0] bit displays (turns on) the LCD segment connected between FP[8:11] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 802: Lcdram (Location 3)
Table 22-14. LCDRAM (Location 3) field descriptions Field Description 0:31 FP[12:15]BP[5:0]. LCD segment ON. The FP[12:15]BP[5:0] bit displays (turns on) the LCD segment connected between FP[12:15] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 803: Lcdram (Location 4)
Table 22-15. LCDRAM (Location 4) field descriptions Field Description 0:31 FP[16:19]BP[5:0]. LCD segment ON. The FP[16:19]BP[5:0] bit displays (turns on) the LCD segment connected between FP[16:19] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 804: Lcdram (Location 5)
Table 22-16. LCDRAM (Location 5) field descriptions Field Description 0:31 FP[20:23]BP[5:0]. LCD segment ON. The FP[20:23]BP[5:0] bit displays (turns on) the LCD segment connected between FP[20:23] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 805: Lcdram (Location 6)
Table 22-17. LCDRAM (Location 6) field descriptions Field Description 0:31 FP[24:27]BP[5:0]. LCD segment ON. The FP[24:27]BP[5:0] bit displays (turns on) the LCD segment connected between FP[24:27] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 806: Lcdram (Location 7)
Table 22-18. LCDRAM (Location 7) field descriptions Field Description 0:31 FP[28:31]BP[5:0]. LCD segment ON. The FP[28:31]BP[5:0] bit displays (turns on) the LCD segment connected between FP[28:31] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 807: Lcdram (Location 8)
Table 22-19. LCDRAM (Location 8) field descriptions Field Description 0:31 FP[32:35]BP[5:0]. LCD segment ON. The FP[32:35]BP[5:0] bit displays (turns on) the LCD segment connected between FP[32:35] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 808: Lcdram (Location 9)
Table 22-20. LCDRAM (Location 9) field descriptions Field Description 0:31 FP[36:39]BP[5:0]. LCD segment ON. The FP[36:39]BP[5:0] bit displays (turns on) the LCD segment connected between FP[36:39] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 809: Lcdram (Location 10)
Table 22-21. LCDRAM (Location 10) field descriptions Field Description 0:31 FP[40:43]BP[5:0]. LCD segment ON. The FP[40:43]BP[5:0] bit displays (turns on) the LCD segment connected between FP[40:43] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 810: Lcdram (Location 11)
Table 22-22. LCDRAM (Location 11) field descriptions Field Description 0:31 FP[44:47]BP[5:0]. LCD segment ON. The FP[44:47]BP[5:0] bit displays (turns on) the LCD segment connected between FP[44:47] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 811: Lcdram (Location 12)
Table 22-23. LCDRAM (Location 12) field descriptions Field Description 0:31 FP[48:51]BP[5:0]. LCD segment ON. The FP[48:51]BP[5:0] bit displays (turns on) the LCD segment connected between FP[48:51] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 812: Lcdram (Location 13)
Table 22-24. LCDRAM (Location 13) field descriptions Field Description 0:31 FP[52:55]BP[5:0]. LCD segment ON. The FP[52:55]BP[5:0] bit displays (turns on) the LCD segment connected between FP[52:55] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 813: Lcdram (Location 14)
Table 22-25. LCDRAM (Location 14) field descriptions Field Description 0:31 FP[56:59]BP[5:0]. LCD segment ON. The FP[56:59]BP[5:0] bit displays (turns on) the LCD segment connected between FP[56:59] and BP[5:0]. 0 LCD segment OFF 1 LCD segment ON MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 814: Lcdram (Location 15)
All frontplane enable bits, FP[n-1:0]EN are cleared and the ON/OFF control for the display, the LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high impedance state. The pin state during reset is defined by the port control module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 815: Lcd Clock And Frame Frequency
Example: Clock = 16 MHz, Prescaler = 1010;  Eqn. 22-2 16 10  --------------------- - 33 Hz  NOTE A “Frame” is the full refresh cycle of the display. See Section 22.6, LCD waveform examples, for waveform illustrations. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 816: Contrast Adjustment
1/1 duty and 1/1 bias ratios with the additional contrast adjustment phases 1 Frame 1 Frame FPx (xxx0) FPx (xxx0) FPy (xxx1) FPy (xxx1) = Contrast Adjustment Phase Figure 22-23. Contrast adjustment phases MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 817: Lcd Ram
The swapping of LCDBPS depends on the availability of Frontplane pins FP[n-1:0]. If the number of frontplanes n implemented is not sufficient no remapping will occur. See Table 22-28 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 818: Lcd Bias And Modes Of Operation
No remapping: Frontplanes FP[39:0] and BP[3:0] will stay the same, because condition n>=44 is not fulfilled. 22.5.7 LCD bias and modes of operation The LCD64F6B driver has seven modes of operation: • 1/1 Duty (1 backplane), 1/1 Bias (2 voltage levels) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 819 Table 22-29. In the OFF state the corresponding pins BP[m-1:0]can be used for other functionality. Table 22-29. LCD duty and bias LCDCR Register Backplanes Bias Level Duty DUTY BIAS=0 BIAS=1 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 820: Operation In Power Saving Modes
If LCDRCS is set, the source clock for LCD Driver system (prescaler input) is OSC clock. See device level documentation for detail on OSC clk. Selecting MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 821: Boost At Switching
The user can select any combination of PWR, BST, BSTEN, BSTAO to what fit his needs best. Figure 22-24 gives an overview what is the impact when taking advance of Boost at switching and Standard drive selection. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 822: Interrupts
The EOF flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LCDINT = 1), EOF causes an interrupt request. The number of frames (NOF) bits determine how many frames are count until EOF flag is set. The possible number of frames are: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 823: Lcd Waveform Examples
- Only BP0 is used, a maximum of 64 segments are displayed. 1 Frame VLCD VSSX VLCD FPx (xxx0) VSSX VLCD FPy (xxx1) VSSX +VLCD BP0-FPx (OFF) -VLCD +VLCD BP0-FPy (ON) -VLCD Figure 22-25. 1/1 Duty and 1/1 Bias MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 824: Duty Multiplexed With 1/2 Bias Mode
Bias = 1/3:BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - Only BP0 and BP1 are used, a maximum of 128 segments are displayed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 825: Duty Multiplexed With 1/3 Bias Mode
-VLCD 2/3 -VLCD Figure 22-27. 1/2 Duty and 1/3 Bias 22.6.4 1/3 Duty multiplexed with 1/3 Bias mode Duty = 1/3:DUTY = 010 Bias = 1/3:BIAS = 0 or BIAS = 1 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 826: Duty Multiplexed With 1/3 Bias Mode
Bias = 1/3:BIAS = 0 or BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - BP4 and BP5 are not used, a maximum of 256 segments are displayed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 827: Duty Multiplexed With 1/3 Bias
Bias = 1/3:BIAS = 0 or BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - BP5 is not used, a maximum of 320 segments are displayed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 828: Duty Multiplexed With 1/3 Bias Mode
Bias = 1/3:BIAS = 0 or BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - All backplanes are used, a maximum of 384 segments are displayed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 829: Initialization Information
-VLCD1/3 -VLCD 2/3 -VLCD Figure 22-31. 1/6 Duty and 1/3 Bias 22.7 Initialization information This is a step-wise example instruction for initializing. The initial values of all registers are the reset values. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 830 Set LCDCR Set LCDPCR Set FPENR0/1 Init LCDRAM LCDEN = 1 Access RAM and LCDCCR Figure 22-32. Example initialization diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 831: Introduction
16 identifier filters for autonomous message handling in Slave mode 23.2.2 UART mode features • Full duplex communication • 8- or 9-bit with parity • 4-byte buffer for reception, 4-byte buffer for transmission • 8-bit counter for timeout management MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 832: Features Common To Lin And Uart
Configure LIN parameters (for example, baud rate or mode) • Request transmissions • Handle receptions • Manage interrupts • Configure LIN error and timeout detection • Process diagnostic information The message buffer stores transmitted or received LIN frames. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 833: Fractional Baud Rate Generation
Figure 23-2. LINFlex block diagram 23.4 Fractional baud rate generation The baud rates for the receiver and transmitter are both set to the same value as programmed in the Mantissa (LINIBRR) and Fraction (LINFBRR) registers. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 834 Desired) the baud rate register Desired) Actual Actual register baud rate baud rate / Desired / Desired LINIBRR LINFBRR baud rate LINIBRR LINFBRR baud rate 10417 10416.7 –0.003 10416.7 –0.003 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 835: Operating Modes
LIN Slave mode with filter activation is selected, initializes the identifier list. 23.5.2 Normal mode Once initilization is complete, software clears the INIT bit in the LINCR1 to put the hardware into Normal mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 836: Low-Power Mode (Sleep)
“Hot Self-test”, meaning the LINFlex can be tested as in Loopback mode but without affecting a running LIN system connected to the LINTX and LINRX pins. In this mode, the LINRX pin is disconnected from the LINFlex and the LINTX pin is held recessive. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 837: Memory Map And Registers Description
854 0x0030 LIN control register 2 (LINCR2) See note on page 854 0x0034 Buffer identifier register (BIDR) 0x0000_0000 on page 856 0x0038 Buffer data register LSB (BDRL) 0x0000_0000 on page 857 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 838: Register Description
Register description This section describes in address order all the LINFlex registers. Each description includes a standard register diagram. Details of register bit and field function follow the register diagrams, in bit order. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 839: Lin Control Register 1 (Lincr1)
0 Checksum field is sent after the required number of data bytes is sent. 1 No checksum field is sent. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 840 1 Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming message is discarded. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 841 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 842: Lin Interrupt Enable Register (Linier)
Header Error Interrupt Enable 0 No interrupt on Break Delimiter error, Synch Field error, Identifier field error. 1 Interrupt generated on Break Delimiter error, Synch Field error, Identifier field error. 21:22 Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 843 Header Received Interrupt Enable 0 No interrupt when a valid LIN header has been received. 1 Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR is set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 844: Lin Status Register (Linsr)
Address: Base + 0x0008 Access: User read/write Reset LINS[0:3] RBSY RPS WUF DBFF DBEF DRF DTF HRF W w1c Reset Figure 23-9. LIN status register (LINSR) Table 23-8. LINSR field descriptions Field Description 0:15 Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 845 1 Buffer ready to be read by software. This bit must be cleared by software after reading data received in the buffer. This bit is cleared by hardware in Initialization mode. Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 846 Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say: • All filters are inactive and BF bit in LINCR1 is set • No match in any filter and BF bit in LINCR1 is set • TX filter match MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 847: Lin Error Status Register (Linesr)
This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field). BDEF Break Delimiter Error Flag This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one bit time). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 848: Uart Mode Control Register (Uartcr)
UART bit is set. TDFL[0:1] = Transmit buffer size – 1. 00 Transmit buffer size = 1. 01 Transmit buffer size = 2. 10 Transmit buffer size = 3. 11 Transmit buffer size = 4. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 849 This bit can be programmed in Initialization mode only when the UART bit is set. UART UART mode enable 0 LIN mode. 1 UART mode. This bit can be programmed in Initialization mode only. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 850: Uart Mode Status Register (Uartsr)
This bit indicates if there is a parity error in the corresponding received byte (Rx0). See Section 23.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs. 0 No parity error. 1 Parity error. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 851 An interrupt is generated if DTIE bit in LINIER is set. Noise Flag This bit is set by hardware when noise is detected on a received character. This bit is cleared by software. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 852: Lin Timeout Control Status Register (Lintcsr)
TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in LIN timeout mode, then hardware takes control of TOCE bit. CNT[0:7] Counter Value 24:31 These bits indicate the LIN Timeout counter value. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 853: Lin Output Compare Register (Linocr)
LIN timeout control register (LINTOCR) Address: Base + 0x0020 Access: User read/write Reset RTO[0:3] HTO[0:6] Reset *: These bits reset to 10 for LINFlex_0 and 01 for LINFlex_1. Figure 23-15. LIN timeout control register (LINTOCR) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 854: Lin Fractional Baud Rate Register (Linfbrr)
The 4 fraction bits define the value of the fraction of the LINFlex divider (LFDIV). Fraction (LFDIV) = Decimal value of DIV_F [0:3] / 16. This register can be written in Initialization mode only. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 855: Lin Integer Baud Rate Register (Linibrr)
These 12 bits define the LINFlex divider (LFDIV) mantissa value (see Table 23-17). This register can be written in Initialization mode only. Table 23-17. Integer baud rate selection DIV_M[0:12] Mantissa 0x0000 LIN clock disabled 0x0001 0x1FFE 8190 ox1FFF 8191 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 856: Lin Checksum Field Register (Lincfr)
Address: Base + 0x0030 Access: User read/write Reset IOBE IOPE WURQ DDRQ DTRQ ABRQ HTRQ Reset *: This bit resets to 1 for LINFlex_0 and 0 for LINFlex_1. Figure 23-19. LIN control register 2 (LINCR2) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 857 Set by software to request the transmission of the LIN header. Cleared by hardware when the request has been completed or aborted. This bit has no effect in UART mode. 24:31 Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 858: Buffer Identifier Register (Bidr)
If the slave has to manage frames with 2 types of checksum, filters must be configured. 24:25 Reserved ID[0:5] Identifier 26:31 Identifier part of the identifier field without the identifier parity. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 859: Buffer Data Register Lsb (Bdrl)
Data byte 0 of the data field. 23.7.2.16 Buffer data register MSB (BDRM) Address: Base + 0x003C Access: User read/write DATA7[0:7] DATA6[0:7] Reset DATA5[0:7] DATA4[0:7] Reset Figure 23-22. Buffer data register MSB (BDRM) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 860: Identifier Filter Enable Register (Ifer)
(Refer to Table 23-24.) These bits can be set/cleared in Initialization mode only. Table 23-24. IFER[FACT] configuration Value Result FACT[0] Filters 0 and 1 are deactivated. Filters 0 and 1 are activated. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 861: Identifier Filter Match Index (Ifmi)
This register is not implemented on LINFlex_1. Address: Base + 0x0044 Access: User read-only Reset IFMI[0:4] Reset Figure 23-24. Identifier filter match index (IFMI) Table 23-25. IFMI field descriptions Field Description 0:26 Reserved MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 862: Identifier Filter Mode Register (Ifmr)
Filters 4 and 5 are in mask mode (filter 5 is the mask for the filter 4). IFM[3] Filters 6 and 7 are in identifier list mode. Filters 6 and 7 are in mask mode (filter 7 is the mask for the filter 6). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 863: Identifier Filter Control Register (Ifcr2N)
2.0 and higher. 1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and earlier. 24:25 Reserved ID[0:5] Identifier 26:31 Identifier part of the identifier field without the identifier parity. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 864: Identifier Filter Control Register (Ifcr2N + 1)
2.0 and higher. 1 Classic Checksum covering Data field only. This is compatible with LIN specification 1.3 and earlier. 24:25 Reserved ID[0:5] Identifier 26:31 Identifier part of the identifier field without the identifier parity MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 865: Register Map And Reset Values
23.7.3 Register map and reset values Table 23-30. Register map and reset values Address Register offset name LINCR1 Reset value LASE AWUM MBL0 MBL1 MBL2 MBL3 SLFM LBKM SBDT RBLM SLEEP INIT LINIER Reset value SZIE OCIE BEIE CEIE HEIE FEIE BOIE LSIE...
Page 866 Table 23-30. Register map and reset values (continued) Address Register offset name LINTCSR Reset value LTOM TOCE CNT0 CNT1 CNT2 CNT3 CNT4 CNT5 CNT6 CNT7 LINOCR Reset value OC20 OC21 OC22 OC23 OC24 OC25 OC26 OC27 OC10 OC11 OC12 OC13 OC14 OC15 OC16...
Page 867 Table 23-30. Register map and reset values (continued) Address Register offset name BIDR Reset value DFL0 DFL1 DFL2 DFL3 DFL4 DFL5 BDRL Reset value DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA10 DATA11 DATA12...
Page 868 Table 23-30. Register map and reset values (continued) Address Register offset name IFCR2n Reset value DFL0 DFL1 DFL2 IFCR2n + 1 Reset value DFL0 DFL1 DFL2...
Page 869: Uart Mode
Figure 23-29. UART mode 9-bit data frame 23.8.1.1 Buffer in UART mode The 8-byte buffer is divided into two parts: one for receiver and one for transmitter as shown in Table 23-31. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 870: Uart Transmitter
• If the buffer lock function is enabled (RBLM bit in LINCR1 set) the most recent message is discarded and the previous message is available in the buffer. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 871: Clock Gating
If the response has been sent successfully, the DTF bit in the LINSR is set. In case of error, the DTF flag is not set and the corresponding error flag is set in the LINESR (refer to Section 23.8.2.1.6, Error handling). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 872 In case of Bit Error detection during transmission, LINFlex stops the transmission of the frame after the corrupted bit. LINFlex returns to idle state and an interrupt is generated if the BEIE bit in the LINIER is set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 873: Slave Mode
Using a filter avoids the software having to configure the direction, the data field length and the checksum type in the BDIR. The software fills the BDAR and triggers the data transmission by setting the DTRQ bit in LINCR2. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 874 Bit error: During transmission, the value read back from the bus differs from the transmitted value. • Framing error: A dominant state has been sampled on the stop bit of the currently received character (synch field, identifier field or data field). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 875: Slave Mode With Identifier Filtering
— — or send a response. If the message does not target the node, it must be discarded without software intervention. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 876 ID (or the mask), the direction (TX or RX), the data field length, and the checksum type. If no filter is active, an RX interrupt is generated on any received identifier event. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 877: Slave Mode With Automatic Resynchronization
Slave mode with automatic resynchronization Automatic resynchronization must be enabled in Slave mode if f tolerance is greater than periph_set_1_clk 1.5%. This feature compensates a f deviation up to 14%, as specified in LIN standard. periph_set_1_clk MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 878 The first check is based on a measurement between the first falling edge and the last falling edge of the Synch Field: • If D1 > 14.84%, LHE is set. • If D1 < 14.06%, LHE is not set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 879: Clock Gating
• OC2[0:7] is updated with the value of OC = CNT[0:7] + 28 + RTO[0:6] × 9 (frame Frame Frame timeout value for an 8-byte frame), • the TOCE bit is set. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 880 On the checksum reception or in case of error in the header or data field, the TOCE bit is reset. Frame Header Response Response space [0:7] Header Response Break [0:7] Frame Figure 23-33. Header and response timeout MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 881: Output Compare Mode
In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector is RXI or TXI depending on the value of identifier received. For debug and validation purposes MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 882 LIN Controller (LINFlex) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 883: Overview
(RGDn) as well as the combinational logic blocks to determine the region hit and the access protection error. For information on the details of the access evaluation macro, see Section 24.3.1, Access evaluation macro. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 884 > > rgd(n-1) start r,w,x hit_b error ips_rdata > > IPS Bus ahb_error_ap error_detail (EDRn) error_address (EARn) Figure 24-1. AHB_MPU block diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 885: Features
AHB system bus port(s). Power dissipation is minimized when the MPU’s global enable/disable bit is cleared (MPU_CESR[VLD] = 0). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 886: External Signal Description
MPU Error Detail Register, Slave Port 3 R-only on page 887 0x0030– Reserved 0x03FF 0x0400 MPU_RGD0 MPU Region Descriptor 0 on page 888 0x0410 MPU_RGD1 MPU Region Descriptor 1 on page 888 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 887: Register Description
The following sections detail the individual registers within the MPU’s programming model. 24.2.2.1 MPU Control/Error Status Register (MPU_CESR) The MPU_CESR provides one byte of error status plus three bytes of configuration information. A global MPU enable/disable bit is also included in this register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 888: Mpu Error Address Register, Slave Port N (Mpu_Earn)
MPU_EDRn register contain the most recent access error; there are no hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence of each protection violation. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 889: Mpu Error Detail Register, Slave Port N (Mpu_Edrn)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EACD EPID EATTR Reset - Figure 24-4. MPU Error Detail Register, Slave Port n (MPU_EDRn) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 890: Mpu Region Descriptor N (Mpu_Rgdn)
The first word of the MPU region descriptor defines the 0-modulo-32 byte start address of the memory region. Writes to this word clear the region descriptor’s valid bit (see Section 24.2.2.4.4, MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) for more information). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 891 For the processor privilege rights, there are three flags associated with this function: {read, write, execute}. In this context, these flags follow the traditional definition: • Read (r) permission refers to the ability to access the referenced memory address using an operand (data) fetch. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 892 Bus master 4 write enable. If set, this flag allows bus master 4 to perform write operations. If cleared, M4WE any attempted write by bus master 4 terminates with an access error and the write is not performed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 893 Bus master 0 process identifier enable. If set, this flag specifies that the process identifier and mask M0PE (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 894 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V PIDMASK Reset - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-8. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 895: 24.2.2.5 Mpu Region Descriptor Alternate Access Control N (Mpu_Rgdaacn
Bus master 6 read enable. If set, this flag allows bus master 6 to perform read operations. If cleared, any M6RE attempted read by bus master 6 terminates with an access error and the read is not performed. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 896 Bus master 1 process identifier enable. If set, this flag specifies that the process identifier and mask M1PE (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 897: Functional Description
AHB system bus address phase signals (AHB_ap) and the contents of a region descriptor (RGDn) and performs two major functions: region hit determination (hit_b) and detection of an access protection violation (error). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 898: Access Evaluation—Hit Determination
The protection violation logic then evaluates the access against the effective permissions using the specification shown in Table 24-10. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 899: Putting It All Together And Ahb Error Terminations
If instead the access is allowed, then the MPU simply passes all “original” AHB signals to the slave device. In this case, from functionality point of view, the MPU is fully transparent. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 900: Initialization Information
In any event, the processor can retrieve the captured error address and detail information simply be reading the MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is signaled by MPU_CESR[SPERR]. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 901 Memory Protection Unit (MPU) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 902 Memory Protection Unit (MPU) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 903: Introduction
The MC_ME controls the device mode and mode transition sequences in all functional states. It also contains configuration, control and status registers accessible for the application. Figure 25-1 depicts the MC_ME block diagram. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 904 Mode Entry Module (MC_ME) MC_ME VREG MC_PCU Flashes Registers Platform Interface MC_RGM FIRC MC_CGM FXOSC FMPLL0 FMPLL1 core Device Mode State Machine peripherals WKPU Figure 25-1. MC_ME block diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 905: Features
It forces the system into a software request assertion, DRUN via pre-defined safe configuration from which the system may try to from DRUN, Test, software recover. and Run0…3 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 906: External Signal Description
The MC_ME contains registers for: • Mode selection and status reporting • Mode configuration • Mode transition interrupts status and mask control • Scalable number of peripheral sub-mode selection and status reporting MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 907: Memory Map
Run Peripheral Configuration 1 word read/write … 0xC3FD_C09C ME_RUN_PC7 Run Peripheral Configuration 7 word read/write 0xC3FD_C0A0 ME_LP_PC0 Low-Power Peripheral word read/write Configuration 0 0xC3FD_C0A4 ME_LP_PC1 Low-Power Peripheral word read/write Configuration 1 … MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 908 0xC3FD_C128 ME_PCTL104 CMU0 Control byte read/write NOTE Any access to unused registers as well as write accesses to read-only registers will: • Not change register content • Cause a transfer error MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 909 Table 25-3. MC_ME memory map Address Name 0xC3FD_C000 ME_GS R S_CURRENT_MODE S_DFLA S_CFLA S_SYSCLK 0xC3FD_C004 ME_MCTL TARGET_MODE 0xC3FD_C008 ME_ME 0xC3FD_C00C ME_IS w1c w1c w1c w1c 0xC3FD_C010 ME_IM 0xC3FD_C014 ME_IMTS w1c w1c w1c w1c w1c MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 910 Mode Entry Module (MC_ME) Table 25-3. MC_ME memory map (continued) Address Name 0xC3FD_C018 ME_DMTS 0xC3FD_C01C Reserved 0xC3FD_C020 ME_RESET_MC DFLAON CFLAON SYSCLK 0xC3FD_C024 ME_TEST_MC DFLAON CFLAON SYSCLK 0xC3FD_C028 ME_SAFE_MC DFLAON CFLAON SYSCLK MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 911 Table 25-3. MC_ME memory map (continued) Address Name 0xC3FD_C02C ME_DRUN_MC DFLAON CFLAON SYSCLK 0xC3FD_C030 ME_RUN0…3_MC … DFLAON CFLAON 0xC3FD_C03C SYSCLK 0xC3FD_C040 ME_HALT_MC DFLAON CFLAON SYSCLK 0xC3FD_C044 Reserved 0xC3FD_C048 ME_STOP_MC DFLAON CFLAON 0xC3FD_C04C … Reserved 0xC3FD_C050 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 912 Mode Entry Module (MC_ME) Table 25-3. MC_ME memory map (continued) Address Name 0xC3FD_C054 ME_STANDBY_MC DFLAON CFLAON SYSCLK 0xC3FD_C058 … Reserved 0xC3FD_C05C 0xC3FD_C060 ME_PS0 0xC3FD_C064 ME_PS1 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 913 Mode Entry Module (MC_ME) Table 25-3. MC_ME memory map (continued) Address Name 0xC3FD_C068 ME_PS2 0xC3FD_C06C ME_PS3 0xC3FD_C070 Reserved 0xC3FD_C074 … Reserved 0xC3FD_C07C 0xC3FD_C080 ME_RUN_PC0…7 … 0xC3FD_C09C 0xC3FD_C0A0 ME_LP_PC0…7 … 0xC3FD_C0BC MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 914: Register Description
0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address 0xC3FD_C083. 25.3.2.1 Global Status Register (ME_GS) Address 0xC3FD_C000 Access: Supervisor read S_CURRENT_MODE S_DFLA S_CFLA Reset S_SYSCLK Reset Figure 25-2. Global Status Register (ME_GS) This register contains global mode status. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 915 1 secondary frequency modulated phase locked loop is providing a stable clock S_FMPLL0 primary frequency modulated phase locked loop status 0 primary frequency modulated phase locked loop is not stable 1 primary frequency modulated phase locked loop is providing a stable clock MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 916: Mode Control Register (Me_Mctl)
This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to ME_<mode>_MC registers must respect this for successful mode requests. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 917: Mode Enable Register (Me_Me)
Read access will always return inverted key. KEY: 0101101011110000 (0x5AF0) INVERTED KEY: 1010010100001111 (0xA50F) 25.3.2.3 Mode Enable Register (ME_ME) Address 0xC3FD_C008 Access: Supervisor read/write Reset Reset Figure 25-4. Mode Enable Register (ME_ME) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 918 1 Safe mode is enabled TEST Test mode enable 0 Test mode is disabled 1 Test mode is enabled RESET Reset mode enable 0 Reset mode is disabled 1 Reset mode is enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 919: Interrupt Status Register (Me_Is)
(S_MTRANS transits from 1 to 0). It is cleared by writing a 1 to this bit. This mode transition interrupt bit will not be set while entering low-power modes Halt, Stop, or Standby. 0 No mode transition complete interrupt occurred 1 Mode transition complete interrupt is pending MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 920: Interrupt Mask Register (Me_Im)
0 Safe mode interrupt is masked 1 Safe mode interrupt is enabled M_MTC Mode transition complete interrupt mask 0 Mode transition complete interrupt is masked 1 Mode transition complete interrupt is enabled MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 921: Invalid Mode Transition Status Register (Me_Imts)
Reset/Safe modes. It is cleared by writing a 1 to this bit. 0 No new mode requested other than Reset/Safe while Safe event is pending 1 New mode requested other than Reset/Safe while Safe event is pending MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 922: Debug Mode Transition Status Register (Me_Dmts)
CORE_DBG Processor is in Debug mode indicator — This bit is set while the processor is in debug mode. 0 The processor is not in debug mode 1 The processor is in debug mode MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 923 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 924: Reset Mode Configuration Register (Me_Reset_Mc)
Address 0xC3FD_C020 Access: Supervisor read/write DFLAON CFLAON Reset SYSCLK Reset Figure 25-9. Invalid Mode Transition Status Register (ME_IMTS) This register configures system behavior during Reset mode. Please refer to Table 25-11 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 925: Test Mode Configuration Register (Me_Test_Mc)
Address 0xC3FD_C028 Access: Supervisor read/write DFLAON CFLAON Reset SYSCLK Reset Figure 25-11. Safe Mode Configuration Register (ME_SAFE_MC) This register configures system behavior during Safe mode. Please refer to Table 25-11 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 926: Drun Mode Configuration Register (Me_Drun_Mc)
This register configures system behavior during DRUN mode. Please refer to Table 25-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. NOTE The values of FXOSCON, FMPLL1ON, CFLAON and DFLAON are retained through Standby mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 927: Run0...3 Mode Configuration Registers (Me_Run0...3_Mc)
Figure 25-14. Halt Mode Configuration Register (ME_HALT_MC) This register configures system behavior during Halt mode. Please refer to Table 25-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 928: Stop Mode Configuration Register (Me_Stop_Mc)
Address 0xC3FD_C054 Access: Supervisor read/write DFLAON CFLAON Reset SYSCLK Reset Figure 25-16. Standby Mode Configuration Register (ME_STANDBY_MC) This register configures system behavior during Standby mode. Please refer to Table 25-11 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 929 1 fast external crystal oscillator (4-16MHz) is switched on FIRCON fast internal RC oscillator (16MHz) control 0 fast internal RC oscillator (16MHz) is switched off 1 fast internal RC oscillator (16MHz) is switched on MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 930: Peripheral Status Register 0 (Me_Ps0)
25.3.2.16 Peripheral Status Register 0 (ME_PS0) Address 0xC3FD_C060 Access: Supervisor read Reset Reset Figure 25-17. Peripheral Status Register 0 (ME_PS0) This register provides the status of the peripherals. Please refer to Table 25-12 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 931: Peripheral Status Register 1 (Me_Ps1)
25.3.2.17 Peripheral Status Register 1 (ME_PS1) Address 0xC3FD_C064 Access: Supervisor read Reset Reset Figure 25-18. Peripheral Status Register 1 (ME_PS1) This register provides the status of the peripherals. Please refer to Table 25-12 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 932: Peripheral Status Register 2 (Me_Ps2)
25.3.2.19 Peripheral Status Register 3 (ME_PS3) Address 0xC3FD_C06C Access: Supervisor read Reset Reset Figure 25-20. Peripheral Status Register 3 (ME_PS3) This register provides the status of the peripherals. Please refer to Table 25-12 for details. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 933: Run Peripheral Configuration Registers (Me_Run_Pc0...7)
RUN0 Peripheral control during Run0 0 Peripheral is frozen with clock gated 1 Peripheral is active DRUN Peripheral control during DRUN 0 Peripheral is frozen with clock gated 1 Peripheral is active MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 934: Low-Power Peripheral Configuration Registers (Me_Lp_Pc0...7)
STOP Peripheral control during Stop 0 Peripheral is frozen with clock gated 1 Peripheral is active HALT Peripheral control during Halt 0 Peripheral is frozen with clock gated 1 Peripheral is active MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 935: Peripheral Control Registers (Me_Pctl0...143)
ME_MCTL register. But in case of special events, mode transition can be automatically managed by hardware. In order to switch from one mode to another, the application should access the ME_MCTL register twice by writing MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 936 ME_GS register matches the configuration programmed in the respective ME_<mode>_MC register. software SYSTEM MODES USER MODES request recoverable hardware RUN0 failure SAFE software HALT request RUN1 RESET DRUN RUN2 STOP RUN3 non-recoverable failure TEST STANDBY Figure 25-24. MC_ME mode diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 937: Mode Details
25.4.2.3 Safe mode The device enters this mode on the following events: • From DRUN, Run0…3, or Test mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0010” MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 938: Test Mode
ME_TEST_MC register. Except for the main voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 939: Run0...3 Modes
As soon as any of the above events occur, a Halt mode transition request is generated. The mode configuration information for this mode is provided by ME_HALT_MC register. This mode is quite configurable, and the ME_HALT_MC register should be programmed according to the system needs. The MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 940: Stop Mode
If the pads’ power sequence driver cell needs to be disabled while entering this mode, the PDO bit of the ME_STOP_MC register should be set. The state of the outputs is kept. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 941: Standby Mode
The process of mode transition follows the following steps in a pre-defined manner depending on the current device mode and the requested target mode. In many cases of mode transition, not all steps need MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 942: Target Mode Request
Run0…3 Halt Stop Standby     FIRC always on always on always on      FXOSC off by default, but also writable     FMPLL0 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 943: Peripheral Clocks Disable
Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive state when the device enters the Safe mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 944: Processor Low-Power Mode Entry
On completion of the Target mode request, if the main voltage regulator needs to be switched on from its off state based on the MVRON bit of the ME_<current mode>_MC and ME_<target mode>_MC MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 945: Flash Modules Switch-On
Switch-On, if the PDO bit of the ME_<target mode>_MC register is cleared, then • All pad outputs are enabled to return to their previous state • The I/O pads power sequence driver is switched on MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 946: Peripheral Clocks Enable
If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is possible only in the Stop and Test modes. In the Standby mode, the clock configuration is fixed, and the system clock is automatically forced to 0. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 947: Power Domain #2 Switch-Off
If the PDO bit of the ME_<target mode>_MC register is 1 then • The outputs of the pads are forced to the high impedance state if the target mode is Safe or Test MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 948: Fmpll0 Switch-Off
S_MVR of the ME_GS register. This step is required only during the entry of low-power modes like Halt and Stop. This step is executed only after completing the following processes: • FMPLL0 Switch-Off • Flash Switch-Off MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 949: Current Mode Update
Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register. The mode transition latency can differ from one mode to another depending on the resources’ availability before the new mode request and the target mode’s requirements. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 950 Memory Clock Disable FLASH Switch-Off Outputs -Off Power Domain Switch-Off Switch-Off STANDBY Clock sources Target Main VREG STANDBY Switch-Off Request Switch-Off S_MTRANS = 0 Current Mode Update Figure 25-25. MC_ME Transition Diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 951: Protection Of Mode Configuration Registers
I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of ME_IM register is 1. 25.4.5.2 Invalid mode transition interrupt The mode transition request is considered invalid under the following conditions: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 952 Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register is set, and an interrupt request is generated if the mask bit M_IMODE is ME_IM register is 1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 953: Safe Mode Transition Interrupt
RUN_CFG and LP_CFG bits. Any further modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers during a debug session will take effect immediately without requiring any new mode request. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 954: Application Example
DONE write ME_MCTL with current or SAFE mode and key write ME_MCTL with current or SAFE mode and inverted key Figure 25-26. MC_ME Application Example Flow Diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 955 Mode Entry Module (MC_ME) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 956 Mode Entry Module (MC_ME) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 957: Introduction
Introduction The Nexus Development Interface (NDI) block provides real-time development support capabilities for the MPC5606S MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility.
Page 958: Features
Figure 26-2. NDI implementation block diagram 26.3 Features The NDI module of the MPC5606S is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional Class 3 and Class 4 features available.The following features are implemented: • Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to...
Page 959: Modes Of Operation
The NDI block indicates to the MCU that it is not using the auxiliary output port. This indication can be used to tristate the output pins or use them for another function. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 960: Operating Mode
Nexus reset Name Function Pull state EVTI Event-in pin — EVTO Event-out pin — MCKO Message clock out pin — MDO[3:0] Message data out pins — MSEO Message start/end out pin — MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 961: Memory Map And Register Description
26-3, allows the part revision number, design center, part identification number, and manufacturer identity code of the device to be determined through the auxiliary output port, and serially through TDO. This register is read-only. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 962: Port Configuration Register (Pcr)
STOP_SYNC bits, but must preserve the original state of the remaining bits in the register. NOTE The mode or clock division must not be modified after MCKO has been enabled. Changing the mode or clock division while MCKO is enabled can produce unpredictable results. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 963 MCKO Enable. This bit enables the MCKO clock to run. When enabled, the frequency of MCKO is determined by the MCKO_DIV field. 0 MCKO clock is driven to zero. 1 MCKO clock is enabled. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 964: Development Control Register 1, 2 (Dc1, Dc2)
Development Control Register 1, 2 (DC1, DC2) The development control registers are used to control the basic development features of the Nexus module. Figure 26-5 shows development control register 1 and Table 26-5 describes the register’s fields. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 965 0 Watchpoint messaging disabled. 1 Watchpoint messaging enabled. 8–23 Reserved. 24–26 Overrun Control. OVC[2:0] 000 Generate overrun messages. 001–010 Reserved. 011 Delay processor for BTM / DTM / OTM overruns. 1XX Reserved. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 966 XXXX1XXX Watchpoint #4 (DAC1 from Nexus1) triggers EVTO. XXXXX1XX Watchpoint #5 (DAC2 from Nexus1) triggers EVTO. XXXXXX1X Watchpoint #6 (DCNT1 from Nexus1) triggers EVTO. XXXXXXX1 Watchpoint #7 (DCNT2 from Nexus1) triggers EVTO. 8–31 Reserved. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 967: Development Status Register (Ds)
00 Normal (run) mode. 01 CPU in halted state. 10 CPU in stopped state. 11 Reserved. CPU Checkstop Status. 0 CPU not in checkstop state. 1 CPU in checkstop state. 7–31 Reserved. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 968: Read/Write Access Control/Status (Rwcs)
000 Primary memory map. 001–111 Reserved. 8–9 Read/Write Access Priority. PR[1:0] 00 Lowest access priority. 01 Reserved (default to lowest priority). 10 Reserved (default to lowest priority). 11 Highest access priority. 10–15 Reserved. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 969: Read/Write Access Address (Rwa)
Figure 26-9. Read/Write Access Address Register (RWA) 26.6.2.7 Read/Write Access Data (RWD) The read/write access data register provides the data to/from system bus memory-mapped locations when initiating a read or a write access. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 970: Watchpoint Trigger Register (Wt)
These watchpoints can control program and/or data trace enable and disable. The WT bits can be used to produce an address-related window for triggering trace messages. Nexus 0x000B Access: User read/write Reg: Reset Reset Figure 26-11. Watchpoint Trigger Register (WT) Table 26-10 details the watchpoint trigger register fields. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 971: Functional Description
(written by the debugger), which results in the deassertion of the lp_sync_out input. In anticipation of the low-power mode exit notification, the TDO pad is driven to 1. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 972: Enabling Nexus Clients For Tap Access
Opcode for e200z0 OnCE Nexus ENABLE instruction 0x7C (10-bits) BYPASS Opcode for the e200z0 OnCE BYPASS instruction 0x7F (10-bits) Refer to the e200z0 reference manual for a complete list of available OnCE instructions. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 973: Configuring The Ndi For Nexus Messaging
The default value selected if a reserved encoding is programmed is SYS_CLK2. NOTE On MPC5606S, the pad type used for the Nexus2+ signals will not support the default SYSCLK2 and SYSCLKsetting, so the user must change the MCKO frequency to be not faster than SYSCLK4.
Page 974: Nexus Messaging
NPC drives EVTO for two system clock periods. EVTO sharing is active as long as the NDI is not in reset. 26.7.7 Debug mode control On MPC5606S, program breaks can be requested either by using the EVTI pin as a break request, or when a Nexus event is triggered. 26.7.7.1 EVTI generated break request To use the EVTI pin as a debug request, the EIC field in the e200z0 Nexus2+ Development Control Register 1 (DC1[4:3]) must be set to configure the EVTI input as a debug request.
Page 975: Introduction
Bus Clock Figure 27-1. PIT block diagram 27.1.2 Features The main features of this block are: • Timers can generate DMA trigger pulses • Timers can generate interrupts • All interrupts are maskable MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 976: Signal Description
Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. NOTE Reserved registers will read as 0, writes will have no effect. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 977: Register Descriptions
0 Timers continue to run in debug mode. 1 Timers are stopped in debug mode. 27.3.2.2 Timer Load Value (LDVAL) register The Timer Load Value (LDVAL) register selects the timeout period for the timer interrupts. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 978: Current Timer Value (Cval) Register
The Current Timer Value (CVAL) register indicates the current timer position. Offset: Channel_base + 0x04 Access: Read-only R TVL Reset R TVL TVL9 TVL8 TVL7 TVL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0 Reset Figure 27-4. Current Timer Value (CVAL) register MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 979: Timer Control (Tctrl) Register
To avoid this, the associated TIF flag must be cleared first. Timer Enable Bit. 0 Timer will be disabled 1 Timer will be active 27.3.2.5 Timer Flag (TFLG) register The Timer Flag (TFLG) register holds the PIT interrupt flags. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 980: Functional Description
It is also possible to change the counter period without restarting the timer by writing the LDVAL register with the new load value. This value will then be loaded after the next trigger event (see Figure 27-9). MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 981: Debug Mode
0 by writing a 1 to that TIF bit. 27.5 Initialization and application information 27.5.1 Example configuration In the example configuration: MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 982 PIT_TCTRL1 = TIE; // enable Timer 1 interrupts PIT_TCTRL1 |= TEN; // start timer 1 // Timer 3 PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cycles PIT_TCTRL3 = TEN; // start timer 3 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 983: Introduction
28.1.1 Overview MPC5606S devices have one PBRIDGE, which provides an interface between the system bus and all lower bandwidth peripherals. Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface.
Page 984: Read Cycles
16-KB boundaries. Each slave peripheral is allocated one 16-KB block of the memory map, and is activated by one of the module enables from the PBRIDGE. The PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor or user mode. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 985: Introduction
#0 are in the power-down state. In addition, the MC_PCU acts as a bridge for mapping the VREG peripheral to the MC_PCU address space. Figure 29-1 depicts the MC_PCU block diagram. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 986: Features
A handshake mechanism for power state changes thus guaranteeing operable voltage • Maps the VREG registers to the MC_PCU address space 29.1.3 Modes of operation The MC_PCU is available in all device modes. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 987: External Signal Description
Any access to unused registers as well as write accesses to read-only registers will: • Not change register content • Cause a transfer error Table 29-2. MC_PCU memory map Address Name 0xC3FE_8000 PCU_PCONF0 0xC3FE_8004 PCU_PCONF1 0xC3FE_8008 PCU_PCONF2 MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 988: Register Descriptions
0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address 0xC3FE_8043. 29.3.2.1 Power Domain #0 Configuration Register (PCU_PCONF0) Address 0xC3FE_8000 Access: Supervisor read Reset Reset Figure 29-2. Power Domain #0 Configuration Register (PCU_PCONF0) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 989 1 Power domain on STOP Power domain control during Stop mode 0 Power domain off 1 Power domain on STBY0 Power domain control during Standby mode 0 Power domain off 1 Power domain on MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 990: Power Domain #1 Configuration Register (Pcu_Pconf1)
Figure 29-4. Power Domain #2 Configuration Register (PCU_PCONF2) This register defines for power domain #2 whether it is on or off in each device mode. The bit field description is the same as in Table 29-3. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 991: Power Domain Status Register (Pcu_Pstat)
MC_PCU Configuration Per default, all power domains are powered in all modes other than Standby. Software can change the configuration for each power domain on a mode basis by programming the PCU_PCONFn registers. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 992: Mode Transitions
When the MC_PCU receives a mode change request to Run0, it starts its startup phase if PCU_PCONF2.RUN0 is 1. The power domain is re-connected to the power supply, and the voltage in MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 993: Standby Mode Transition
STANDBY DRUN startup state startup phase startup state power-down power-down state phase Notes: Not drawn to scale; PCONF1.RUN0 = 1; PCONF1.STBY0 = 0 Figure 29-7. MC_PCU Events During Power Sequences (Standby mode) MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 994: Power Saving For Memories During Standby Mode
Additional power is required during restoring the information (e.g. in the platform). Care should be taken that the time during which the SoC is operating in Standby mode is significantly longer than the required time for restoring the information. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 995: Preface
Advanced Microcontroller Bus Architecture Chip Select. Direct Memory Access. End of Queue Least Significant Bit Most Significant Bit Peripheral Chip Select QSPI, QuadSPI Quad Serial Peripheral Interface Serial Communications Clock Serial Peripheral Interface MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 996: Glossary For Quadspi Module
First-In-First-Out buffer for received data Serialize To convert data from a parallel format to a serial format. To set a bit or bits means to establish logic level one on the bit or bits. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 997: Introduction
The combination of SCK polarity, SCK phase, data MSB/LSB first, and associated CS signal timing during a serial transmission TX FIFO First-In-First-Out buffer for transmit data 30.2 Introduction Figure 30-1 is a block diagram of the Quad Serial Peripheral Interface (QuadSPI) module. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 998 & Dataflow Control QSPI_IF QSPI_IF_core core clock domain Shift Register Clock Domain Crosser Baud Rate, Delay and Transfer Control QSPI_IF_sclk ModeMux Pad_Ctrl SCLK clock domain Functionality QuadSPI Bus Figure 30-1. QuadSPI block diagram MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 999: Overview
SPI Serial Flash supporting single, dual and quad mode of operation. • One chip select signal dedicated for usage with a serial flash device. • DMA support to read RX Buffer data via AMBA AHB bus. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...
Page 1000: Quadspi Modes Of Operation
Stop mode The Stop mode is also used for power management. When a request is made to enter Stop mode, the QuadSPI block completes the action currently processed. Then the request is acknowledged. MPC5606S Microcontroller Reference Manual, Rev. 7 Freescale Semiconductor...

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NXP Semiconductors MPC5606S Reference Manual

Chapter 1

Chapter 10

Crossbar Switch (XBAR)

Chapter 15 Enhanced Direct Memory Access (Edma)

Chapter 21

Interrupt Controller (INTC)

Chapter 5 Analog-To-Digital Converter (ADC)

Chapter 11 Deserial Serial Peripheral Interface (DSPI)

Chapter 35 Stepper Motor Controller (SMC)

Chapter 2

Chapter 3

Chapter 4

Chapter 6

Chapter 23

Chapter 7

Chapter 8

Chapter 9

Chapter 12 Register Summary

Chapter 14 Integer Unit Features

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