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Freescale Semiconductor
Application Note
Qorivva MPC57xx e200zx Core
Differences
c55 process migration
by: Randy Dees
1 Introduction
Freescale's Qorivva MPC57xx devices are the latest
generation of Automotive microcontrollers (MCU) based on
the Power Architecture™ core. This generation is
manufactured in a 55 nm wafer processing flow (c55).
Previous generations of devices were manufactured in larger
geometry technologies.
In addition to being manufactured in a smaller technology, the
e200zx cores used in the c55 devices have been updated for
higher speeds, lower power, and better die size utilization
(equating to lower cost for the core itself). Many features of
the cores are selectable by the definition requirements of the
individual devices that use these cores. This document outlines
major differences in the e200zx cores based on the options
selected for devices in the MPC57xx family. While it lists the
differences and gives a basic summary of the feature, this
document does not fully explain the feature in detail. The core
reference manuals should be consulted for additional
information.
The table below shows the different technologies, as well as
the different types of cores that are used by the different
families of devices, starting with the first fully integrated
Power Architecture core with embedded nonvolatile flash
memory and peripherals (MPC555). There was an earlier
Automotive Power Architecture, the MPC505/MPC509,
however, it did not have integrated flash or peripherals.
© 2013 Freescale Semiconductor, Inc.
Document Number:AN4802
Contents
1
Introduction................................................................1
1.1
MPC57xx core instantiations..... .................... 2
2
cores...........................................................................3
2.1
e200zx core execution options....................... 3
2.2
options........................................... ................ 5
2.3
e200zx debug options............. ....................... 7
A
Revision history.......................... ............................ 10
Rev 0, 10/2013
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Summary of Contents for NXP Semiconductors MPC57xx
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Page 1: Table Of Contents
This document outlines major differences in the e200zx cores based on the options selected for devices in the MPC57xx family. While it lists the differences and gives a basic summary of the feature, this document does not fully explain the feature in detail. -
Page 2: Mpc57Xx Core Instantiations
1.1 MPC57xx core instantiations Many of the different devices in the MPC57xx family have a varying number of cores, including devices with different types of cores. The following table shows the cores that are instantiated on the different devices in the family. In addition, it shows the core that debuggers can access after reset with a blank flash (or when a valid reset configuration is not programmed into the flash). -
Page 3: Differences Between Mpc57Xx E200Zx Cores
The second major generation of the e200zx cores has minor variations for different devices. The following sections show all of the devices in the MPC57xx family and the variations of the cores used in each device (and version). The core options have been divided into three sections: •... - Page 4 Variable Length Encoded (VLE) instruction set. The previous e200z0 cores used on some of the MPC5500 and MPC5600 devices supported only the VLE instruction set. Most of new MPC57xx devices support only the VLE instruction set, however, there is at least one device planned in the future that will support the full Book E instruction set.
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Page 5: E200Zx Bus Interface And Memory Options
(SPE) supports a full range of instructions for digital signal processing algorithms. There are currently two major versions of the SPE (1.1 and 2.1) that are supported on the MPC57xx devices. No signal processing instructions — Some core variations do not include any type of signal processing extensions. - Page 6 Memory Protection Unit (MPU) - The Memory Protection Unit (MPU) allows memory regions to be protected from being accessed by certain cores, protected from being modified by certain cores, protected from core execution, for enabling or disabling of being cached, and for other safety protection features. Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013 Freescale Semiconductor, Inc.
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Page 7: E200Zx Debug Options
Each of the options is then explained. Table 6. e200zx cores debug feature options e200z210 based cores Table continues on the next page... 1. Not all devices support an external bus. Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013 Freescale Semiconductor, Inc. - Page 8 Fixed (unbuffere MPC5777M Core 2 MPC5744P Core 0 e200z4251n3 30 or 4 Fixed Fixed e200z710 based cores MPC5777M Core 0/1 e200z710n3 Fixed Fixed Table continues on the next page... Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013 Freescale Semiconductor, Inc.
- Page 9 Aurora port. Smaller sizes are generally used for a parallel Message Data Output Nexus port. Some core variations support two port widths, while some variations support only a single port width. This is primarily to support either the Nexus Port Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013 Freescale Semiconductor, Inc.
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Page 10: Revision History
DQTAG as a Variable length packet instead of the Fixed length field. Appendix A Revision history The table below shows the complete revision history of this document. Table A-1. Revision History Revision Author Changes Randy Dees Initial customer release. Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013 Freescale Semiconductor, Inc. - Page 11 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express Home Page: or implied copyright licenses granted hereunder to design or fabricate freescale.com any integrated circuits based on the information in this document. Web Support: Freescale reserves the right to make changes without further notice to any products herein.
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