Mitsubishi Electric MELSEC Q Series Programming Manual page 68

Other applicable data
For bit data, an index setting is applicable to device numbers whose digits are specified.
Note that an index setting is not applicable to the digit-specified bit device.
EN
s
K4X0Z2
EN
s
K4Z3X0
For intelligent function module devices
module and buffer memory addresses.
EN
s
U10Z1\G0Z2
For link direct devices
EN
s
J1Z1\K4X0Z2
For multiple CPU area devices
memory addresses.
EN
s
U3E0Z1\G0Z2
When applying an index setting to extended data registers (D) or extended link registers (W), it can be applied in 32-bit range
as applying an index setting to file registers (ZR) in the following two methods.
• Specify a range of index registers used for a 32-bit index setting.
• Specify a 32-bit index setting using 'ZZ'.
*1 For intelligent function module devices and link direct devices, refer to the User's Manual (Function Explanation, Program
Fundamentals) of the CPU module used.
*2 For multiple CPU area devices, refer to the User's Manual (Function Explanation, Program Fundamentals) of the CPU module used.
*3 For Universal model QCPU (excluding Q00UJCPU), and LCPU
32-bit index settings using 'ZZ' can be used for the following CPU modules only. For the usable programming
tool, refer to the operating manual of the programming tool.
• QnU(D)(H)CPU with a serial number whose first five digits are '10042' or higher (excluding Q00UJCPU)
• Built-in Ethernet port QCPU
• LCPU
4 PROGRAM CONFIGURATION
66
4.6 Index Setting
BIN
ENO
d
D0
Index setting is applicable
to the device number,
If Z2=3, then (X0+3)=X3
BIN
ENO
d
D0
Index setting is not applicable
to the digit-specified bit device.
*1
, an index setting is applicable to both start I/O numbers of the intelligent function
MOV
ENO
d
D0
If Z1=2 and Z2=8,
then U(10+2)\G(0+8)=U12\G8
*1
, an index setting is applicable to both network numbers and device numbers.
MOV
ENO
d
D0
If Z1=2 and Z2=8,
then J(1+2)\K4X(0+8)=J3\K4X8
*2
, an index setting is applicable to both start I/O numbers of the CPU module and CPU shared
MOV
ENO
d
D0
*3