Table of Contents
Advertisement
5: SPECIFICATIONS
5.3
Electrical Characteristics
Parameter
Input Leakage Current
OFF-state Leakage Current
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
Positive Trigger Voltage
Negative Trigger Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
Pulldown Resistance
Operating Supply Current
Quiescent Supply Current
(between HV
and V
)
DD
SS
Quiescent Supply Current
(between LV
and V
)
DD
SS
Note: 1. The pulse applied to the RESET# pin must be held low for 200 µs or more to be effective.
However, avoid keeping the input pulse active for more than several seconds because the
LCD's d.c. drive capability may be adversely affected.
2. The VB0–DB7 pins come with a feedback circuit, so that even when input becomes high im-
pedance, the pins retain the state held immediately before. Therefore, input voltage of an in-
termediate level allows input current to flow to the pin.
84
Symbol
Test Condition
I
—
LI
I
—Note 2)
OZ
I
= -8.0mA
OH
V
OH
HV
=Min
DD
I
= 8.0m
OL
V
OL
HV
=Min
DD
CMOS level
V
IH1
HV
= Max
DD
CMOS level
V
IL1
HV
= Min
DD
V
CMOS Schmitt
T1+
V
CMOS Schmitt
T1-
V
CMOS Schmitt
H1
TTL level
V
IH2
HV
= Max
DD
TTL level
V
IL2
HV
= Min
DD
VI = HV
R
DD
PD
f
=10 MHz
OSC
Nonloaded
I
opr
256 x 200dot
Sleep mode
I
QH
XCG1, CS#, RD# = V
Sleep mode
I
QH
XCG1, CS#, RD# = V
[V
= 0V, HV
SS
Min.
-1
-1
HV
-0.4
DD
—
3.5
—
2.0
0.8
0.3
2.0
—
30
—
—
DD
—
DD
EPSON
= 4.5 – 5.5V, Ta = -40 – 85°C]
DD
Rated Value
Typ.
Max.
—
1
—
1
—
—
—
0.4
—
—
—
1.0
—
4.0
—
3.1
—
—
—
—
—
0.8
60
144
TBD
TBD
—
30
—
35
S1D13700 Technical Manual
Unit
uA
uA
V
V
V
V
V
V
V
V
V
kΩ
mA
uA
uA
Advertisement
Table of Contents
