Microsemi IGLOO2 User Manual
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Microsemi IGLOO2 User Manual

Microsemi IGLOO2 User Manual

Fpga evaluation kit
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Summary of Contents for Microsemi IGLOO2

  • Page 1 IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 3: Table Of Contents

    IGLOO2 FPGA Evaluation Kit User Guide Table of Contents 1 – Introduction ....................5 Kit Contents ..........................5 IGLOO2 FPGA Evaluation Kit Web Resources ................. 5 Board Description ........................5 2 – Installation and Settings ................. 9 Software Installation ........................9 Hardware Installation .........................
  • Page 4 Product Support ..................61 Customer Service ........................61 Customer Technical Support Center ..................61 Technical Support ........................61 Website ............................ 61 Contacting the Customer Technical Support Center ............... 61 ITAR Technical Support ......................62 IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 5: Introduction

    A (SMA) connectors, a 64-bit GPIO Header, and various connectors for SPI support. The IGLOO2 memory management system is supported by 512 Mb of on board mobile LPDDR SDRAM memory and 64 Mb SPI flash. The serializer and deserializer (SERDES) block can be accessed through the peripheral component interconnect express (PCIe) edge connector or high speed SMA connectors.
  • Page 6 USB micro AB connector Figure 1. IGLOO2 FPGA Evaluation Kit Block Diagram Board Overview Figure 2 shows an overview of the IGLOO2 Evaluation Kit Board features. Figure 2. IGLOO2 FPGA Evaluation Kit Board Overview IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 7 512 Mb (MT46H32M16LF – 8 Meg x 16 x 4 banks) for storing the data bits. SDRAM SPI flash 64 Mb SPI flash Winbond electronics W25Q64FVSSIG connected to SPI port 0 of the IGLOO2 FPGA high performance memory system (HPMS). Ethernet...
  • Page 8 1 – Introduction Name Description USB3320, interfacing with FPGA pins of the IGLOO2 HPMS. OSC-125 125 MHz clock oscillator (differential output) OSC-50 50 MHz clock oscillator OSC-32 32.768 KHz low-power oscillator IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 9: Installation And Settings

    Download and install the latest release of Microsemi Libero System-on-Chip (SoC) software v11.1 or later, from the Microsemi website and register for a free Gold license. For instructions on how to install Libero and SoftConsole, Libero Installation and Licensing Guide refer to the available on the Microsemi website.
  • Page 10 1.2 V current sensing test point TP15 1.8 V current sensing test point TP16, TP17 Test points across current sense resistor 0.05 Ohms for 1.2 V TP18, TP19 Test points across current sense resistor 0.05 Ohms for 1.8 V IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 11: Igloo2 Power Sources

    Testing the Hardware If the board is shipped directly from Microsemi, it contains a test program that determines whether or not the board works properly. If you suspect that the board is damaged, you can rerun the Manufacturing Test to verify the key interfaces of the board functionality.

  • Page 13: Key Components Description And Operation

    Measure the output voltage (VOUT) at TP14. I = (VOUT/5) Core Power consumed P= (1.2 V)*I For example, when the voltage measured across TP14 as 0.5 V, then the consumed core power is 0.12 W. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 14 1.2 V Current Sensing for Flash*Freeze The IGLOO2 device consumes very low power in Flash*Freeze mode. The voltage across the sense resistor (0.05 ohms) needs to be measured directly using a precision digital multi-meter that can read sub milli-volts. Test points TP16 and TP17 can be used to directly measure voltage across the 1.2 V sense resistor.

  • Page 15: Memory Interface

    3 – Key Components Description and Operation Memory Interface Dedicated I/Os are provided for HPMS DDR and fabric DDR for the IGLOO2 device. Apart from the dedicated I/Os, regular I/Os can also be used to connect to other memory devices. Refer to...

  • Page 16: Serdes0 Interface

    RX pad via trace routed in 6th layer via (to top layer) trace AC Coupling trace Marvel PHY pin SERDES0 reference clock 0 is routed directly from the PCIe connector to IGLOO2 FPGA. SERDES0 reference clock 1 is routed from the onboard 125 MHz clock oscillator and optionally routed from SMA connectors through LVDS Mux/Buffer chip.
  • Page 17 Table Note: • SERDES0 TXD pairs are capacitively coupled to the IGLOO2 device. Series AC coupling capacitors are used to provide Common mode voltage independence. • The AC coupling capacitors are not provided for SERDES 0 RXD signals. The mating board should have the AC coupling capacitors.

  • Page 18: Usb Interface

    1000BASE-T full or half duplex Ethernet on CAT5 twisted pair cable. The PHY connection to a user-provided Ethernet cable is through an RJ-45 connector with built-in magnetics. The 88E1340S device supports the quad SGMII for direct connection to an IGLOO2 chip. Refer to Figure The 88E1340S is configured through the CONFIG [3:0] pins and CLK_SEL [1:0].
  • Page 19 Oscillator- 125MHz REF_CLKP REF_CLKN SCLK XTAL_IN 25 MHz XTAL_OUT JTAG FT4232H Figure 10. IGLOO2 Marvell PHY Interface Note: For more information, refer to page 11 and 12 of Board Level Schematics document (provided separately). IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 20: Programming

    One 10X2 RVI header is provided on the board for debugging. This header allows plugging in the Keil ULINK debugger or IAR J-Link debugger. FlashPro4 Programming Header The IGLOO2 device on the Evaluation Kit can be programmed using a FlashPro4 programmer. In addition, FlashPro4 is used for software debugging by SoftConsole. Note: •...

  • Page 21: I2C Port Header

    Header - H1 MSIO28NB1 I2C0_SCL 10, 14 MSIO28PB1 I2C0_SDA 11, 15 MSIO11NB2/CCC_NE0_CLKI2 I2C1_SCL 2, 6 MSIO11PB2/CCC_NE0_CLKI1 I2C1_SDA 3, 7 Note: For more information, refer to page 8 of Board Level Schematics document (provided separately). IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 22: System Reset

    50 MHz clock oscillator with +/-50 ppm is available on the board. This clock oscillator is connected to the FPGA fabric to provide a system reference clock. An on-chip IGLOO2 PLL can be configured to generate a wide range of high precision clock frequencies. Table 8. 50 MHz Clock...

  • Page 23: Debugging

    32.768 KHz crystal oscillators for main and auxiliary oscillators of IGLOO2 FPGA. Debugging User LEDs The board provides user access to eight active low LEDs, which are connected to the IGLOO2 device for debugging applications. Table 8 lists the onboard debugging LEDs.
  • Page 24 For more information, refer to page 15 of Board Level Schematics document (provided separately). Slide Switches–DPDT SW7–Power ON/OFF switch from external DC Jack, +12 V DC DIP Switch - SPST SW5–is a DIP switch that has four connections to the IGLOO2 device. Table 10 lists the onboard DIP switches. Table 11. DIP Switches...

  • Page 25: Gpio Header Pin Out

    Pin Name AB15 MSIO110PB4 3P3V AA15 MSIO110NB4 AA16 MSIO114PB4 AB18 MSIO118PB4 AA17 MSIO114NB4 AB19 MSIO118NB4 AB17 MSIO113PB4 MSIO117PB4 AA18 MSIO113NB4 MSIO117NB4 MSIO116PB4 MSIO115PB4 MSIO116NB4 MSIO115NB4 MSIO112PB4 MSIO27PB1 MSIO112NB4 MSIO27NB1 MSIO108PB4 MSIO111PB4 MSIO108NB4 MSIO111NB4 MSIO66PB7 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 26 Header- J1 Header- J1 Pin No Pkg No Pin Name Pin No Pkg No Pin Name MSIO67PB7 MSIO66NB7 MSIO67NB7 MSIO70PB7 MSIO64PB7 MSIO70NB7 MSIO64NB7 MSIO65PB7 MSIO69PB7 MSIO65NB7 MSIO69NB7 MSIO71PB7 MSIO72PB7 MSIO71NB7 MSIO72NB7 MSIO68PB7 3P3V MSIO68NB7 3P3V IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 27: Pin List

    4 – Pin List Table 12 lists the pins for IGLOO2 M2GL010T-FG484 devices. Note: *D21- Pin cannot be used as a fabric output and it is only an Input. Table 13. Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name DDRIO51PB0/MDDR_DM_RDQS0 DDRIO51NB0/MDDR_DQ4 DDRIO48PB0/MDDR_DQ8...
  • Page 28 AA21 JTAGSEL AA22 SERDES_0_TXD1_N SERDES_0_TXD2_N SERDES_0_TXD3_N AB10 AB11 VDDI4 AB12 MSIO105PB4/CCC_NE0_CLKI0 AB13 MSIO105NB4 AB14 MSIO110PB4 AB15 AB16 MSIO113PB4 AB17 MSIO118PB4 AB18 MSIO118NB4 AB19 SERDES_0_TXD0_P AB20 XTLOSC_MAIN_XTAL AB21 AB22 SERDES_0_TXD1_P SERDES_0_TXD2_P SERDES_0_TXD3_P MSIO71NB7 DDRIO52PB0/MDDR_DQS0 VDDI0 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 29 DDRIO41PB0/MDDR_CKE VDDI0 DDRIO37NB0/MDDR_ADDR0 DDRIO34PB0/MDDR_ADDR5 MSIO69PB7 VDDI0 DDRIO31NB0/MDDR_ADDR11 MSIO27NB1 MSIO65NB7 DDRIO62PB0 DDRIO59PB0/GB0 DDRIO58NB0/MDDR_DQS_ECC_N VDDI0 DDRIO54PB0/MDDR_DQ0 MSIO71PB7 VDDI0 DDRIO52NB0/MDDR_DQS0_N DDRIO46NB0/MDDR_DQS1_N VDDI0 DDRIO41NB0/MDDR_CS_N DDRIO37PB0/MDDR_BA2 DDRIO35PB0/MDDR_ADDR3 DDRIO35NB0/MDDR_ADDR4 DDRIO33NB0/MDDR_ADDR7 VDDI7 DDRIO33PB0/MDDR_ODT MSIO27PB1 MSIO65PB7 MSIO64PB7 DDRIO61PB0 VDDI0 DDRIO58PB0/MDDR_DQS_ECC DDRIO55NB0 MSIO72PB7 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 30 DDRIO47PB0/MDDR_DQ10 DDRIO47NB0/MDDR_DQ11 DDRIO43PB0/MDDR_DQ14 DDRIO36PB0/MDDR_ADDR1 VDDI0 DDRIO29PB0/MDDR_ADDR14 MSIO72NB7 DDRIO30NB0/MDDR_ADDR13 MSI26NB1 FLASH_GOLDEN_N MSIO68PB7 MSIO68NB7 MSIO64NB7 DDRIO61NB0 MDDR_IMP_CALIB_ECC DDRIO57NB0/MDDR_DM_RDQS_ECC DDRIO55PB0/CCC_NE0_CLKI3 MSIO73PB7 DDRIO53NB0/MDDR_DQ3 VDDI0 DDRIO49PB0/MDDR_DQ7 DDRIO43NB0/MDDR_DQ15 DDRIO40PB0/MDDR_RESET_N DDRIO36NB0/MDDR_ADDR2 DDRIO32PB0/MDDR_ADDR8 DDRIO29NB0/MDDR_ADDR15 DDRIO30PB0/MDDR_ADDR12 MSIO73NB7 VDDI1 MSIO25NB1 MSIO25PB1 MSIO70PB7 MSIO70NB7 DDRIO60PB0/MDDR_TMATCH_ECC_OUT IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 31 M2GL010TS/M2GL010T-FG484 Pin Name DDRIO57PB0/MDDR_TMATCH_ECC_IN VDDI7 DDRIO53PB0/MDDR_DQ2 DDRIO49NB0/MDDR_TMATCH_0_OUT VDDI0 DDRIO42PB0/MDDR_RAS_N DDRIO40NB0/MDDR_CAS_N DDRIO32NB0/MDDR_ADDR9 MSIO24NB1 MSIO24PB1 MSIO23NB1 MSIO23PB1 VDDI1 MSIO74PB7 MSIO74NB7 MSIO67PB7 MSIO67NB7 VDDI0 DDRIO60NB0/CCC_NE1_CLKI3 VDDI0 MSIO78NB7 VREF0 VREF0 DDRIO45PB0/MDDR_TMATCH_0_IN DDRIO45NB0/MDDR_DM_RDQS1 DDRIO42NB0/MDDR_WE_N VREF0 MSIO28NB1 MSIO28PB1 MSIO22NB1 MSIO22PB1/GB6 VDDI7 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 32 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name MSIO66PB7 MSIO66NB7 MSIO75NB7 MSIO78PB7/GB2 VDDI0 VDDI0 CCC_NE0_PLL_VDDA MDDR_PLL_VDDA MDDR_PLL_VSSA VDDI1 MSIO21NB1 MSIO21PB1/GB5 MSIO77PB7 MSIO77NB7 MSIO76PB7 MSIO75PB7 MSIO80PB7 CCC_NE0_PLL_VSSA CCC_NE1_PLL_VSSA CCC_NE1_PLL_VDDA MSIO20NB2 MSIO80NB7 VDDI1 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 33 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name MSIO79PB7/GB1 MSIO79NB7 MSIO76NB7 VDDI7 MSIOD85PB6/CCC_NE1_CLKI1 MSIO18NB2 MSIO19NB2 MSIO19PB2 MSIO20PB2 MSIOD85NB6 MSIO17NB2 MSIO17PB2 VDDI6 MSIOD82PB6 MSIOD82NB6 MSIO81PB7 MSIO81NB7 MSIOD83PB6 MSIO18PB2 VDDI2 MSIO16NB2 MSIO16PB2 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 34 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name MSIOD86PB6 MSIO15NB2 MSIO15PB2 MSIOD86NB6 MSIOD87PB6 MSIOD87NB6 VDDI6 MSIOD84NB6 MSIOD83NB6 MSIOD92NB6 VPPNVM MSIOD90NB6 VDDI2 MSIO14PB2 MSIO14NB2 MSIOD90PB6 MSIOD88PB6 MSIOD88NB6 MSIOD84PB6/CCC_NE1_CLKI2 MSIOD95NB6 MSIOD92PB6 VSSNVM MSIO8PB2 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 35 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name MSIO8NB2 MSIO12PB2/SPI_0_CLK VDDI6 MSIO12NB2/SPI_0_SDI MSIO13PB2/SPI_0_SDO MSIO13NB2/SPI_0_SS0 MSIOD91PB6 MSIOD91NB6 MSIOD89PB6 MSIOD89NB6 MSIOD95PB6 MSIOD94PB6 MSIO7NB2 MSIO6PB2 MSIO6NB2 SC_SPI_SDO MSIOD94NB6 SC_SPI_SS MSIO11PB2/CCC_NE0_CLKI1 MSIOD93NB6 MSIOD93PB6 VDDI6 MSIOD96PB6 MSIOD96NB6 SERDES_0_VDD MSIOD97NB6 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 36 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name DEVRST_N MSIO7PB2 MSIO1PB2 MSIO1NB2 VDDI2 MSIOD97PB6 SC_SPI_CLK SC_SPI_SDI MSIO11NB2/CCC_NE0_CLKI2 MSIOD98PB6 MSIOD98NB6 SERDES_0_L01_VDDAIO MSIOD100NB5/SERDES_0_REFCLK0_N SERDES_0_L23_VDDAIO MSIO107NB4 VDDI4 MSIO2PB2 MSIO2NB2 MSIO5PB2 MSIO5NB2 VDDI2 MSIOD99NB6 MSIOD99PB6 SERDES_0_PLL_VSSA SERDES_0_PLL_VDDA SERDES_0_VDD MSIOD100PB5/SERDES_0_REFCLK0_P IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 37 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name MSIO107PB4 MSIO112PB4 MSIO112NB4 MSIO0PB2 VDDI5 MSIO4NB2 MSIO4PB2 MSIOD101PB5/SERDES_0_REFCLK1_P MSIOD101NB5/SERDES_0_REFCLK1_N SERDES_0_L01_REXT SERDES_0_L01_REFRET SERDES_0_L01_VDDAPLL SERDES_0_L23_VDDAPLL VDDI4 MSIO104PB4/GB3 MSIO108PB4 MSIO108NB4 MSIO115NB4 MSIO0NB2 JTAG_TMS MSIO3NB2 MSIO3PB2 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 38 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name SERDES_0_L23_REXT SERDES_0_L23_REFRET SERDES_0_RXD0_P MSIO103PB4/PROBE_A MSIO104NB4/GB7 VDDI4 MSIO109NB4 MSIO111NB4 MSIO115PB4 MSIO116NB4 JTAG_TCK VDDI3 JTAG_TDI SERDES_0_RXD1_P SERDES_0_RXD2_P SERDES_0_RXD3_P MSIO102PB4 SERDES_0_RXD0_N MSIO103NB4/PROBE_B MSIO106NB4 MSIO109PB4 MSIO111PB4 VDDI4 MSIO116PB4 MSIO117PB4 MSIO117NB4 JTAG_TDO JTAG_TRSTB SERDES_0_RXD1_N IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 39 4 – Pin List PKG.PIN M2GL010TS/M2GL010T-FG484 Pin Name SERDES_0_RXD2_N SERDES_0_RXD3_N MSIO102NB4/CCC_NE1_CLKI0 IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 41: Board Components Placement

    5 – Board Components Placement The IGLOO2 Evaluation Kit components placement on top and bottom sides, are shown in the following figures. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 42 100MBPS LINK LPDDR M2GL_M2S-EVAL-KIT DVP-102-000402-001 Rev C DPR1 I2C0_SCL SERDES_REFCLK1P FTDI TP18 TP19 1P8V_CUR_SENSE 1P8V Active TP11 CLK_EN 1P2V_CUR_SENSE XTAL 1P2V TP10 SERDES_REFCLK1 TP15 C103 TP14 CON1 B11 B12 Figure 18. Silkscreen Top View IGLOO2 FPGA Evaluation Kit User Guide SILKSCREEN_TOP...
  • Page 43 C309 R229 C317 R228 C321 C325 C324 C326 C329 C362 R230 R232 C333 R238 R237 C334 C335 R272 R239 C336 C359 C337 R243 R244 R245 R249 R267 R254 CON1 Figure 19. Silkscreen Bottom View IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 45: Demo Design

    The IGLOO2 M2GL-EVAL-KIT comes with a preloaded PCIe control plane demo design. This demo design demonstrates key features of IGLOO2 device such as - PCIe, GPIOs, and fabric interface controller of the IGLOO2 device. These features can be used for rapid prototyping and validation of user specific designs.

  • Page 47: Manufacturing Test

    M2GL-EVAL-KIT Board Testing Procedures IGLOO2 M2GL-EVAL-KIT contains a manufacturing test program that can be run to verify the functionality of the board. This program contains a list of options that can be run as diagnostics for the SERDES interface, low-power DDR (LPDDR), serial programming interface (SPI) flash, and debugging the LEDs and switches.
  • Page 48 7 – Manufacturing Test Figure 20. SERDES TEST APP Window Click the port settings tab on the SERDES TEST APP window. Figure 21 shows the port settings tab. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 49 7 – Manufacturing Test Figure 21. Port Settings Tab Select the highest COM port from the drop-down list and click Open to establish the connection with the test PC. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 50 7 – Manufacturing Test Figure 22. Selecting the COM Port Click the serdes analyzer tab to verify the connection. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 51 Make sure that Communication Status indicator is in green. If the UART communication is not set up properly, Communication Status indicator will be in red. Note: If the Core Reset status indicator is shown in green, click Deassert Core Reset to disable the core reset. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 52 Click Enable Near(TX to RX) loopback to enable the internal near end loopback on SERDES Lane 0. Figure 26. Enabling Internal Loopback shows Near lpbk status indicator in green after clicking Enable Near(TX to RX) loopback. Figure 27 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 53 11. Click Disable PRBS Gen +checker to stop the packet transmission and click Disable Near (TX to RX) loopback to disable the loopback. After clicking, Near LPBK status and PRBS gen status indicators change to red. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 54 Figure 31. Selecting SERDES Lane 1 Click Enable PRBS Gen+checker to check the error count. Figure 32. Enabling PRBS Genarator shows PRBS gen status indicator in green after clicking Enable PRBS Gen+checker. Figure 33 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 55 LPDDR and SPI Test Use the following procedure to initiate LPDDR and SPI tests on IGLOO2 Evaluation Kit: Connect USB cable (mini USB to Type A USB cable) to J18 and other end of the cable to the USB port of test PC.
  • Page 56 Select the highest COM port from the drop-down list and click Open to establish the connection with the test PC. Figure 36. Selecting COM Port Note: When using the USB cable for UART communication, four COM ports are shown in the drop-down list. Click the register configuration tab. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 57 Figure 38 shows the test status as Pass once the test is completed successfully. Figure 38. LPDDR Test Note: If the LPDDR test fails, the number of locations are displayed where the test is failed. IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 58: Switches And Led Tests

    After power ON, power supplies with respect to the ground must be measured and the range must be as listed in Table Table 15. Power Supply Range Power Rail Probing point Accepted Voltage Range. (in Volt) 1P2V C95 Pin 2 1.15<VDD_REG<1.25 5P0V C16 pin 2 4.75<5P0V<5.25 3P3V C76 pin 2 3.15<3P3V<3.46 IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 59 Measure clock signal at Y2 pin 3 and ensure that the stable 50 MHz signal is available. Reset Measurement Measure reset signal at resistor R14 and ensure that this is 3.3 V and held High. FPGA Programming Check whether IGLOO2 has been successfully programmed through the JTAG interface. IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 60: List Of Changes

    The revision number is located in the part number after the hyphen. The part number is displayed at the bottom of the last page of the document. The digits following the slash indicate the month and year of publication. IGLOO2 FPGA Evaluation Kit User Guide...

  • Page 61: Product Support

    Fax, from anywhere in the world 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues and various FAQs.

  • Page 62: Itar Technical Support

    For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), Cases, select Yes in the ITAR drop-down list. contact us via soc_tech_itar@microsemi.com. Alternatively, within complete list ITAR-regulated Microsemi FPGAs, visit ITAR page. IGLOO2 FPGA Evaluation Kit User Guide...
  • Page 64 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA © 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Within the USA: +1 (949) 380-6100 Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

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