Read File Register - Delta DVP-PLC Applications Manual

API Mnemonic
148 D MEMR P
Type Bit Devices
X Y
OP
m
D
n
Operands:
m: Address in the file register to be read
n: Number of data read at a time
Explanations:
1. Range of m: K0 ~ K1,599 (SA/SX/SC); K0 ~ K9,999 (EH/EH2/SV)
2. Range of D: D2000 ~ D4999 (SA/SX/SC); D2000 ~ D9999 (EH/EH2/SV)
3. Range of n: For 16-bit instruction K1 ~ K1,600 (SA/SX/SC), K1 ~ K8,000 (EH/EH2/SV); For 32-bit instruction
K1 ~ K800 (SA/SX/SC), K1 ~ K4,000 (EH/EH2/SV)
4. See the specifications of each model for their range of use.
5. Flag: M1101. See explanations below.
6. SA/SX/SC/EH/EH2/SV uses this instruction to read the data in file registers and store them into data registers.
7. SA/SX/SC offers 1,600 16-bit file registers.
8. m and n of SA/SX/SC do not suppot E and F index register modification.
9. EH/EH2/SV offers 10,000 16-bit file registers.
10. If m, D and n fall without their range, operation error will occur. M1067, M1068 = On and D1067 will record the
error code H'0E1A.
Program Example 1:
1. The 16-bit instruction MEMR reads 100 data at address 10 in the file register and store the read data in register
D starting from D2000.
2. When X0 = On, the instruction will be executed. When X0 = Off, the instruction will not be executed and the
previously read data will remain unchanged.
X0
MEMR
Program Example 2:
1. The 32-bit instruction DMEMR reads 100 data at address 20 in the file register and store the read data in
register D starting from D3000.
2. When X0 = On, the instruction will be executed. When X0 = Off, the instruction will not be executed and the
previously read data will remain unchanged.
X0
DMEMR
DVP-PLC Application Manual
Operands

Read File Register

M S K H KnX KnY KnM KnS T
* *
* *
ES EX SS SA SX SC EH SV ES EX SS SA SX SC EH SV ES EX SS SA SX SC EH SV
D: Device for storing the read data (starting from the designated D)
K10 D2000 K100
K20 D3000 K100
8 Application Instructions API 100-149
Function
Word Devices
C
PULSE
Controllers
ES/EX/SS SA/SX/SC EH/SV
Program Steps
D E F MEMR, MEMRP: 7 steps
*
DMEMR, DMEMRP: 13 steps
*
*
16-bit 32-bit
8-67