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Motorola MB68k-100 User Manual

68000 motherboard
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Rev. A
Grant K.
(c) 2011

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Summary of Contents for Motorola MB68k-100

  • Page 1 Rev. A Grant K. (c) 2011...

  • Page 2: Table Of Contents

    68000 Motherboard User’s Manual Rev. A TABLE OF CONTENTS INTRODUCTION ............4 DESIGN MOTI VATION ..........4 DESIGN INSPI RAT ION ..........4 WHAT I S A COMPUT ER? ..........7 THE M B68K-100 COMPUT ER ........13 MB 68k -10 0 Spe ci fi cat ion ............13 Wh at’...
  • Page 3 68000 Motherboard User’s Manual Rev. A 7.12. 3 On-Boar d Ou tpu t Lat ch ............37 7.13 Inter rup t Log ic ..............37 7.14 On-Boar d Me mory Ban ks 0 /1 ..........38 7.15 Sta ck In terf a ce ..............39 7.15.

  • Page 4: Introduction

    MB68k-100’s design philosophy is one to emphasize clear understanding of the system at every level. With its discrete circuit...
  • Page 5 It found a home in an array of computer peripherals, networking equipment and other high-end gadgetry. My own childhood laser printer succumbed to the screwdriver, yielding a traditional 64-pin PDIP Motorola 68000 at its core. This processor defined a generation of computing in each market it touched.
  • Page 6 The 68000’s sophisticated design was born of its advanced implementation in silicon. A relatively late arrival to the 16-bit processor field, Motorola’s 68000 design was able to leverage an increased level of integration on silicon. Constructed in superior HMOS (High Density, Short Channel MOS) technology, the pull-up device in each gate’s output...

  • Page 7: What I S A Comput Er

    Source- BYTE Publications Inc., Design Philosophy Behind Motorola’s MC68000, Nanocoding implements April 1983 deeper level of execution for common sequences that appear within the encoding of different instructions. A picture of the processor die is broken down in Figure 1, indicating the function of each circuit section.
  • Page 8 68000 Motherboard User’s Manual Rev. A numeral system is base 2, meaning that only these two digits are available. In base 2 the significance of each digit’s place along a binary number differs by a factor of 2. When written, binary numbers are expressed with a trailing subscript 2. Like in the base 10 system, the number 1 in binary represents a one.
  • Page 9 68000 Motherboard User’s Manual Rev. A Table 2: Extended ASCII Code Table Table 3: ASCII Code Example Character ASCII Code (Hexadecimal) The hardware in the computer design is responsible for the routing of the digital information to perform the computer’s operation. For example, the computer may be controlling multiple elements of a digital light bar output according to the states set on a series of digital inputs.
  • Page 10 68000 Motherboard User’s Manual Rev. A Figure 2: Data Flow Diagrams, Read The mechanics of the Write operation, shown in Figure 3 below, closely follow the Read. The target device is specified by its address. But the Read/Write line here indicates a Write operation is to be executed.
  • Page 11 68000 Motherboard User’s Manual Rev. A These basic functions are the microprocessor instructions. Microprocessor instructions are the most fundamental building blocks of any program. Any program is composed of these individual steps that are carried out directly in the computer hardware. The specific vocabulary of these primitive program operations is defined by the particular microprocessor in use.
  • Page 12 68000 Motherboard User’s Manual Rev. A Table 4: Initialization Example with Assembly Language +Offset Op Code Instruction Source Operand Destination Comment Mnemonic Operand … 2E7C MOVEA.L #(ONBD_BANK0+ 00004000 ONBD_BANK0_SZ), supervisor stack top of on- board SRAM 207C MOVEA.L #(ONBD_BANK0+ user 00003C00 ONBD_BANK0_SZ- stack next...

  • Page 13: The M B68K-100 Comput Er

    Rev. A The M B68k-100 Com put er The MB68k-100 is a single board computer based on the Motorola 68000 microprocessor. It offers many on-board features and is highly configurable via its multitude of jumpers and circuit access points. It also includes expansion capabilities through its stackable daughter board interface.
  • Page 14 68000 Motherboard User’s Manual Rev. A Table 6: Recommended and Absolute Ratings Guidelines* Rating Condition Value Unit System Clock, maximum as tested Supply Current, typ = 10MHz < 450 Supply Voltage, minimum Voltage Regulation bypassed +5.12 Voltage Regulation, VR120 installed with 7805 Voltage Regulation, VR120 installed with PT5101 Supply Voltage, maximum...

  • Page 15: What's W Hat And W Here Is I T

    68000 Motherboard User’s Manual Rev. A 5.2 What’s W hat and W here Is I t The overlay below maps some basic circuit sections of the MB68k-100 board. Figure 4: MB68k-100 Block Overlay Clock Sync Power Input Reverse Prot Interrupt Logic...

  • Page 16: Bas Ic Block Level Description

    Figure 5 below depicts a greatly simplified (and willfully incomplete) block diagram of the MB68k-100 motherboard’s architecture. The interrupt logic, for example, is completely neglected. But the purpose is to give a superficial primer of the basic system operation.
  • Page 17 68000 Motherboard User’s Manual Rev. A Figure 5: Rudimentary Architecture Block Diagram In brief, the following conceptually outlines the basic mechanics of a bus cycle: 1. The microprocessor sets up the Address Bus, Read/Write data direction and, for a Write operation, the Data Bus. 2.

  • Page 18: Glimps E Of T He 68000

    The Data and Address buses are shown, as well as the various control signaling. The functions and interactions of these signals are discussed in subsequent sections. For deeper detail, refer to the Motorola M68000 8-/16-/32-bit Microprocessors User’s Manual. Figure 6: 68000 Input and Output...

  • Page 19: Bus Contr Ol S Ignal Timing

    Data Transfer Acknowledge. It uses negative logic and is abbreviated as /DTACK. Motorola’s microprocessor literature refers to this means of bus control as asynchronous. Read cycles require that the data has arrived and stabilized on the data bus before the /DTACK signal is asserted.
  • Page 20 68000 Motherboard User’s Manual Rev. A clock edge between them, then no sequencing order is required. Put simply, data on the data bus must be established for the first falling clock edge once /DTACK is asserted. Write cycles require that the data on the bus be maintained by the processor for long enough to meet the hold time write requirement of the target device.
  • Page 21 For reference, see the bus cycle timing diagrams in the Bus Operations sections of the Motorola 68000 User’s Manual. Figure 8: Regular Bus Read Cycle...

  • Page 22: Bus Termination Int O A 6800 Bus Cycle

    7.1 Power I nput To start, the MB68k-100 motherboard requires DC input power. This may be provided either through the barrel connector, A1J120, or the terminal block connector, A1TB120. The barrel connector has a 2.1mm inner diameter and 5.5mm outer. It receives a barrel plug, such as the CUI Inc., PP3-002AH.

  • Page 23: Volt Age Regulat Ion

    +12VDC, where there is no additional load beyond the MB68k-100 board. If the voltage regulator is bypassed with A1JP121, the input voltage must still compensate for the drop across the reversal protection FET.

  • Page 24: The 68000 Micr Opr Ocess Or

    68000 Motherboard User’s Manual Rev. A threshold for reset trigger is controlled by the R140x/R141x resistor divider network. The threshold voltage per the base design is nominally 4.9V, with the tolerance range bounded between 4.7V and 5.0V. This selection meets both the minimum typical power voltage requirement for TTL logic at 4.5V, while permitting operation with a standard +5.0VDC supply.

  • Page 25: The Syst Em Cloc K

    68000 Motherboard User’s Manual Rev. A Table 8: Indicators Name Color Indication Power White +5V system power present Halt 68000 /HALT signal is asserted Reset Yellow 68000 /RESET signal is asserted Green 68000 is actively addressing, signaling that the microprocessor is running 7.5 The Syst em Cloc k The system clock may be derived from one of several sources, as selected by the System Clock Source Selector, A1JP112.
  • Page 26 68000 Motherboard User’s Manual Rev. A Table 9: Clock Divisor Selector, A1JP110 Clock Divisor Jumper Position Note This setting relies on the D flip-flop to clock during the narrow response of the 4017 RESET. RESET timing may be adjusted with the R119/C119 filter. 9-10 11-12 13-14...

  • Page 27: Exter Nal Run Contr Ol

    25 and 26 of A1CON160/162. Only the /RST_PULSE signal is used by the MB68k-100 circuitry. Internally, this reset pulse is used to latch on- board peripheral write registers to their initial, start-up values. These registers catch the value of the LSB data bus, which has pull-down resistors that dominate during reset.

  • Page 28: The St Art Ve Cto R Sel Ector (Svs)

    68000 Motherboard User’s Manual Rev. A Note the Reset Pulse Generator requires the /RESET signal be asserted for at least one clock period. The Reset Pulse Generator only reflects release of the /RESET signal, not /HALT. Processor execution of the RESET instruction drives only the /RESET line and so triggers generation of a reset pulse.

  • Page 29: Addr Ess S Pace Mapping

    68000 Motherboard User’s Manual Rev. A Cycle when the Data Bus is not driven by the processor, this presents no conflict. The SVS is enabled by the SVS Enable jumper, A1JP181. Note that the SVS loads the 68000’s Supervisor Stack Pointer with the same address as used for the Initial PC as the Reset vector.

  • Page 30: Data Strobed Flow L Ogic

    68000 Motherboard User’s Manual Rev. A 7.10 Data Strobed Flow L ogic The 68000 microprocessor supports a 24-bit address bus but does this with only 23 address lines. Because its data bus width is 16-bit, two 8-bit devices may be serviced simultaneously in a bus cycle.

  • Page 31: Bus Termination Wit H Aut O /Dtack

    Selector, A1JP330, specifies the timeout period in clock cycles. The Bus Error Timer Enable, A1JP331, enables the Bus Error Timer. For reference, see the section on Bus Error Operation of the Motorola 68000 User’s Manual for further detail on the Bus Error exception.

  • Page 32: Wa It State Gen Era Tor

    7.12 On- Board Per ipher als Several on-board peripherals are included in the MB68k-100 design. The address space for these peripherals, denoted as ONBD_BASE, may be selected via the On-Board Block Address Selector, A1JP280. It may be mapped to any of the eight address blocks but is typically located within Block Address 0.

  • Page 33: Int Errupt E Nable Regist Er

    68000 Motherboard User’s Manual Rev. A Table 14: On-Board Register Summary ONBD_BASE Peripheral Name Quick Description +offset Interrupt Enable Register, +$A0000 $00 Interrupt Logic control A1CON340 Clock Synchronization +$C0000 Input signals Register synchronized to clock On-Board Interrupt Logic Level $07 On-Board Interrupt Logic Level Hardware Entropy Generator XX Hardware Entropy...

  • Page 34: On-Board Interrupt Logic Level

    68000 Motherboard User’s Manual Rev. A parallel groups of bits. If an external asynchronous transition straddles a positive clock edge, spurious data may result. Writes to this register are ignored, but the write operation is signaled on the TP_WRDECRST_6 test point. Table 15: Clock Synchronization Register Breakdown Bits Description...
  • Page 35 Example output of the Hardware Entropy Generator is given below in Table 17 per the high-speed sampling program snippet given in Table 16. The program was executed on MB68k-100 hardware at 10.24MHz microprocessor clock speed, in ambient lighting and at approximately 22°C. Differences observed primarily follow the selection of the particular avalanche diode component.

  • Page 36: On-Board Digital Input Interface

    68000 Motherboard User’s Manual Rev. A Table 17: Sample Output of the Hardware Entropy Generator MB68k-100A, S/N 001 10101010101010101011010101011010101101010111010101101010101010110101010101010101 01010101010101010101010101010101010101010101010101011010101101010110101010101010 10101010101010101010101101101011101010101011010101010101010101010101010101101010 10101010101010110101010101101010110101101010101101011011010110110110101101101101 01010101110101010101010110110101110101010110101011010101010101011101101010101010 11010101101010110101010101101010101101010101011011010101010110101010101010101010 10110111010101010101101101010101010101010101010101010101010101101101011010101101 01010101010101010110110101010101010110101010101010101010101010101010101010111011 01010101010110101101010101010101010110101101011010101101110101010101010101010110 11010101010111010101101011010101010110101010101101011010101011010101010101101011 01101010101011011010110101010101010101010110101010101010101110101010101110101011 01010101101010101011010101011010101010110101101010110101101010101010101101110101 11010010101010101010101010101010101010101011101010101010101101010101010110110101 01101010110101011010101010101110101101101011010101010101010101010110101010101010 10101010101010101011010101010101010101010101010101101010101011010110101010101010 10111010101010101010110101101010101010101010101010111010101010101011010101010101 MB68k-100A, S/N 002 11100001111110000111111000011111100000000000000000001111111111000011111100001111 11000011111111111111111111111110000000000111100000011110000001111000000000000000 00000000001111111111000011111100001111110000000000111111111111111111111111111111 11100000011110000001111000000111111111111111111111111111110000111111000011111100 00111111111111111111111111111111111111111000000111100000011111111111111111111111 11111111111111110000111111000011111100000000001111111111000000000111111111100001...

  • Page 37: On- Board Out Put L Atch

    68000 Motherboard User’s Manual Rev. A Clock Synchronization Register respectively. These pins each have a 10k! pull-down resistance and 0.1µF capacitance to negative. Again it should be noted that multi-bit data changes among parallel groups of bits may result in spurious data being latched, if the change event straddles a positive clock edge. This occurs if some, but not all, of the parallel bits are established to their new states at the time of the clock transition.

  • Page 38: On-Boar D Me Mory Ban Ks 0 /1

    68000 Motherboard User’s Manual Rev. A A1JP340. The maximum hardware latency to the processor is the propagation delay of a 74xx74 and 74xx148 (13+19 ns typ., 25+30 ns max. at 25°C), plus one clock cycle. The interrupt event latch may be cleared in software by disabling the corresponding enable bit.

  • Page 39: Stack Int Erf Ac E

    7.15.1 Stack Int erf ac e Connectors The MB68k-100 offers two 0.1" pitch headers, each with 2x32 pins, that may be used to interface with a stack of mezzanine daughter boards. The connectors have reference designators CON160 and CON161. The connectors are positioned on opposite sides of the motherboard, parallel along their long dimensions.
  • Page 40 68000 Motherboard User’s Manual Rev. A M68K_VMA 68000 Valid M68K_E 68000 Enable (E) Memory Address Clock M68K_VPA 68000 Valid M68K_BERR !!!! 68000 Bus Error Peripheral Address M68K_ IPL2 !!!! 68000 Interrupt M68K_ IPL1 !!!! 68000 Interrupt Priority Level, bit Priority Level, bit 1 M68K_ IPL0 !!!! 68000 Interrupt...

  • Page 41: Mount Ing Holes

    7.15.2 Mount ing Holes The motherboard also offers ten mounting holes for securing the MB68k-100 motherboard, as well as any mezzanine boards installed. These mounting holes have an inner diameter of 0.126" (3.2mm). Their positions are shown in Figure 12. Suitable mounting hardware is listed in Table 21 below.
  • Page 42 68000 Motherboard User’s Manual Rev. A Figure 12: Mounting Hole Positions Table 21: Mounting Hardware Options Item Type Item Detail Manufacturer Manu. P/N Distributor Dist. P/N Standoff, 4/40, .600", Keystone 4799 Digi-Key 4799K-ND PC/104 M/F, Hex, Electronics Nylon Standoff, 4/40, .600", Keystone 8799 Digi-Key...

  • Page 43: Quick Jumper Ref Erenc E

    68000 Motherboard User’s Manual Rev. A 7.16 Quick Jumper Ref erenc e The asterisk denotes default jumper position. Jumper Ref. Jumper Name Description Des. Position Jumper Position Description A1JP110 Clock Divisor Selects Clock Frequency Divider rate Selector Pos 1 Divide by 2 Pos 2 Divide by 4 Pos 3...
  • Page 44 68000 Motherboard User’s Manual Rev. A A1JP180 Start Vector Address Presents byte value for reads of addresses 1 and Selector 5 for specifying initial start address for execution and supervisor stack pointer Pos 1 Initial SSP/PC bit 16 Pos 2* Initial SSP/PC bit 17 (0x00020000 for on-board...
  • Page 45 68000 Motherboard User’s Manual Rev. A Pos 3 Block Address 2, /CS2 Pos 4 Block Address 3, /CS3 Pos 5 Block Address 4, /CS4 Pos 6 Block Address 5, /CS5 Pos 7 Block Address 6, /CS6 Pos 8 Block Address 7, /CS7 A1JP290 Digital Output Light Enables light bar to display output latch state...

  • Page 46: The Soft Er Si De

    8.1 Softw are Development Tools Being based on the 68000 processor, a wide range of tools is freely available for software development of the MB68k-100. Among them are the following. 8.1.1 m68k- elf m68k-elf is a development suite for command line software development under Linux, Cygwin and other environments.

  • Page 47: Easy68K

    68000 assembly code. It requires a Windows platform computer. Its tools allow for the generation of Motorola S-Record output files. These files may then be used to generate split binary files for the even and odd program memory ROMs.
  • Page 48 68000 Motherboard User’s Manual Rev. A Loop again if the fill length has not yet been reached. BLOCKFILLB_LONGLOOP Because the lower 16-bits were accommodated above, this covers the entire 32-bit length counter. BLOCKFILLB_RTS: Label for the exit point of the routine. Terminate execution of the routine by returning to the calling parent.
  • Page 49 68000 Motherboard User’s Manual Rev. A within D2. MOVE.B D1, D2 Move the fill byte value into the lower byte of the lower word, from where it had just been shifted. The lower word now contains the fill byte value in both the upper and lower byte positions.

  • Page 50: Sof T War E Note S On The Mb6 8K -100

    68000 Motherboard User’s Manual Rev. A BLOCKFILLB_RTS(PC,D0.W) the remainder index. The remainder count has determined the number of instructions up from the exit point to pass execution. MOVE.B D1, (A0)+ Jump target for 3 remaining bytes to transfer. MOVE.B D1, (A0)+ Jump target for 2 remaining bytes to transfer.

  • Page 51: Gettin G Started

    68000 Motherboard User’s Manual Rev. A Getti ng St arted The basic steps to getting started are as follows: 1. Install the jumpers. Jumper functions are described above in section 7, Circuit Description. See section 7.16, Quick Jumper Reference, for quick reference. 2.

  • Page 52: Troubleshooting

    68000 Motherboard User’s Manual Rev. A 10 Troubl eshooti ng Experience dictates… Symptom Action Halt and Reset LEDs remain illuminated Ensure sufficient input voltage is applied to allow the Discrete Voltage Supervisor to release the system from reset. Vcc should measure as +5VDC and a +4.90V typical absolute minimum relative to GND.
  • Page 53 68000 Motherboard User’s Manual Rev. A old values. It is intended that input data not change during the latching clock edge. 4. The Hardware Entropy Generator operates open loop. A more refined design might use a feedback control scheme to assure the operation of the entropy device in its chaotic region, while also being careful to preserve the random character of the output.

  • Page 54: Project Document Com Pendium

    Document defining MB68k-100 project’s Configuration controlled documentation tree MB68k-100, x MB68k-100 Schematic MB68k-100 Layout MB68k-100, x - Manufacturing MB68k-100 Manufacturing Data Data 68000 Motherboard BOM MB68k-100 Parts List MB68k-100 Motherboard MB68k-100 Assembly Procedure Assembly Procedure MB68k-100 Motherboard Test MB68k-100 Test Procedure...

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