Ddr3 Sdram Test By Nios Ii - Terasic TR5 User Manual

6.3 DDR3 SDRAM Test by Nios II

Many applications use a high performance RAM, such as a DDR3 SDRAM, to provide temporary
storage. In this demonstration hardware and software designs are provided to illustrate how to perform
DDR3 memory access in QSYS. We describe how Altera's "DDR3 SDRAM Controller with UniPHY"
IP is used to access the DDR3-Sodimm on the FPGA board, and how the Nios II processor is used to
read and write the SDRAM for hardware verification. The DDR3 SDRAM controller handles the
complex aspects of using DDR3 SDRAM by initializing the memory devices, managing the SDRAM
banks, and keeping the devices refreshed at appropriate intervals.
 System Block Diagram
Figure 6-4 shows the system block diagram of this demonstration. The QSYS system requires one
50 MHz clock source provided from the board. The DDR3 controller is configured as a 2 GB DDR3-
800Mhz controller. The DDR3 IP generates one 800 MHz clock as SDRAM's data clock and one
quarter-rate system clock 800/4=200 MHz for those host controllers, e.g. Nios II processor, accessing
the SDRAM. In the QSYS, Nios II and the On-Chip memory are designed running with the 200 MHz
clock, and the Nios II program is running in the on-chip memory. A PIO Controller is used to monitor
buttons status which is used to trigger starting memory testing.
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TR5 User Manual www.terasic.com
July 27, 2017