JVC RX-E112RSL Service Manual page 18

RX-E112RSL/RX-E111RSL
TC9446F-025 (IC631) : Audio digital processor
1. Block diagram
Program
Instruction
control
IRQ
Interrupt
2
SDIn
4
Audio
SDOn
Interface
LRCK/BCK
RX DIR
LOCK
RST
MIMD
MICS Timer
MILP
MIDIO
MCU interface
MICK
MIACK
2. Pin function
Pin No. Symbol I/O Function
1 RST I Reset signal input terminal
(L:reset H:nomal operation)
2 MIMD I Mode select input for MCU interface
(L:serial H:IC bus)
3 MICS I Chip select input for MCU interface
4 MILP I Latch pulse input for MCU interface
5 MIDIO I/O Data I/O for MCU interface
6 MICK I Clock input for MCU interface
7 MIACK O Acknowledge output for MCU interface
8~11 FI0~3 I Flag input 0~3
12 IRQ I Interrupt input
13 VSS - Digital ground
14 LRCKA I LR clock input-A for audio interface
15 BCKA I Bit clock input-A for audio interface
16~19 SDO0~3 O Data output-0~3 for audio interface
20 LRCKB I LR clock input-B for audio interface
21 BCKB I Bit clock input-B for audio interface
22, 23 SDI0, 1 I Data input-0, 1 for audio interface
24 VDD - Digital power supply
25 LRCKOA O LR clock output-A for audio interface
26 BCKOA O Bit clock output-A for audio interface
27, 28 TEST0,1 I Test input-0, 1 (L:test H:nomal operation)
29 LRCKOB O LR clock output-B for audio interface
30 BCKOB O Bit clock output-B for audio interface
31 TXO O SPDIF output
32,33 TEST2,3 I Test input-2, 3 (L:test H:nomal operation)
34 RX I SPDIF input
35 VSS - Digital ground
36 TSTSUB0 I Test sub input-0 (L:test H:nomal operation)
37 FCONT O Frequency control output for VCO circuit
38 TSTSUB1 I Test sub input-1, 2
39 TSTSUB2 (L:test H:nomal operation)
40 PDO O Phase detect signal output
1-18
Program
ROM
4k word x3
XRAM
YRAM
4k word
4k word
RAM
128 word
40 bit
X bus
Instruction
Detector
Y bus
Register
1 bus
X0, X1, X2
Y0, Y2, Y3
MX
A1
Round/Limiter
Address Operater
ERAM
CROM
X pointer
4k word
4k word
register
MY MZ AX AY
MAC ALU
A0 A2 A3
Round/Limiter
Pin No. Symbol I/O
41 VDDA
42 PLON
43 AMPI
44 AMPO
45 CKI
46 VSSA
47 CKO
48 LOCK
49 VSS
50 WR
51 OE
52 CE
53 VDD
54~61 IO7~0 I/O
62 VSS
63~70 AD0~7
71 VDD
72~80 AD8~16
81 VSS
82~89 PO0~7
90 VDDDL
91 LPFO
92 DLON
93 DLCKS
94 SCKO
95 VSSDL
96 SCKI
97 VSSX
98, 99 XO,XI I/O
100 VDDX
Timing
x2
DLL
Y pointer
C pointer
register
register
Bus switch
External SRAM
interface
General output
port
Flag
DIT
Function
- Analog power supply
I Clock selection input
(L:external clock H:VCO clock)
I AMP.input for LPF
O AMP.output for LPF
I External clock input
- Analog ground
O DIR clock output
O VCO lock output
- Gigtal ground
O Writing signal output for extrenal SRAM
O Enable signal output for external SRAM
O Chip enable signal output for external SRAM
- Digital power supply
Data I/O-7~0 for external SRAM
- Digital ground
O Address output-0~7 for external SRAM
- Digital power supply
O Address output-8~16 for external SRAM
- Digital ground
O General output port-0~7
- Power supply for DLL circuit
O LPF output for DLL circuit
I *
O ASP clock output
- Ground for DLL circuit
I External system clock input
- Ground for crysoal oscillator
Crystal oscillator I/O
- Digital power supply
*
DLCKS pin DLON pin DLL clock setting
L L SCKI input (DLL circuit OFF)
L H Four times XI clock
H L Three times XI clock
H H Six times XI clock
SCKO
SCKI
DLON
LPFO
3
CE, OE, WR
17
ADn
8
IOn
8
POn
4
FIn
TXO