Table of Contents
Advertisement
S1R72104 Technical Manual
6. FUNCTIONAL DESCRIPTION
6.1 CPU Interface Circuit
This block can be interfaced to a general-purpose CPU. It controls the interface with the CPU generally.
If XCS signal from CPU is LOW, the block can access the internal register. It decodes the address bus AD4 to
AD0 to generate the address of the internal register. At this time, it generates the read/write strobe signal from
XRD/XWR signal, transferring data between the internal register. A wait signal to CPU is not generated
because of no-wait operation.
6.2 Internal Registers
Refer to the section of Register Functions as for the addresses of the internal registers and description of each
bit. The main functions of this block are as follows:
(1) It generates control signals to each block according to the address, write-data and write-strobe signals
generated by the CPU interface circuit.
(2) It stores the status signals from each block, and outputs data according to the address and read-strobe
signals sent from the CPU interface circuit.
6.3 Port Interface Circuit
This is a block controlling the transfer to and from the external DMA port. It has the following functions:
(1)
It controls the linkage operation of each functional block according to the control signal and the
stop-operation signal sent from the DMA control circuit.
(2) It control the transfer status of the external port according to PDREQ/XPDACK signals.
(3) It reads/writes the data of the data bus PD15-0 of the port from/to FIFO in SCSI-2 block. If the transfer
becomes impossible because of FIFO's full/empty state, the block suspends transfer to and from the port
according to the timing specified by the PDREQ/XPDACK signals.
(4) The port allows selection of bit width 8 or 16.
(5) The port interface allows selection of the master or slave function (toward PDREQ/XPDACK/XPRD/XPWR
direction).
6.4 DMA Control Circuit
This is a block which controls the transfer between DMA port and FIFO in SCSI-2 block. It has the following
functions:
(1) It controls the linkage operation of each functional block according to the control signal from the internal
register and the information and stop-operation signals from each block.
(2) It stores the status of each of functional blocks when their linkage operation ends, reporting it to the
internal register at the specified timing.
6.5 SCSI-2 Interface Circuit
This is a block which controls the interfaces conforming to the SCSI-2 standard in general. It has the
following functions:
(1) It performs the SCSI protocol control automatically with hardware.
(2) It has 16-staged off-set counter to control the off-set and transfer rate during synchronous transfer.
(3) In the command phase, it distinguishes automatically the groups of commands received (in Target mode).
(4) It controls the automatic status/message transfer function. It supports the messages 00h/0Ah/0Bh (in
Target mode).
SCAM compatibility
Besides the traditional SCSI, this LSI has some additional functions compatible to SCAM (SCSI Configured
Auto Magnify) as listed below. .
These functions allow a device to operate as a SCAM Lv.1 drive.
(1) It monitors and recognizes SCAM selection and generates interruption.
(2) It responds to the selection response delay of 4ms or more, so it can distinguish SCAM selection from
ordinary selection.
(3) It can operate SCSI bus's signal line directly because of its actual operation responding to SCAM selection
and sending/receiving data.
6
EPSON
Rev.1.1
Advertisement
Table of Contents
