Internal Block Diagram; Functional Block Descriptions; Bus Signal Translation; Control Registers - Epson SED1352 Technical Manual

Epson Research and Development
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3.2 Internal Block Diagram

IOR#, IOW#, IOCS#,
MEMCS#, MEMR#,
MEMW#, BHE#,
AB[19:0]
Bus
Signal
Translation
READY
DB[15:0]

3.3 Functional Block Descriptions

3.3.1 Bus Signal Translation

According to configuration setting VD2, Bus Signal Translation translates MC68000 type CPU signals or READY type
MPU signals to internal bus interface signals.

3.3.2 Control Registers

The fifteen internal Control and Configuration Registers are accessed by direct-mapping or by using the built-in internal
index register.

3.3.3 Sequence Controller

The Sequence Controller generates horizontal and vertical display timings according to the configuration registers
settings.

3.3.4 LCD Panel Interface

The LCD Interface performs frame rate modulation for passive monochrome LCD panels.
Hardware Functional Specification
Issue Date: 99/07/28
Port
Decoder
Memory
Decoder
Data Bus
Conversion
Timing Generator
Power Save
Oscillator

Figure 6: Internal Block Diagram

Control Registers
Sequence
Controller
Look-Up
Address
Generator
Display
Data
CPU/CRT
Formatter
Selector
SRAM Interface
LCDENB
UD[3:0]
LCD
Table LD[3:0]
Panel
LP, YD,
Interface
WF,
XSCL
SED1352
X16-SP-001-16
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