Pioneer MJ-L5 Service Manual page 61

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PD5450B (MD CORE MAIN UNIT : IC104)
• Mechanism Control microcomputer
•
Pin Assignment (Top View)
TE
L 13942296513
•
Block Diagram
I/O PORT
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8 8
Port P0 Port P1 Port P2
Internal Peripheral
A/D Converter
Functions
(10bits × 8 channels)
(expansion to 10 channels possible)
TIMER
Timer TA0 (16bits)
UART/clock-synchronized SI/O
Timer TA1 (16bits) (8bits × 2 channels)
Timer TA2 (16bits)
Timer TA3 (16bits)
CHC operation circuit
Timer TA4 (16bits)
(CCITT method)
Timer TB0 (16bits)
(formation polynomial: X
Timer TB1 (16bits)
Timer TB2 (16bits)
16 bits CPU CORE
Monitoring timer
Register
(16 bits)
R0H
R1H
DMAC (2 channels) R2
R3
A0
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D/A Converter
A1
(8bits× 2 channels)
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2 9
8
Q Q
3 6 7 1 3 1 5
8 8 8
Port P3 Port P4
System clock generation
XIN – XOUT
XCIN – XCOUT
16 12 5
+ X + X + 1)
MEMORY
Stack Pointer
R0L ISP
R1L USP
Vector Table
INTB
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Analog Multiplier
MJ-L5, SP-L5
9 4 2 8
0 5 8 2 9 9 4 2 8
8 8
Port P5 Port P6
ROM
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RAM
10k bite
9 9
9 9
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