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NXP Semiconductors LPC43Sxx User Manual

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UM10503

LPC43xx/LPC43Sxx ARM Cortex-M4/M0 multi-core

microcontroller

Rev. 2.1 — 10 December 2015

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Keywords

LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310,

LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323,

LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, LPC43S50, LPC43S30,

LPC43S20, LPC43S37, LPC43S57, LPC43S67, LPC4367, LPC43S70, ARM

Cortex-M4, ARM Cortex-M0, SPIFI, SCTimer/PWM, USB, Ethernet,

LPC4300 user manual, LPC43xx/LPC43Sxx user manual

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LPC4300/LPC43S00 user manual

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Summary of Contents for NXP Semiconductors LPC43Sxx

Page 1 LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310, LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323, LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, LPC43S50, LPC43S30, LPC43S20, LPC43S37, LPC43S57, LPC43S67, LPC4367, LPC43S70, ARM Cortex-M4, ARM Cortex-M0, SPIFI, SCTimer/PWM, USB, Ethernet, LPC4300 user manual, LPC43xx/LPC43Sxx user manual Abstract LPC4300/LPC43S00 user manual...
Page 2 Added block diagram of LPC436x/LPC43S6x. See Figure 5 “LPC436x/LPC43S6x block diagram (parts with on-chip flash, dual-core)” • Updated Table 10 “LPC43xx/LPC43Sxx SRAM configuration” to add LPC436x and LPC43S6x parts. • Updated Figure 10 “Parts with on-chip flash: Memory mapping (overview)”.
Page 3 UM10503 NXP Semiconductors LPC43xx/LPC43Sxx User manual Revision history …continued Date Description • Updated Figure 24 “IAP parameter passing”. • Updated Figure 27 “Boot flow for encrypted images (flashless parts)”. • Removed tge GPCLEAR_ENx bits from the register description. See Table 917 “Event Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description”.
Page 4 • IRC accuracy corrected in Section 1.2 “Features”. • Added text: The secure boot from USART3 is not supported for LPC43Sxx parts: see Section 5.1, Section 7.1, Table 21, and Table 22. UM10503 All information provided in this document is subject to legal disclaimers.
Page 5 UM10503 NXP Semiconductors LPC43xx/LPC43Sxx User manual Revision history …continued Date Description • Modifications: Section 1.7 “ARM core features” added. • ARM Cortex-M0 debug features added. See Section 51.3. • Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 447 “SPIFI control register (CTRL, address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in...
Page 6 UM10503 NXP Semiconductors LPC43xx/LPC43Sxx User manual Revision history …continued Date Description 20140128 LPC43xx User manual • Modifications: Description of the C_CAN CLKDIV register corrected. See Table 1073. • Priorities of the EMC SDRAM ports added. See Section 22.4. • Table 20 “OTP function allocation” corrected.
Page 7 UM10503 NXP Semiconductors LPC43xx/LPC43Sxx User manual Revision history …continued Date Description 20131017 LPC43xx User manual • Modifications: 12-bit ADC (ADCHS) for parts LPC4370 added. See Chapter 47. • Table “LPC43xx part identification numbers” updated. • BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter 12 “LPC43xx Clock Generation Unit (CGU)”, Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration...
Page 8 UM10503 NXP Semiconductors LPC43xx/LPC43Sxx User manual Revision history …continued Date Description • Modifications: LPC4320 and LPC4310 part IDs corrected. See Table 45 “LPC43xx part identification numbers” and the LPC4350/30/20/10 errata sheet. • Description of word1 of the part id corrected. See Table 45 “LPC43xx part identification numbers”.
Page 9 UM10503 NXP Semiconductors LPC43xx/LPC43Sxx User manual Revision history …continued Date Description 20121203 LPC43xx user manual. • Modifications Statement regarding the connection between sampling pin P2_7 and the watchdog timer overflow bit is incorrect and was removed in Section “Sampling of pin P2_7” and Figure “Boot process flowchart for LPC43xx parts with flash”.
Page 10 UM10503 NXP Semiconductors Chapter : Revision history …continued Date Description • Modifications: ETM time stamping feature not implemented. • Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section “Determine the cause of a core reset” added. • Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver and API.
Page 11 Section “Susp_CTRL module” added for USB1. • Section “USB power optimization” updated. • Table “Boot image header use” added. • AES only available for LPC43Sxx parts. • Bank, Row, Column addressing for SDRAM devices added. • Parts LPC4337 and LPC4333 added. 20120608 LPC43xx user manual.
Page 12 Changed maximum clock frequency for SWD and ETB access to 120 MHz. • Reduced and normal power modes removed. • AES encryption option added (parts LPC43Sxx only). • SGPIO register names and descriptions updated. • Update description of bit 0 in the USBSTS_D and bit 5:0 in ENDPTCOMPLETE registers of USB0/1.
Page 13 (SCTimer/PWM) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. The LPC43xx/LPC43Sxx operate at CPU frequencies of up to 204 MHz. The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
Page 14 UM10503 NXP Semiconductors Chapter 1: Introductory information – ARM Cortex-M0 processor (version r0p0) capable of off-loading the main ARM Cortex-M4 processor. – Running at frequencies of up to 204 MHz. – JTAG and built-in NVIC. • Cortex-M0 Processor subsystem core (LPC437x/LPC43S7x and LPC436x/LPC43S6x parts only) –...
Page 15 UM10503 NXP Semiconductors Chapter 1: Introductory information – One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY. – One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.
Page 16 – One 6-channel, 12-bit high-speed ADC (ADCHS) with DMA support and a data conversion rate of 80 MSamples/s (LPC4370 only). • Security (LPC43Sxx only) – AES decryption programmable through an on-chip API. – Two 128-bit secure OTP memories for AES key storage and customer use.
Page 17 UM10503 NXP Semiconductors Chapter 1: Introductory information 1.3 Ordering information (flashless parts) Table 1. Ordering information Type number Package Name Description Version Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm LPC4370FET256 LBGA256 SOT740-2 TFBGA100 Plastic thin fine-pitch ball grid array package;...
Page 18 UM10503 NXP Semiconductors Chapter 1: Introductory information Table 2. Ordering options Type number Total Cores Ethernet USB0 USB1 10-bit 12-bit GPIO SRAM (Host, (Host, Device, Device)/ channels channels OTG) ULPI (ADCHS) interface LPC4310FET100 168 kB M4/M0 LPC4310FBD144 168 kB M4/M0...
Page 19 UM10503 NXP Semiconductors Chapter 1: Introductory information Table 3. Ordering information …continued Type number Package Name Description Version TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC4325JET100 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm...
Page 20 UM10503 NXP Semiconductors Chapter 1: Introductory information Table 4. Ordering options LPC4337JET256 1 MB 512 kB 512 kB 136 kB yes/yes yes LPC4337JBD144 1 MB 512 kB 512 kB 136 kB yes/no LPC4337JET100 1 MB 512 kB 512 kB 136 kB...
Page 21 INTERRUPT GPIO GROUP1 INTERRUPT = connected to GPDMA 002aaf772-x AES is supported for LPC43Sxx parts only. Fig 1. LPC4350/30/20/10 Block diagram (flashless parts, dual-core) UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Page 22 UM10503 NXP Semiconductors Chapter 1: Introductory information slaves LPC4370 SUBSYSTEM AHB MULTILAYER MATRIX system masters 2 kB LOCAL SRAM 16 kB LOCAL SRAM CORTEX-M0 SUBSYSTEM SGPIO TEST/DEBUG INTERFACE CORE-CORE BRIDGE TEST/DEBUG INTERFACE TEST/DEBUG HIGH-SPEED PHY INTERFACE CORTEX-M4 ETHERNET HIGH-SPEED HIGH-SPEED...
Page 23 UM10503 NXP Semiconductors Chapter 1: Introductory information slaves LPC43S70 SUBSYSTEM AHB MULTILAYER MATRIX system masters 2 kB LOCAL SRAM 16 kB LOCAL SRAM CORTEX-M0 SUBSYSTEM SGPIO TEST/DEBUG INTERFACE CORE-CORE BRIDGE TEST/DEBUG INTERFACE TEST/DEBUG HIGH-SPEED PHY INTERFACE CORTEX-M4 ETHERNET HIGH-SPEED HIGH-SPEED...
Page 24 GPIO GROUP1 INTERRUPT = connected to DMA 002aah234-x AES is supported for parts LPC43Sxx only. LCD on parts LPC4357/53 only. Fig 4. LPC43xx block diagram (parts with on-chip flash, dual-core) UM10503 All information provided in this document is subject to legal disclaimers.
Page 25 UM10503 NXP Semiconductors Chapter 1: Introductory information LPC436x/43S6x slaves AHB MULTILAYER MATRIX system masters 2 kB LOCAL SRAM 16 kB LOCAL SRAM CORTEX-M0 SUBSYSTEM SGPIO TEST/DEBUG INTERFACE CORE-CORE TEST/DEBUG BRIDGE INTERFACE TEST/DEBUG INTERFACE CORTEX-M0 APPLICATION HIGH-SPEED PHY CORTEX-M4 ETHERNET HIGH-SPEED...
Page 26 UM10503 NXP Semiconductors Chapter 1: Introductory information 1.7 ARM core features 1.7.1 ARM Cortex-M4 processor The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching.
Page 27 Rev. 2.1 — 10 December 2015 User manual 2.1 How to read this chapter The ARM Cortex-M0APP processor is available on all LPC43xx/LPC43Sxx parts. The ARM Cortex-M0SUB subsystem core is only available on parts LPC437x/LPC43S7x and LPC436x/LPC43S6x parts only. 2.2 Basic configuration The ARM Cortex-M0 processor(M0APP) is configured as follows: •...
Page 28 Multi-core connections 2.3 Introduction The LPC43xx/LPC43Sxx is a multi-core microcontroller implementing an ARM Cortex-M4 and one or two ARM Cortex-M0 cores. All cores have access to the complete memory map. The ARM Cortex-M4 is used as them main processor. One ARM Cortex-M0core (M0APP) can be used as co-processor to off-load the ARM Cortex-M4 and to perform serial I/O tasks.
Page 29 UM10503 NXP Semiconductors Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and Interrupt Write Pointer Read CMD_BUFFER Pointer Cortex M4 Cortex M0 (Master) (Slave) Write Pointer MSG_BUFFER Read Pointer Interrupt = M0 subsystem = M4 subsystem = shared Fig 7. Dual-core block diagram 2.4.1 Hardware...
Page 30 UM10503 NXP Semiconductors Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and 2.5 IPC Protocol implementation example The IPC supports low-level interfaces, e.g. a register level interface, but can also be implemented as a higher level API. The ARM Cortex-M4 host CPU is the master in this example. It initiates commands to the ARM Cortex-M0 that mimic a hardware register level interface.
Page 31 UM10503 NXP Semiconductors Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and The command queue is filled by the ARM Cortex-M4 and emptied by the ARM Cortex-M0; the write pointer is advanced by the ARM Cortex-M4 every time it adds a new command to the queue.
Page 32 UM10503 NXP Semiconductors Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and Small data transfers can be performed by the single 32-bit data read, CMD_RD_ID, and write, CMD_WR_ID, commands. These commands use a 3-Byte addressing scheme to support an argument space of 212 = 4096 32-bit words. Large data transfers can be more efficiently handled using pointers.
Page 33 UM10503 NXP Semiconductors Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and 2.5.3 Example Assume that a certain task with ID 0x1234 should be executed by the ARM Cortex-M0. For example, read data from a register level interface controlled by the ARM Cortex-M0.
Page 34 3.3 Memory configuration 3.3.1 On-chip static RAM The LPC43xx/LPC43Sxx support up to 282 kB SRAM on flashless parts or up to 136 kB on parts with on-chip flash with separate bus master access for higher throughput and individual power control for low power operation (see Figure 12).
Page 35 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping Table 10. LPC43xx/LPC43Sxx SRAM configuration Part Local SRAM Local SRAM AHB SRAM AHB SRAM AHB SRAM/ subsystem ETB SRAM SRAM LPC4370 128 kB 72 kB 16 + 2 kB 32 kB 16 kB...
Page 36 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping Remark: Although the EEPROM is mapped in a bit-banding capable region, attempts to write access the EEPROM in the bit-banding aliased memory space will not result in a bit write 3.3.3 On-chip flash...
Page 37 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping 3.3.6 Memory Protection Unit (MPU) The MPU is a integral part of the ARM Cortex-M4 for memory protection and supported by all LPC43xx parts. The processor supports the standard ARMv7 Protected Memory System Architecture model.
Page 38 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping 3.4 Memory map (flashless parts) LPC4370/50/30/20/10 LPC43S70/S50/S30/S20 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3...
Page 39 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC4370/50/30/20/10/S70/S30/S20 0x400F 0000 reserved 0x400E 5000 0xFFFF FFFF APB3 ADC1 0x400E 4000 external memories and peripherals ARM private bus ADC0...
Page 40 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping 3.5 Memory map (parts with on-chip flash) The memory map shown in Figure 10 Figure 11 is global to both the Cortex-M4 and the Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between both processors.
Page 41 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 128 MB SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3 0x7000 0000 256 MB dynamic external memory DYCS2...
Page 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC436x/5x/3x/2x/1x/S6x/S5x/S3x 0x400F 0000 0x4006 0000 reserved 0x400E 5000 0xFFFF FFFF reserved 0x4005 4000 APB3 ADC1 0x400E 4000 external memories and...
Page 43 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping 3.6 AHB Multilayer matrix configuration The multilayer AHB matrix enables all bus masters to access any embedded memory as well as external SPI flash memory connected to the SPIFI interface. When two or more bus masters try to access the same slave, a round robin arbitration scheme is used;...
Page 44 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping TEST/DEBUG INTERFACE CORTEX-M0 SUBSYSTEM master BRIDGE TEST/DEBUG TEST/DEBUG INTERFACE HIGH-- INTERFACE slaves SPEED ETHERNET USB1 masters 2 kB SRAM CORTEX-M0 USB0 CORTEX-M4 APPLICATION 16 kB SRAM System code code SGPIO BRIDGE slaves...
Page 45 UM10503 NXP Semiconductors Chapter 3: LPC43xx/LPC43Sxx Memory mapping TEST/DEBUG INTERFACE CORTEX-M0 SUBSYSTEM master BRIDGE TEST/DEBUG TEST/DEBUG INTERFACE slaves INTERFACE HIGH-- SPEED 2 kB SRAM masters ETHERNET USB1 CORTEX-M0 CORTEX-M4 16 kB SRAM APPLICATION USB0 System code code SGPIO BRIDGE slaves...
Page 46 (OTP) memory and API Rev. 2.1 — 10 December 2015 User manual 4.1 How to read this chapter This chapter applies to all LPC43xx/LPC43Sxx parts with the following exceptions:. • AES keys and AES functions are supported for parts LPC43Sxx only. •...
Page 47 UM10503 NXP Semiconductors Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) The virgin OTP state is all zeros. A zero value can be overwritten by a one, but a one in any of the OTP bits cannot be changed. Programming the OTP requires a higher voltage than reading. The read voltage is generated internally.
Page 48 UM10503 NXP Semiconductors Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) Table 14. OTP memory description (OTP base address 0x4004 5000) Word Access Address Size Description Reference bank offset User programmable; initial 0x010 32 bit General purpose OTP memory 0, word 0, or...
Page 49 UM10503 NXP Semiconductors Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) Table 15. OTP memory bank 3, word 0 - Customer control data (address offset 0x030) Symbol Value Description 28:25 BOOT_SRC Boot source selection in OTP. For details, see Table 0000 External pins...
Page 50 UM10503 NXP Semiconductors Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) Ptr to ROM Driver table 0x1040 0100 Device 0 ROM Driver Table Ptr to Function 0 Ptr to Device Table 0 Ptr to Function 1 +0x04 Ptr to Function 2 Ptr to OTP driver table +0x08 …...
Page 51 UM10503 NXP Semiconductors Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) 4.5.1 OTP function allocation Remark: See Section 4.1 for availability of OTP functions for different boot ROM versions. Table 20. OTP function allocation Function Offset Description OTP bank OTP memory programmed...
Page 52 UM10503 NXP Semiconductors Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP) Table 20. OTP function allocation Function Offset Description OTP bank OTP memory programmed name otp_ProgGP2_0 0x20 Programs the general purpose OTP memory GP2 word 0. 3 (word 1) General Use for customer-specific data. The data parameter is one purpose 32-bit word.
Page 53 Rev. 2.1 — 10 December 2015 User manual 5.1 How to read this chapter This chapter applies to all parts. AES support is available on LPC43Sxx parts only. See Chapter 7 “LPC43Sxx Boot ROM for secure parts”. Flash-based parts boot from on-chip flash by default (see...
Page 54 P2_3 and P2_4. For flash parts, enter UART ISP mode. The secure boot from USART3 is not supported for LPC43Sxx parts. The boot loader programs the appropriate pin function at reset to boot using SSP0. Remark: Pin functions for SPIFI and SSP0 boot are different.
Page 55 Boot from device connected to USART3 using pins P2_3 and P2_4. For flash parts, enter UART ISP mode. The secure boot from USART3 is not supported for LPC43Sxx parts. The boot loader programs the appropriate pin function at reset to boot from SPIFI or SSP0.
Page 56 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM RESET INITIALIZE CRP1/2/3 ENABLED? ENABLE DEBUG USER CODE VALID in FLASH BANK A? CRP3 ENABLED? USER CODE VALID in FLASH Enter ISP BANK B? USER CODE VALID? MODE? (P2_7=LOW) EXECUTE INTERNAL USER CODE...
Page 57 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM should be compiled with entry point at 0x0000 0000. On AES capable parts with a programmed AES key, the image and header are authenticated using the CMAC algorithm prior to copying to the internal SRAM. If authentication fails the device is reset.
Page 58 = 0x1000 0000, = 0x1000 0000, = boot address, For details on secure booting using the AES engine, see Chapter 7 “LPC43Sxx Boot ROM for secure parts”. Fig 16. Boot process for parts without flash UM10503 All information provided in this document is subject to legal disclaimers.
Page 59 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM 5.3.3 Boot image header format Non-AES capable products may boot from an image with header or execute directly from the boot source if the boot source is memory mapped (see Table 23). When no valid header is found, then the CPU will try to execute code from the first location of the memory mapped boot source.
Page 60 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM 5.3.4 Boot modes 5.3.4.1 UART boot mode Figure 17 details the boot-flow steps of the UART boot mode. The execution of this mode occurs only if the boot mode is set accordingly (see boot modes...
Page 61 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Setup Pin Init UART assuming Configuration PCLK =12MHz UART0 P2_1, P2_0 or UART3 P2_3,P2_4 receive character char = 0x3F? transmit receive “OK” CR image transmit valid “FAILED” image? CR LF transmit “OK” CR see main boot flow Fig 17.
Page 62 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Setup Pin Configuration Read Image EMC _A[13:0] Header EMC_CS0 Image size > 16384-16 Extend address bus see main boot flow Fig 18. EMC boot process 5.3.4.3 SPI boot mode The boot uses SSP0 in SPI mode. The SPI clock is 18 MHz.
Page 63 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM If no header is present, it is assumed that the image is located on address 0x8000 0000 and is executed from there. Setup clock Setup Pin SPIFI_SCK= Configuration Detect device 32MHz P3_3..P3_8...
Page 64 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Table 25. QSPI devices supported by the boot code and the SPIFI API Manufacturer Device Comment Spansion S25FL032P1F S25FL064P1F S25FL256SAGMFI001 S25FL129P0XNFI01 Winbond W25Q80BVSSIG, W25Q16DV, W25Q32FV Remark: After booting, include the SPIFI API driver in your firmware image and use it to re-initialize the SPIFI device for best performance.
Page 65 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Boot source? USB0 USB1 Setup clock Setup clock USB_CLK=480MHz USB_CLK=60MHz Enable HS PHY Setup VBUS pin P2_5 enumerate receive image see main boot flow Fig 21. USB boot process 5.3.5 Boot process timing The following parameters describe the timing of the boot process: Table 27.
Page 66 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM IRC12 IRC12 stable starts IRC12 RESET VDDREG valid threshold 22 μs 0.5μs; IRC stability count supply boot time ramp up user code μs μs μs processor status check boot initialise copy image to...
Page 67 UM10503 Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and Rev. 2.1 — 10 December 2015 User manual 6.1 How to read this chapter The flash programming ISP is available for parts with on-chip flash. A reduced set of In-System-Programming (ISP) commands is supported for flashless parts (see Table 34).
Page 68 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP • Flash signature generation: built-in hardware can generate a signature for a range of flash addresses or for the entire flash memory. 6.4 General description The boot loader controls initial operation after reset and also provides the tools for programming the flash memory.
Page 69 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.4.1 Sampling of pin P2_7 Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated, it may take up to 3 ms before P2_7 is sampled and the decision on whether to continue with user code or ISP handler is made.
Page 70 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.4.3 Boot process for parts with internal flash Section 5.3.1 “Boot process for parts with internal flash”. 6.4.4 Memory map after any reset When a user program begins execution after reset, the interrupt vectors are set to point to...
Page 71 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.4.5.3 ISP data format The data stream is in UU-encoded format. The UU-encode algorithm converts 3 B of binary data in to 4 B of printable ASCII character set. It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex.
Page 72 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.5 Sector numbers Some IAP and ISP commands operate on sectors and specify sector numbers. The following table indicates the correspondence between sector numbers and memory addresses for LPC43xx device. IAP and ISP routines are located in the Boot ROM.
Page 73 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.6 Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted.
Page 74 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 33. Code Read Protection hardware/software interaction CRP option User Code P2_7 pin at JTAG enabled LPC43xx partial flash Valid reset enters ISP update in ISP mode mode None High...
Page 75 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 76 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7.2 Set Baud Rate <Baud Rate> <stop bit> The UART PCLK is derived from the IRC at 12 MHz. Table 36. ISP Set Baud Rate command Command Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200...
Page 77 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 38. ISP Write to RAM command Command Input Start Address: RAM address where data bytes are to be written. This address should be a word boundary. Number of Bytes: Number of bytes to be written. Count should be a multiple of 4...
Page 78 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7.6 Prepare sectors for write operation <start sector number> <end sector number> <flash bank> This command is the first step in the two-step flash write/erase operation. Table 40. ISP Prepare sectors for write operation command...
Page 79 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes> Before executing this command, perform the “Prepare sectors for write operation” command. Table 41. ISP Copy command Command...
Page 80 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7.8 Go <address> <mode> Table 42. ISP Go command Command Input Address: Flash or RAM address from which the code execution is to be started. This address must be on a word boundary and it is not allowed to add the Thumb bit (bit 0) of the address.
Page 81 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7.10 Blank check sectors <sector number> <end sector number> <flash bank> Table 44. ISP Blank check sector command Command Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number.
Page 82 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 46. LPC43xx part identification numbers Device Hex coding Word0 Word1 LPC43S30FBD144 0xA000 0A60 0xXXXXXXX00 LPC4320FET100 0xA000 CB3C 0xXXXX XX00 LPC4320FBD144 0xA000 CB3C 0xXXXX XX00 LPC43S20FBD144 A000CB6C 0xXXXXXXX00 LPC43S20FET180 A000CB6C...
Page 83 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 46. LPC43xx part identification numbers Device Hex coding Word0 Word1 LPC4325JET100 0xA001CB3C 0xXXXX XX22 LPC4323JBD144 0xA00BCB3C 0xXXXX XX44 LPC4323JET100 0xA00BCB3C 0xXXXX XX44 LPC4322JBD144 0xA00BCB3C 0xXXXX XX80 LPC4322JET100 0xA00BCB3C 0xXXXX XX80...
Page 84: Return Code Cmd_Success
UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.7.14 Compare <address1> <address2> <no of bytes> Table 49. ISP Compare command Command Input Address1 (DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
Page 85 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 50. ISP Set active boot flash bank command Command Input Flash bank: Selects flash bank A or B for booting if the part supports more than on bank. (0 = flash bank A, 1 = flash bank B).
Page 86 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.8 IAP commands Remark: IAP commands are not supported for flash-less parts. For in-application programming, call the IAP routine with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters.
Page 87 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Command Parameter Array Command code command_param[0] command_param[1] Param 0 Param 1 command_param[2] ARM REGISTER r0 command_param[n] Param n ARM REGISTER r1 Status Result Array Status code status_result[0] Result 0 status_result[1]...
Page 88 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 4. Set the function pointer: IAP iap_entry=(IAP)IAP_LOCATION; 5. Use the following statement to call the IAP: iap_entry (command_param,status_result); The IAP call can be simplified further by using the symbol definition file feature supported by ARM Linker in RVDS (Realview Development Suite).
Page 89 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 52. IAP Initialization command Command Init IAP Result None Description Initializes and prepares the flash for erase and write operations. Stack usage 88 B 6.8.2 Prepare sectors for write operation This command is the first step in the two-step flash write/erase operation.
Page 90: Src_Addr_Error (Address Not On Word Boundary) | Dst_Addr_Error (Address Not On Correct Boundary) | Src_Addr_Not_Mapped
UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 54. IAP Copy RAM to Flash command Command Copy RAM to Flash Input Command code: 51 (decimal) Param0(DST): Destination flash address where data bytes are to be written. This address should be a 512 byte boundary.
Page 91 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.8.5 Blank check sectors Table 56. IAP Blank check sectors command Command Blank check sectors Input Command code: 53 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
Page 92 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 58. IAP Read Boot Code version number command Command Read boot code version number Result Result0: 2 bytes of boot code version number. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>...
Page 93 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.8.10 Re-invoke ISP Table 61. IAP Re-invoke ISP Command Compare Input Command code: 57 (decimal) Status Code None Result None. Description This command is used to invoke the boot loader in ISP mode. It configures UART0 pins U0_RX and U0_TX.
Page 94 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 63. IAP Set active boot flash bank Command Set active boot flash bank Input Command code: 60 (decimal) Param0: Flash bank (0 = flash bank A, 1 = flash bank B).
Page 95 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 64. ISP Status Codes Summary Status Code Mnemonic Description 0x0000 0012 INVALID_STOP_BIT Invalid stop bit setting. 0x0000 0013 CODE_READ_PROTECTION_ Code read protection enabled. ENABLED 0x0000 0014 INVALID_FLASH_UNIT Invalid flash unit.
Page 96 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.11.1.1 Signature generation address and control registers These registers control automatic signature generation. A signature can be generated for any part of the flash memory contents. The address range to be used for generation is defined by writing the start address to the signature start address register (FMSSTART) and the stop address to the signature stop address register (FMSSTOP.
Page 97 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP Table 69. FMSW1 register bit description (FMSW1, address: 0x4000 C030 (flash A) and 0x4000 D030 (flash B)) Symbol Description Reset Value 31:0 SW1[63:32] Word 1 of 128-bit signature (bits 63 to 32).
Page 98 UM10503 NXP Semiconductors Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP 6.11.2 Algorithm and procedure for signature generation Signature generation A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register.
Page 99 6), but other (secure) boot modes are also supported. The UART boot mode is only supported for flashless parts. The secure boot from USART3 is not supported for LPC43Sxx parts. 7.1.1 Determine the boot code version For parts with on-chip flash, the boot code version can be determined using ISP or IAP calls.
Page 100 Update the header with the calculated hash size. f. Encrypt header as before using CBC and an initialization vector of 0. 2. On the LPC43Sxx, program the encryption key into the OTP memory bank 1 using the API function aes_ProgramKey1 (see Table 76).
Page 101 UM10503 NXP Semiconductors Chapter 7: LPC43Sxx Boot ROM for secure parts 512B ENCRYPTION 512B 512B 512B <512B partition data in 512 Byte frames encrypt data with CBC AES AES key = User Key IV = AES (User Key,1) HASH VALUE...
Page 102 UM10503 NXP Semiconductors Chapter 7: LPC43Sxx Boot ROM for secure parts CPU clock disable key1 RESET = IRC IRQ & programmed? 12MHz load AES enable JTAG CPU clock ISP pin P2_7 96MHz LOW ? boot source = boot source UART, USB, SSP...
Page 103 UM10503 NXP Semiconductors Chapter 7: LPC43Sxx Boot ROM for secure parts Once the AES key1 is programmed in the OTP, the development mode is terminated and JTAG access is automatically disabled for flashless parts. 7.3.3 Boot image header format AES capable products with a programmed AES key1 will always boot from a secure image and use CMAC authentication.
Page 104 UM10503 NXP Semiconductors Chapter 7: LPC43Sxx Boot ROM for secure parts The authentication process works as follows: 1. Use the CMAC algorithm to generate the 128-bit tag. Truncate the tag to 64 MSB and insert this truncated tag in the header.
Page 105 UM10503 NXP Semiconductors Chapter 7: LPC43Sxx Boot ROM for secure parts Table 75. Typical boot process timing parameters Parameter Description Value < 1.25 s Check boot selection pins 250 s ; 180 s ; 200 s Initialize device < 0.3 s...
Page 106 Chapter 8: LPC43Sxx Security API Rev. 2.1 — 10 December 2015 User manual 8.1 How to read this chapter AES encryption and decryption and the AES API are supported for parts LPC43Sxx only. 8.2 Features • Decryption of external image data.
Page 107 UM10503 NXP Semiconductors Chapter 8: LPC43Sxx Security API OTP, a second key stored in the OTP (this key is not encrypted), a software supplied key, or a key generated by an on-chip random number generator. For encryption and decryption of data, an API is provided.
Page 108 8.5.6). 8.4 AES API The AES is controlled through a set of simple API calls located in the LPC43Sxx ROM. The API calls to the ROM are performed by executing functions which are pointed to by pointer within the ROM driver table.
Page 109 UM10503 NXP Semiconductors Chapter 8: LPC43Sxx Security API 8.4.1 AES functions The ROM-based security AES API controls the AES block. AES API functions are provided to encrypt or decrypt data from memory to memory using an ECB or CBC algorithm. If the CBC algorithm is selected, a user-defined initialization vector can be defined.
Page 110 UM10503 NXP Semiconductors Chapter 8: LPC43Sxx Security API Table 76. AES API calls Function Offset relative to Description the API entry point aes_LoadKeySW 0x14 Loads 128-bit AES software defined user key Parameter - unsigned char *key(16 bytes) Return - unsigned: see general error codes.
Page 111 UM10503 NXP Semiconductors Chapter 8: LPC43Sxx Security API Table 76. AES API calls Function Offset relative to Description the API entry point aes_Config_DMA 0x2C Checks for valid AES configuration of the chip and setup DMA channel to process an AES data block.
Page 112 UM10503 NXP Semiconductors Chapter 8: LPC43Sxx Security API 8.4.1.2 AES Error codes For general error codes, see Chapter 53 “LPC43xx/LPC43Sxx API General error codes”. /* Security API related errors */ ERR_SEC_AES_BASE = 0x00030000, /*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_AES_BASE+1, /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED, /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED, /*0x00030004*/ ERR_SEC_AES_DMA_CHANNEL_CFG,...
Page 113 The init vector does not have to be secret and is also used to decrypt the data. For the CMAC calculation, an AES initialization vector of iv = 0 is used. For the LPC43Sxx image, a user specific iv is used: iv = AES (User Key, 1) 8.5.5 Endianness...
Page 114 UM10503 NXP Semiconductors Chapter 8: LPC43Sxx Security API RAM Offset IV and Key: Always little endian IV: 000102030405060708090a0b0c0d0e0f 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 Key: 2b7e151628aed2a6abf7158809cf4f3c 4F CF 09 88 15 F7 AB A6 D2 AE 28 16 15 7E 2B...
Page 115 Flash/EEPROM interrupts: available on parts with on-chip flash only. The Cortex-M0SUB subsystem core NVIC is only available on parts LPC4370/LPC43S70 and LPC436x/LPC43S6x. 9.2 Basic configuration On the LPC43xx/LPC43Sxx, each core is supports its own NVIC. Each core can only access its own local NVIC registers. 9.3 Features •...
Page 116 UM10503 NXP Semiconductors Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller 9.4 General description The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M4 and M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
Page 117 UM10503 NXP Semiconductors Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller Table 78. Connection of interrupt sources to the Cortex-M4 NVIC Interrupt Exception Vector Function Flags Number Offset 0x70 TIMER0 0x74 TIMER1 0x78 TIMER2 0x7C TIMER3 0x80 MCPWM Motor control PWM...
Page 118 UM10503 NXP Semiconductors Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller Table 78. Connection of interrupt sources to the Cortex-M4 NVIC Interrupt Exception Vector Function Flags Number Offset 0x108 M0SUB TXEV instruction from the M0 subsystem core 0x10C C_CAN0 0x110 9.6.2 Interrupt sources for the Cortex-M0APP Table 79.
Page 119 UM10503 NXP Semiconductors Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller Table 79. Connection of interrupt sources to the Cortex-M0APP NVIC Interrupt Exception Vector Function Flag(s) Number Offset 0xB0 M0_I2S0_OR_I2S1_QEI I2S0 OR I2S1 OR QEI interrupt 0xB4 M0_C_CAN0 0xB8 M0_SPIFI_OR_ADCHS SPIFI OR ADCHS interrupt...
Page 120 UM10503 NXP Semiconductors Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller Table 80. Connection of interrupt sources to the Cortex-M0SUB subsystem NVIC Interrupt Exception Vector Function Flag(s) Number Offset 0xB4 M0S_C_CAN0 0xB8 M0S_SPIFI_OR_ADCHS SPIFI OR ADCHS combined interrupt 0xBC M0S_M0APP M0APP core 9.7 Register description...
Page 121 UM10503 NXP Semiconductors Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller Table 81. Register overview: NVIC (base address 0xE000 E000) …continued Name Access Address Description Reset offset value IPR5 0x414 Interrupt Priority Registers 5. This register allows assigning a priority to each interrupt.
Page 122 UM10503 Chapter 10: LPC43xx/LPC43Sxx Event router Rev. 2.1 — 10 December 2015 User manual 10.1 How to read this chapter The event router sources vary for different parts. • Ethernet: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and LPC4370/LPC43S70. • USB0: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and LPC4370/LPC43S70.
Page 123 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router The event router has multiple event inputs from various peripherals. When the proper edge detection is set in the EDGE configuration register, the event router can wake up the part or can raise an interrupt in the NVIC.
Page 124 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 83. Event router inputs Event # Source Description WWDT peripheral WWDT interrupt. Not active in Deep-sleep, Power-down, and Deep power-down mode. Use for wake-up from Sleep mode. Ethernet peripheral Wake-up packet indicator. Not active in Deep-sleep, Power-down, and Deep power-down mode.
Page 125 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router 10.5 Pin description Table 84. Event router pin description Direction Description WAKEUP0/1 External wake-up input; can raise an event router interrupt and can cause wake-up from any of the power-down modes. These pins can be configured to monitor the event...
Page 126 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 86. Level configuration register (HILO, address 0x4004 4000) bit description Symbol Value Description Reset value WAKEUP1_L Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.
Page 127 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 86. Level configuration register (HILO, address 0x4004 4000) bit description Symbol Value Description Reset value WWDT_L Level detect mode for WWDT event. Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0.
Page 128 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 86. Level configuration register (HILO, address 0x4004 4000) bit description Symbol Value Description Reset value TIM2_L Level detect mode for combined timer output 2 event. Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0.
Page 129 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router 10.6.2 Edge configuration register This register works in combination with the level configuration register HILO (see Table 86) to configure the level or edge detection for each input to the event router.
Page 130 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 88. Edge configuration register (EDGE, address 0x4004 4004) bit description Symbol Value Description Reset value ATIMER_E Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.
Page 131 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 88. Edge configuration register (EDGE, address 0x4004 4004) bit description Symbol Value Description Reset value SDMMC_E Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.
Page 132 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 88. Edge configuration register (EDGE, address 0x4004 4004) bit description Symbol Value Description Reset value BODRESET_E Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.
Page 133 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 89. Clear event enable register (CLR_EN, address 0x4004 4FD8) bit description Symbol Description Reset value TIM2_CLREN Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register.
Page 134 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 90. Event set enable register (SET_EN, address 0x4004 4FDC) bit description Symbol Description Reset value SDMMC_SETEN Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register.
Page 135 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router 10.6.5 Event status register The STATUS register monitors the internally generated interrupt or event signal from the peripherals. The contents of this register can be read at any time. To change the contents of this register, use the CLR_STAT and SET_STAT registers.
Page 136 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router The ENABLE register can be read at any time. To change the contents of this register, use the CLR_EN and SET_EN registers. Table 92. Event enable register (ENABLE, address 0x4004 4FE4) bit description...
Page 137 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 92. Event enable register (ENABLE, address 0x4004 4FE4) bit description Symbol Description Reset value QEI_EN A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
Page 138 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 93. Clear event status register (CLR_STAT, address 0x4004 4FE8) bit description Symbol Description Reset value SDMMC_CLRST Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register.
Page 139 UM10503 NXP Semiconductors Chapter 10: LPC43xx/LPC43Sxx Event router Table 94. Set event status register (SET_STAT, address 0x4004 4FEC) bit description Symbol Description Reset value USB0_SETST Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register.
Page 140 • FLASHCFGB register • SAMPLECTRL bit in the CREG0 register The ARM Cortex-M0APP processor is available on all LPC43xx/LPC43Sxx parts. The ARM Cortex-M0SUB subsystem core is only available on parts LPC4370/LPC43S70 and LPC436x/LPC43S6x. 11.2 Basic configuration The CREG block is configured as follows: •...
Page 141 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) 11.3 Features The following settings are controlled in the configuration register block: • ETB SRAM configuration • BOD trip settings • RTC Oscillator output • DMA-to-peripheral muxing • Ethernet mode •...
Page 142 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) 11.4 Register description Table 96. Register overview: Configuration registers (base address 0x4004 3000) Name Access Address Description Reset Reset Reset Reference offset value value after value EMC, after UART0/3 USB0/1 boot...
Page 143 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 96. Register overview: Configuration registers (base address 0x4004 3000) Name Access Address Description Reset Reset Reset Reference offset value value after value EMC, after UART0/3 USB0/1 boot boot M0APPMEMMAP 0x404...
Page 144 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 97. CREG0 register (CREG0, address 0x4004 3004) bit description …continued Symbol Value Description Reset Access value 11:10 BODLVL2 BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.
Page 145 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) 11.4.2 CREG1 control register Table 98. CREG1 register (CREG1, address 0x4004 3008) bit description Symbol Value Description Reset Access value Reserved USB0_PHY_PWREN_LP USB0 PHY power control in low power mode. Set this bit to enable the power to USB0 PHY in low power mode.
Page 146 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 100. CREG5 control register (CREG5, address 0x4004 3118) bit description Symbol Value Description Reset Access value Reserved. M0SUBTAPSEL JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.
Page 147 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 101. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value DMAMUXPER1 Select DMA to peripheral connection for DMA peripheral 1 Timer0 match 0...
Page 148 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 101. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value 17:16 DMAMUXPER8 Select DMA to peripheral connection for DMA peripheral 8. Timer3 match 1...
Page 149 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 101. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value 31:30 DMAMUXPER15 Select DMA to peripheral connection for DMA peripheral 15. SCT CTOUT_3...
Page 150 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 102. Flash Accelerator Configuration for flash bank A register (FLASHCFGA, address 0x4004 3120) bit description Symbol Value Description Reset value 11:0 Reserved. Do not change these bits from the reset value.
Page 151 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 103. Flash Accelerator Configuration for flash bank B register (FLASHCFGB, address 0x4004 3124) bit description Symbol Value Description Reset value 11:0 Reserved. Do not change these bits from the reset value.
Page 152 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) • Bit 4 selects the functionality of the SCT outputs connected to the CTOUT_n pins and selected GIMA inputs: – output Red with timer match output (default). SCTimer/PWM – output only.
Page 153 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) 11.4.10 Cortex-M4 TXEV event clear register This register captures the signal TXEV from the ARM Cortex-M4 processor (see Section 2.4.2). Table 106. M4 TXEV clear register (M4TXEVENT, address 0x4004 3130) bit description...
Page 154 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) 11.4.14 Cortex-M0APP TXEV event clear register This register captures the signal TXEV from the ARM Cortex-M0APP processor (see Section 2.4.2). Table 110. Cortex-M0APP TXEV clear register (M0APPTXEVENT, address 0x4004 3400) bit...
Page 155 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 112. USB0 frame length adjust register (USB0FLADJ, address 0x4004 3500) bit description Symbol Description Reset Access value FLTV Frame length timing value 0x20 The frame length is given in the number of high-speed bit times in decimal format.
Page 156 UM10503 NXP Semiconductors Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG) Table 113. USB1 frame length adjust register (USB1FLADJ, address 0x4004 3600) bit description Symbol Description Reset Access value FLTV Frame length timing value 0x20 The frame length is given in the number of high-speed bit times in decimal format.
Page 157 The PMC controls the power consumption of the part and configures the power state of the cores, memories, and peripherals. The LPC43xx/LPC43Sxx supports the following power modes in order from highest to lowest power consumption: 1. Active mode (for each core independently) 2.
Page 158 UM10503 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) System Deep-sleep WAKEUP pins Power-down RTC/Alarm timer alarm M4 NVIC: event router IRQ M4: WFI/WFE, SLEEPDEEP = 1 PD0_SLEEP0_MODE = 0x0030 00AA or 0x0030 FCBA M4 active (master) PD0_SLEEP0_HW_ENA = 0x1...
Page 159 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) 12.2.1 Active mode By default, the LPC43xx/LPC43Sxx is in Active mode, which means that every peripheral can perform a functional operation at nominal operating conditions. 12.2.2 Sleep mode In Sleep mode, the CPU clock is shut down to save power; the peripherals can still remain active and fully functional.
Page 160 UM10503 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) 12.2.4 Power-down mode In Power-down mode the CPU clock and peripheral clocks are shut down but logic states are maintained. All SRAM memory except for the upper 8 kB of the local SRAM located at 0x1008 0000, all analog blocks, and the BOD control circuit are powered down.
Page 161 UM10503 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) 12.2.6 Hardware control of Deep-sleep, Power-down, Deep power-down modes The hardware sleep event enable register (Table 117) enables the ARM Cortex-M0 cores or the ARM Cortex-M4 core to trigger a system power-down (deep-sleep, power-down, or deep power-down).
Page 162 UM10503 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) Table 115. Memory retention Mode 32/128 kB 64/32 kB Local 8 kB local SRAM 16 + 2 kB M0 64 kB AHB 256 byte local SRAM SRAM starting starting at...
Page 163 UM10503 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) Table 117. Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address 0x4004 2000) bit description Symbol Description Reset Access value ENA_EVENT0 Writing a 1 enables the Cortex-M4 core to put the part...
Page 164 UM10503 NXP Semiconductors Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC) 12.4 Functional description 12.4.1 Run-time programming The PD0_SLEEP0_MODE register can be programmed at run-time to change the default power state of the LPC43xx after the next transition to a reduced-power state.
Page 165 UM10503 Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Rev. 2.1 — 10 December 2015 User manual 13.1 How to read this chapter Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See Section 1.3. The corresponding clock control registers are reserved.
Page 166 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.2.1.1 Changing the BASE_M4_CLK after power-up, reset, or deep power-down mode The following procedure shows how to change the default setting of the core clock (BASE_M4_CLK = 96 MHz; IRC = PLL1 clock source) to an operating frequency above 110 MHz while also changing the clock source from IRC to crystal oscillator: 1.
Page 167 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) BASE_M4_CLK BASE_M4_CLK clock source = PLL1 (crystal osc) 204 MHz outPLL 50 μs 110 MHz outPLL/2 90 MHz PLL1 lock time 250 μs 12 MHz enable set PLL1 M, N dividers,...
Page 168 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) PLL0 WWDT BASE_SAFE_CLK (USB0) IDIVA OUTCLK1- 6, 9 - 10 branch clocks to core 12 MHz IRC IDIVB CCU1 PLL0 (BASE_xxx_CLK) and peripherals (AUDIO) RTCX1 32 kHz OSC IDIVC branch clocks to...
Page 169 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) – Integer divider A: maximum division factor = 4 (see Table 139). – Integer dividers B, C, D: maximum division factor = 16 (see Table 140). – Integer divider E: maximum division factor = 256 (see Table 141).
Page 170 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 122. Clock sources for clock generators with selectable inputs Clock generators Clock sources PLL0 PLL0 PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE AUDIO /256 32 kHz oscillator IRC 12 MHz...
Page 171 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 123. Clock sources for output stages Output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) Clock sources PLL1...
Page 172 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.5 Pin description Table 124. CGU pin description Pin function Direction Description XTAL1 Crystal oscillator input XTAL2 Crystal oscillator output RTCX1 RTC 32 kHz oscillator input RTCX2 RTC 32 kHz oscillator output...
Page 173 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 125. Register overview: CGU (base address 0x4005 0000) Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot PLL0AUDIO_STAT...
Page 174 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 125. Register overview: CGU (base address 0x4005 0000) Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot BASE_SPI_CLK...
Page 175 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 125. Register overview: CGU (base address 0x4005 0000) Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot OUTCLK_21_CTRL...
Page 176 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 126. FREQ_MON register (FREQ_MON, address 0x4005 0014) bit description Symbol Value Description Reset Access value RCNT 9-bit reference clock-counter value 22:9 FCNT 14-bit selected clock-counter value MEAS Measure frequency...
Page 177 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 127. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit description Symbol Value Description Reset Access value BYPASS Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and...
Page 178 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 129. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description …continued Symbol Value Description Reset Access value DIRECTI PLL0 direct input DIRECTO PLL0 direct output CLKEN PLL0 clock enable...
Page 179 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) /* multiplier: compute mdec from msel */ unsigned mdec_new (unsigned msel) { unsigned x=0x4000, im; switch (msel) { case 0: return 0xFFFFFFFF; case 1: return 0x18003; case 2: return 0x10003;...
Page 180 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.6.3.4 PLL0USB NP-divider register Remark: The PLL NP-divider register does not use the direct binary representations of N = nsel and P = psel directly. Instead, it uses encoded versions NDEC and PDEC of N and P respectively.
Page 181 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.6.4 PLL0AUDIO registers The PLL0AUDIO provides a wide range of frequencies for audio applications and can be connected to multiple base clocks. The PLL0AUDIO can be used with or without a fractional divider.
Page 182 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 133. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description …continued Symbol Value Description Reset Access value PLLFRACT_ Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit.
Page 183 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) unsigned mdec_new (unsigned msel) { unsigned x=0x4000, im; switch (msel) { case 0: return 0xFFFFFFFF; case 1: return 0x18003; case 2: return 0x10003; default: for (im = msel; im <= PLL0_MSEL_MAX; im++) x = ((x ^ x>>1) &...
Page 184 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) switch (psel) { case 0: return 0xFFFFFFFF; case 1: return 0x62; case 2: return 0x42; default:for (ip = psel; ip <= PLL0_PSEL_MAX; ip++) x = ((x ^ x>>2) & 1) << 4 | x>>1 & 0x3F;...
Page 185 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.6.5.2 PLL1 control register Table 138. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description Symbol Value Description Reset Access value PLL1 power down PLL1 enabled PLL1 powered down BYPASS Input clock bypass control Normal.
Page 186 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 138. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description …continued Symbol Value Description Reset Access value 23:16 MSEL Feedback-divider division ratio (M) 11000 R/W 00000000 = 1 00000001 = 2...
Page 187 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 139. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description …continued Symbol Value Description Reset Access value AUTOBLOCK Block clock automatically during frequency change Disabled. Autoblocking disabled Enabled. Autoblocking enabled...
Page 188 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 140. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. All other values 0x01 are reserved.
Page 189 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 141. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. All other values are 0x01 reserved. 0x00 32 kHz oscillator...
Page 190 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 143. BASE_USB0_CLK control register (BASE_USB0_CLK, address 0x4005 0060) bit description Symbol Value Description Reset Access value Output stage power down Enabled. Output stage enabled (default) Power-down 10:1 Reserved AUTOBLOCK...
Page 191 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 144. BASE_PERIPH_CLK control register (BASE_PERIPH_CLK, address 0x4005 0064) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved. 0x00...
Page 192 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 145. BASE_USB1_CLK control register (BASE_USB1_CLK, address 0x4005 0068) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved. 0x00...
Page 193 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 146. BASE_M4_CLK to BASE_UART3_CLK control registers (BASE_M4_CLK to BASE_UART3_CLK, address 0x4005 006C to 0x4005 00A8) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved.
Page 194 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 147. BASE_OUT_CLK control register BASE_OUT_CLK, addresses 0x4005 00AC) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default)
Page 195 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 148. BASE_AUDIO_CLK control register (BASE_AUDIO_CLK, addresses 0x4005 00C0) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default)
Page 196 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 149. BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK control register (BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK, addresses 0x4005 00C4 to 0x4005 00C8) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01...
Page 197 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.7.4.1 Features • Input frequency: 14 kHz to 150 MHz. The input from an external crystal is limited to 25 MHz. • CCO frequency: 275 MHz to 550 MHz. •...
Page 198 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Bypass Direct Output CTRL[1] CTRL[3] 32kHz CLKOUT ENET_RX_CLK ENET_TX_CLK GP_CLKIN CRYSTAL P-DIVIDER N-DIVIDER Filter PLL1 CLKIN IDIVA “1” IDIVB IDIVC IDIVD Bandwidth Select P,I,R NP_DIV[6:0] NP_DIV[21:12] IDIVE MDIV[31:17] Direct Input...
Page 199 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) • mode 1a: Normal operating mode without post-divider and without pre-divider • mode 1b: Normal operating mode with post-divider and without pre-divider • mode 1c: Normal operating mode without post-divider and with pre-divider •...
Page 200 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-divider In normal operating mode 1d none of the dividers are bypassed. The operating frequencies are: Fout = Fcco /(2 x P) = M x Fin /(N x P)  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150...
Page 201 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) the fractional part of the PLLFRACT_CTRL register (PLLFRACT[14:0]). Consecutive M and M+1 values are then further encoded into appropriate MENC values before being presented as input to the M-divider. Bypass...
Page 202 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.7.6.2 PLL1 description P-divider PSEL<1:0> NSEL<1:0> ÷2xP LOCK FCLKOUT LOCK DETECT BYPASS DIRECT analog section FBSEL MSEL<7:0> Fig 40. PLL1 block diagram The block diagram of this PLL is shown in Figure 40.
Page 203 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.
Page 204 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) FCLKIN      --------------------- - FCCO FCLKOUT Non-integer mode In this mode the post-divider is enabled and the feedback divider is set to run directly on the CCO clock, which gives the following frequency dividers:...
Page 205 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) 13.8 Example CGU configurations 13.8.1 Programming the CGU for Deep-sleep and Power-down modes Before the LPC43xx enters Deep-sleep or Power-down mode, the IRC must be programmed as the clock source in the control registers for all output stages (OUTCLK_0 to OUTCLK_27).
Page 206 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 152. PLL0 (for USB) settings for 480 MHz output clock Fclkin [MHz] PLL0USB_MDIV PLL0USB_NP_DIV Table 130 Table 131 0x073E 56C9 0x0030 2062 0x073E 2DAD 0x0030 2062 0x0B3E 34B1 0x0030 2062...
Page 207 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 153. PLL0AUDIO divider settings for 12 MHz input Fs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRL Table 135 Table 136 16.384 360.448 0x0000101d 0x16872b 12.288 417.792...
Page 208 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 153. PLL0AUDIO divider settings for 12 MHz input Fs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRL Table 135 Table 136 22.05 22.5792 451.584 0x0000100e 0x1c3958 16.384...
Page 209 UM10503 NXP Semiconductors Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU) Table 154. PLL0AUDIO divider setting for 12 MHz with fractional divider bypassed Fout Fcco Error PLL0AUDIO_ PLL0AUDIO_ [KHz] [MHz] [MHz] [Hz] NDEC MDEC PDEC MDIV NP_DIV Table 134 Table 135 44.1...
Page 210 UM10503 Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Rev. 2.1 — 10 December 2015 User manual 14.1 How to read this chapter The ADCHS is only available on parts LPC4370/LPC43S70. The Cortex-M0 subsystem core and the subsystem AHB multilayer matrix are only enabled on parts LPC4370/LPC43S70 and LPC436x/LPC43S6x.
Page 211 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 156. CCU1 branch clocks Base clock Branch clock Description BASE_APB3_CLK CLK_APB3_BUS APB3 bus clock. CLK_APB3_I2C1 Clock to the I2C1 register interface and I2C1 peripheral clock. CLK_APB3_DAC Clock to the DAC register interface.
Page 212 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 156. CCU1 branch clocks Base clock Branch clock Description BASE_M4_CLK CLK_M4_TIMER0 Clock to the timer0 register interface and timer0 peripheral clock. CLK_M4_TIMER1 Clock to the timer1 register interface and timer1 peripheral clock.
Page 213 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) 14.5 Register description Table 158. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset 0x000 CCU1 power mode register 0x0000 0000 Table 160 BASE_STAT...
Page 214 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 158. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_M4_SPIFI_STAT 0x40C CLK_M4_SPIFI status register 0x0000 0001 Table 166 CLK_M4_GPIO_CFG 0x410 CLK_M4_GPIO configuration register...
Page 215 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 158. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset 0x4A8 to Reserved 0x4FC CLK_M4_WWDT_CFG 0x500 CLK_M4_WWDT configuration register 0x0000 0001 Table 163...
Page 216 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 158. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_PERIPH_CORE_CFG 0x710 CLK_PERIPH_CORE configuration 0x0000 0001 Table 163 register CLK_PERIPH_CORE_STAT 0x714 CLK_PERIPH_CORE status register...
Page 217 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 159. Register overview: CCU2 (base address 0x4005 2000) Name Access Address Description Reset value Reference offset 0x408 to Reserved 0x4FC CLK_APB0_USART0_CFG 0x500 CLK_APB0_UART0 configuration register 0x0000 0001 Table 165...
Page 218 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 161. CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit description Symbol Description Reset Access value BASE_APB3_ Base clock indicator for BASE_APB3_CLK CLK_IND 0 = All branch clocks switched off.
Page 219 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 162. CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit description …continued Symbol Description Reset Access value BASE_UART0_ Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off.
Page 220 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 163. CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 1100, 0x4005 1104,..., 0x4005 1A00) bit description Symbol Value Description Reset Access value Run enable Clock is disabled. Clock is enabled.
Page 221 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 165. CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 2100, 0x4005 2200,..., 0x4005 2800) bit description Symbol Value Description Reset Access value Run enable Clock is disabled. Clock is enabled.
Page 222 UM10503 NXP Semiconductors Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU) Table 166. CCU1 branch clock status register (CLK_XXX_STAT, addresses 0x4005 1104, 0x4005 110C,..., 0x4005 1A04) bit description …continued Symbol Description Reset Access value Reserved. RUN_N Clock disable status. This bit has same functionality as the RUN bit except with the opposite polarity.
Page 223 UM10503 Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Rev. 2.1 — 10 December 2015 User manual 15.1 How to read this chapter Flash/EEPROM, Ethernet, USB0, USB1, ADCHS, and LCD related resets are not available on all packages or parts. See Section 1.3.
Page 224 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) RTC POWER DOMAIN alarm timer, RTC, CREG (partial), PMC RESET WWDT CORE_RST CREG (partial), PMC BOD reset GENERATOR WWDT reset Bus bridges, memory controllers PERIPH_RST APB peripherals, GPIO GENERATOR Cortex-M4 core...
Page 225 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 169. Reset output configuration …continued Reset output Reset Reset source Parts of the device reset when generator output activated Reserved LCD_RST MASTER_RST LCD controller reset USB0_RST MASTER_RST USB0 reset...
Page 226 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 169. Reset output configuration …continued Reset output Reset Reset source Parts of the device reset when generator output activated CAN1_RST PERIPH_RST C_CAN1 reset CAN0_RST PERIPH_RST C_CAN0 reset M0APP_RST MASTER_RST ARM Cortex-M0 co-processor reset.
Page 227 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) The CREG0 register maintains its value during reset for partial resets. TRSTn TRSTn_loc RESET CORE_RST BOD reset delay=3 WWDT reset PMC reset CORE_RST WWDT_RST delay=3 no sw CREG_RST delay=3 no sw...
Page 228 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 171. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset 0x410 RESET_EXT_STAT5 0x414 Reset external status register 5 for Table 182 CREG_RST...
Page 229 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 171. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT32 0x480 Reset external status register 32 for Table 183 TIMER0_RST RESET_EXT_STAT33...
Page 230 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 171. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT55 0x4DC Reset external status register 55 for Table 183 CAN0_RST RESET_EXT_STAT56...
Page 231 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 172. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description …continued Symbol Description Reset Access value SCU_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
Page 232: Table Of Contents
UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 173. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description Symbol Description Reset Access value TIMER0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
Page 233 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 173. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description …continued Symbol Description Reset Access value CAN0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
Page 234 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 174. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Symbol Description Reset Access value WWDT_RST Status of the WWDT_RST reset generator output 00 = No reset activated...
Page 235 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 175. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description Symbol Description Reset Access value LCD_RST Status of the LCD_RST reset generator output 00 = No reset activated...
Page 236 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 175. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description …continued Symbol Description Reset Access value 19:18 FLASHA_RST Status of the FLASHA_RST reset generator output 00 = No reset activated...
Page 237 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 176. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description Symbol Description Reset Access value TIMER0_RST Status of the TIMER0_RST reset generator output 00 = No reset activated...
Page 238 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 176. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued …continued Symbol Description Reset Access value 17:16 ADC0_RST Status of the ADC0_RST reset generator output 00 = No reset activated...
Page 239 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 177. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description Symbol Description Reset Access value I2C0_RST Status of the I2C0_RST reset generator output 00 = No reset activated...
Page 240 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 177. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description …continued Symbol Description Reset Access value 17:16 M0APP_RST Status of the M0APP_RST reset generator output 00 = No reset activated...
Page 241 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 178. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued Symbol Description Reset Access value Reserved WWDT_RST Current status of the WWDT_RS 0 = Reset asserted...
Page 242 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 178. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued Symbol Description Reset Access value EMC_RST Current status of the EMC_RST 0 = Reset asserted 1 = No reset...
Page 243: Ritimer_Rst
UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 179. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued Symbol Description Reset Access value RITIMER_RST Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset...
Page 244: Ssp0_Rst
UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) Table 179. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued Symbol Description Reset Access value SSP0_RST Current status of the SSP0_RST 0 = Reset asserted 1 = No reset...
Page 245 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) All reset generators except the WWDT time-out reset, the BOD reset, the reset signal from the PMU, and the software reset, which have no inputs, have an associated external status register. All reset generators have only one input which, depending on the hierarchy, can be either the CORE_RST, the PERIPHERAL_RST, or the MASTER_RST.
Page 246 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) 15.4.4.4 Reset external status registers for PERIPHERAL_RESET Refer to Table 171 for reset generators which have the PERIPH_RST output as reset source. Table 183. Reset external status registers x (RESET_EXT_STATx, address 0x4005 34xx) bit...
Page 247 UM10503 NXP Semiconductors Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU) a. Check the state of the HILO, EDGE registers, and the RESET_E and RESET_ST bits in the EDGE and STATUS registers i. HILO==0 & EDGE==0  power on reset ii. RESET_E==1 && RESET_ST==1  external reset input (RESET) b.
Page 248 This chapter applies to all parts. 16.2 Pin description On the LPC43xx/LPC43Sxx, digital pins are grouped into 16 pin groups, named P0 to P9 and PA to PF, with up to 20 pins used per group. Each digital pin may support up to eight different digital pin functions, including General Purpose I/O (GPIO), selectable through the SCU pin configuration registers.
Page 249 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description Multiplexed digital pins P0_0 I/O GPIO0[0] — General purpose digital input/output pin.
Page 250 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_1 I/O GPIO0[8] — General purpose digital input/output pin. Boot pin...
Page 251 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_5 I/O GPIO1[8] — General purpose digital input/output pin. CTOUT_10 — SCT output 10. Match output 2 of timer 2.
Page 252 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_8 I/O GPIO1[1] — General purpose digital input/output pin. U1_DTR — Data Terminal Ready output for UART1.
Page 253 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_12 I/O GPIO1[5] — General purpose digital input/output pin. U1_DCD — Data Carrier Detect input for UART1.
Page 254 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_16 I/O GPIO0[3] — General purpose digital input/output pin. U2_RXD — Receiver input for USART2.
Page 255 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_20 K10 70 I/O GPIO0[15] — General purpose digital input/output pin.
Page 256 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_2 I/O SGPIO6 — General purpose digital input/output pin. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode.
Page 257 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_5 D10 91 I/O SGPIO14 — General purpose digital input/output pin.
Page 258 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_8 H14 C6 I/O SGPIO15 — General purpose digital input/output pin. Boot pin...
Page 259 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_12 D13 B9 I/O GPIO1[12] — General purpose digital input/output pin.
Page 260 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_1 D10 F7 I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave.
Page 261 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_4 C14 B8 I/O GPIO1[14] — General purpose digital input/output pin.
Page 262 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_8 R — Function reserved. SPI_SSEL — Slave Select for SPI. Note that this pin in an input pin only.
Page 263 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_3 I/O GPIO2[3] — General purpose digital input/output pin. CTOUT_3 — SCT output 3. Match output 3 of timer 0.
Page 264 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_6 I/O GPIO2[6] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 3 of timer 3.
Page 265 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_10 R — Function reserved. CTIN_2 — SCT input 2. Capture input 2 of timer 0.
Page 266 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P5_3 I/O GPIO2[12] — General purpose digital input/output pin. MCI0 — Motor control PWM channel 0, input.
Page 267 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P5_7 I/O GPIO2[7] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A.
Page 268 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_3 N13 - I/O GPIO3[2] — General purpose digital input/output pin.
Page 269 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_6 I/O GPIO0[5] — General purpose digital input/output pin. EMC_BLS1 — LOW active Byte Lane select signal 1.
Page 270 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_10 G13 - I/O GPIO3[6] — General purpose digital input/output pin.
Page 271 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_1 C13 - I/O GPIO3[9] — General purpose digital input/output pin.
Page 272 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_5 I/O GPIO3[13] — General purpose digital input/output pin. CTOUT_12 — SCT output 12. Match output 3 of timer 3.
Page 273 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_0 I/O GPIO4[0] — General purpose digital input/output pin. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition;...
Page 274 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_4 I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
Page 275 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_8 R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY.
Page 276 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P9_3 I/O GPIO4[15] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A.
Page 277 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P9_6 I/O GPIO4[11] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B.
Page 278 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PA_3 I/O GPIO4[10] — General purpose digital input/output pin. QEI_PHA — Quadrature Encoder Interface PHA input.
Page 279 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PB_2 R — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.
Page 280 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PB_6 R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
Page 281 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_3 I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.
Page 282 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_7 R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
Page 283 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_11 R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI data line direction.
Page 284 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_0 R — Function reserved. CTOUT_15 — SCT output 15. Match output 3 of timer 3.
Page 285 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_4 R — Function reserved. CTOUT_8 — SCT output 8. Match output 0 of timer 2.
Page 286 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_8 R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3.
Page 287 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_12 R — Function reserved. R — Function reserved. EMC_CS2 — LOW active Chip Select 2 signal.
Page 288 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_16 R — Function reserved. R — Function reserved. I/O EMC_A16 — External memory address line 16.
Page 289 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_3 R — Function reserved. CAN0_TD — CAN transmitter output.
Page 290 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_7 R — Function reserved. CTOUT_5 — SCT output 5. Match output 3 of timer 3.
Page 291 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_11 R — Function reserved. CTOUT_12 — SCT output 12. Match output 3 of timer 3.
Page 292 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_15 R — Function reserved. CTOUT_0 — SCT output 0. Match output 0 of timer 0.
Page 293 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_3 R — Function reserved. U3_RXD — Receiver input for USART3.
Page 294 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_6 R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
Page 295 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_9 R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
Page 296 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description CLK0 EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin.
Page 297 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description DBGEN JTAG interface control signal. Also used for boundary scan.
Page 298 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description [11] WAKEUP2 I; IA External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes.
Page 299 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 185. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description VBAT RTC power supply: 3.3 V on this pin supplies power to the RTC.
Page 300 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO;...
Page 301 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description LCD is not available on all parts. Symbol Description Multiplexed digital pins P0_0 I; PU I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1.
Page 302 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P1_2 I; PU I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 22). CTOUT_6 — SCT output 6. Match output 2 of timer 1.
Page 303 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P1_6 I; PU I/O GPIO1[9] — General purpose digital input/output pin. CTIN_5 — SCT input 5. Capture input 2 of timer 2.
Page 304 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P1_10 I; PU I/O GPIO1[3] — General purpose digital input/output pin. U1_RI — Ring Indicator input for UART1.
Page 305 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P1_14 I; PU I/O GPIO1[7] — General purpose digital input/output pin. U1_RXD — Receiver input for UART1.
Page 306 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P1_18 I; PU I/O GPIO0[13] — General purpose digital input/output pin. I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2.
Page 307 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P2_1 I; PU I/O SGPIO5 — General purpose digital input/output pin. U0_RXD — Receiver input for USART0.
Page 308 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P2_5 I; PU I/O SGPIO14 — General purpose digital input/output pin. CTIN_2 — SCT input 2. Capture input 2 of timer 0.
Page 309 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P2_9 I; PU I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 22). CTOUT_3 — SCT output 3. Match output 3 of timer 0.
Page 310 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P2_13 I; PU I/O GPIO1[13] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1.
Page 311 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P3_3 I; PU - R — Function reserved. I/O SPI_SCK — Serial clock for SPI. I/O SSP0_SCK — Serial clock for SSP0.
Page 312 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P3_7 I; PU - R — Function reserved. I/O SPI_MOSI — Master Out Slave In for SPI.
Page 313 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P4_2 I; PU I/O GPIO2[2] — General purpose digital input/output pin. CTOUT_0 — SCT output 0. Match output 0 of timer 0.
Page 314 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P4_6 I; PU I/O GPIO2[6] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 0 of timer 1.
Page 315 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P4_10 I; PU - R — Function reserved. CTIN_2 — SCT input 2. Capture input 2 of timer 0.
Page 316 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P5_3 I; PU I/O GPIO2[12] — General purpose digital input/output pin. MCI0 — Motor control PWM channel 0, input.
Page 317 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P5_7 I; PU I/O GPIO2[7] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A.
Page 318 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P6_3 I; PU I/O GPIO3[2] — General purpose digital input/output pin. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit);...
Page 319 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P6_7 I; PU - R — Function reserved. I/O EMC_A15 — External memory address line 15. I/O SGPIO6 — General purpose digital input/output pin.
Page 320 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P6_11 I; PU I/O GPIO3[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved.
Page 321 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P7_2 I; PU I/O GPIO3[10] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1.
Page 322 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P7_6 I; PU I/O GPIO3[14] — General purpose digital input/output pin. CTOUT_11 — SCT output 1. Match output 3 of timer 2.
Page 323 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P8_2 I; PU I/O GPIO4[2] — General purpose digital input/output pin. USB0_IND0 — USB0 port indicator LED control output 0.
Page 324 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P8_6 I; PU I/O GPIO4[6] — General purpose digital input/output pin. USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY.
Page 325 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P9_1 I; PU I/O GPIO4[13] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A.
Page 326 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description P9_5 I; PU - R — Function reserved. MCOA1 — Motor control PWM channel 1, output A.
Page 327 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PA_2 I; PU I/O GPIO4[9] — General purpose digital input/output pin. QEI_PHB — Quadrature Encoder Interface PHB input.
Page 328 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PB_1 I; PU - R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction.
Page 329 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PB_5 I; PU - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.
Page 330 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PC_2 I; PU I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. R — Function reserved. U1_CTS — Clear to Send input for UART 1.
Page 331 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PC_6 I; PU - R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.
Page 332 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PC_10 I; PU - R — Function reserved. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY.
Page 333 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PC_14 I; PU - R — Function reserved. R — Function reserved. U1_RXD — Receiver input for UART 1.
Page 334 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PD_3 I; PU - R — Function reserved. CTOUT_6 — SCT output 7. Match output 2 of timer 1.
Page 335 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PD_7 I; PU - R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2.
Page 336 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PD_11 I; PU - R — Function reserved. R — Function reserved. EMC_CS3 — LOW active Chip Select 3 signal.
Page 337 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PD_15 I; PU - R — Function reserved. R — Function reserved. I/O EMC_A17 — External memory address line 17.
Page 338 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PE_2 I; PU I ADCTRIG0 — ADC trigger input 0. CAN0_RD — CAN receiver input. R — Function reserved.
Page 339 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PE_6 I; PU - R — Function reserved. CTOUT_2 — SCT output 2. Match output 2 of timer 0.
Page 340 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PE_10 I; PU - R — Function reserved. CTIN_3 — SCT input 3. Capture input 1 of timer 1.
Page 341 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PE_14 I; PU - R — Function reserved. R — Function reserved. R — Function reserved. EMC_DYCS3 — SDRAM chip select 3.
Page 342 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PF_2 I; PU - R — Function reserved. U3_TXD — Transmitter output for USART3. I/O SSP0_MISO — Master In Slave Out for SSP0.
Page 343 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PF_6 I; PU - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
Page 344 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description PF_9 I; PU - R — Function reserved. [13] I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
Page 345 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description Clock pins CLK0 EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved.
Page 346 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description TCK/SWDCLK I; F Test Clock for JTAG interface (default) or Serial Wire (SW) clock. TRST I; PU I Test Reset for JTAG interface.
Page 347 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description ADC pins ADCHS_0 I; IA 12-bit high-speed ADC input channel 0. ADCHS_1 I; IA 12-bit high-speed ADC input channel 1.
Page 348 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 186. LPC4370/LPC43S70 Pin description …continued LCD is not available on all parts. Symbol Description VDDIO F10, I/O power supply. Tie the VDDREG and VDDIO pins to a common power E12, supply to ensure the same ramp-up time for both supply voltages.
Page 349 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if V present; DD(IO) if V not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital DD(IO) section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP...
Page 350 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) Pin name Description Multiplexed digital pins P0_0 I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
Page 351 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P1_1 I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 22). CTOUT_7 — SCT output 7. Match output 3 of timer 1.
Page 352 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P1_5 I/O GPIO1[8] — General purpose digital input/output pin. CTOUT_10 — SCT output 10. Match output 3 of timer 3. R — Function reserved.
Page 353 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P1_8 I/O GPIO1[1] — General purpose digital input/output pin. U1_DTR — Data Terminal Ready output for UART1. CTOUT_12 — SCT output 12. Match output 3 of timer 3.
Page 354 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P1_12 I/O GPIO1[5] — General purpose digital input/output pin. U1_DCD — Data Carrier Detect input for UART1. R — Function reserved.
Page 355 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P1_16 I/O GPIO0[3] — General purpose digital input/output pin. U2_RXD — Receiver input for USART2. I/O SGPIO3 — General purpose digital input/output pin.
Page 356 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P1_20 I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. R — Function reserved. ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
Page 357 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P2_2 I/O SGPIO6 — General purpose digital input/output pin. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11.
Page 358 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P2_5 I/O SGPIO14 — General purpose digital input/output pin. CTIN_2 — SCT input 2. Capture input 2 of timer 0. USB1_VBUS — Monitors the presence of USB1 bus power.
Page 359 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P2_9 I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 22). CTOUT_3 — SCT output 3. Match output 3 of timer 0.
Page 360 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P2_13 I/O GPIO1[13] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. R — Function reserved.
Page 361 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P3_2 I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I S-bus specification.
Page 362 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P3_5 I/O GPIO1[15] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.
Page 363 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P4_0 I/O GPIO2[0] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. NMI — External interrupt input to NMI.
Page 364 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P4_4 I/O GPIO2[4] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. LCD_VD1 — LCD data.
Page 365 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P4_7 LCD_DCLK — LCD panel clock. GP_CLKIN — General purpose clock input to the CGU. R — Function reserved. R — Function reserved.
Page 366 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P5_0 I/O GPIO2[9] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. I/O EMC_D12 — External memory data line 12.
Page 367 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P5_4 I/O GPIO2[13] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. I/O EMC_D8 — External memory data line 8.
Page 368 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P6_0 R — Function reserved. I2S0_RX_MCLK — I2S receive master clock. R — Function reserved. R — Function reserved. I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and received by the slave.
Page 369 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P6_3 I/O GPIO3[2] — General purpose digital input/output pin. USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that the VBUS signal must be driven (active HIGH).
Page 370 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P6_7 R — Function reserved. I/O EMC_A15 — External memory address line 15. I/O SGPIO6 — General purpose digital input/output pin.
Page 371 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P6_11 I/O GPIO3[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. EMC_CKEOUT0 — SDRAM clock enable 0.
Page 372 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P7_2 I/O GPIO3[10] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver.
Page 373 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P7_6 I/O GPIO3[14] — General purpose digital input/output pin. CTOUT_11 — SCT output 1. Match output 3 of timer 2. R — Function reserved.
Page 374 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P8_2 I/O GPIO4[2] — General purpose digital input/output pin. USB0_IND0 — USB0 port indicator LED control output 0. R — Function reserved.
Page 375 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P8_6 I/O GPIO4[6] — General purpose digital input/output pin. USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY.
Page 376 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P9_1 I/O GPIO4[13] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A. R — Function reserved.
Page 377 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description P9_5 R — Function reserved. MCOA1 — Motor control PWM channel 1, output A. USB1_PPWR — VBUS drive signal (towards external charge pump or power management unit);...
Page 378 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PA_2 I/O GPIO4[9] — General purpose digital input/output pin. QEI_PHB — Quadrature Encoder Interface PHB input. R — Function reserved. U2_RXD — Receiver input for USART2.
Page 379 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PB_1 R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. LCD_VD22 — LCD data.
Page 380 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PB_5 R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. LCD_VD14 — LCD data. R — Function reserved.
Page 381 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PC_2 I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. R — Function reserved. U1_CTS — Clear to Send input for UART 1.
Page 382 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PC_6 R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. R — Function reserved. ENET_RXD2 — Ethernet receive data 2 (MII interface).
Page 383 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PC_10 R — Function reserved. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. U1_DSR — Data Set Ready input for UART 1.
Page 384 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PC_14 R — Function reserved. R — Function reserved. U1_RXD — Receiver input for UART 1. R — Function reserved. I/O GPIO6[13] — General purpose digital input/output pin.
Page 385 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PD_3 R — Function reserved. CTOUT_6 — SCT output 7. Match output 2 of timer 1. I/O EMC_D17 — External memory data line 17.
Page 386 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PD_7 R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. I/O EMC_D21 — External memory data line 21.
Page 387 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PD_11 R — Function reserved. R — Function reserved. EMC_CS3 — LOW active Chip Select 3 signal. R — Function reserved.
Page 388 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PD_15 R — Function reserved. R — Function reserved. I/O EMC_A17 — External memory address line 17. R — Function reserved.
Page 389 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PE_2 ADCTRIG0 — ADC trigger input 0. CAN0_RD — CAN receiver input. R — Function reserved. I/O EMC_A20 — External memory address line 20.
Page 390 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PE_6 R — Function reserved. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U1_RI — Ring Indicator input for UART 1.
Page 391 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PE_10 R — Function reserved. CTIN_3 — SCT input 3. Capture input 1 of timer 1. U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1.
Page 392 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PE_14 R — Function reserved. R — Function reserved. R — Function reserved. EMC_DYCS3 — SDRAM chip select 3. I/O GPIO7[14] — General purpose digital input/output pin.
Page 393 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PF_2 R — Function reserved. U3_TXD — Transmitter output for USART3. I/O SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved.
Page 394 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PF_6 R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1.
Page 395 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description PF_9 R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. CTOUT_1 — SCT output 1. Match output 3 of timer 3.
Page 396 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description Clock pins CLK0 EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved.
Page 397 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description Debug pins DBGEN JTAG interface control signal. Also used for boundary scan. TCK/SWDCLK I; F Test Clock for JTAG interface (default) or Serial Wire (SW) clock.
Page 398 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description [11] WAKEUP1 I; IA External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part.
Page 399 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration Table 188. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued Pin name Description USB0_VSSA Dedicated analog ground for clean reference for termination _TERM resistors. USB0_VSSA Dedicated clean analog ground for generation of reference _REF currents and voltages.
Page 400 UM10503 NXP Semiconductors Chapter 16: LPC43xx/LPC43Sxx Pin configuration N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA = inactive;...
Page 401 UM10503 Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO configuration Rev. 2.1 — 10 December 2015 User manual 17.1 How to read this chapter The following peripherals are not available on all parts, and the corresponding bit values that select those functions in the SFSP registers are reserved: •...
Page 402 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 189. SCU clocking and power control Base clock Branch clock Operating frequency Clock to SCU register interface BASE_M4_CLK CLK_M4_SCU up to 204 MHz 17.3 General description The system control unit determines the function and electrical mode of most digital pins.
Page 403 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO 17.3.2 Digital pin mode The EPUN and EPD bits (see Figure 43) in the SFS registers allow the selection of weak on-chip pull-up or pull-down resistors with a typical value of 50 k for each pin or the selection of the repeater mode.
Page 404 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO 17.3.8 I C0-bus pins The SFSI2C0 register (Table 196) allows to configure different modes for I C0-bus interface: • Standard mode/Fast-mode I C with an open-drain output according to the I C-bus specification.
Page 405 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG P0_0 GPIO0[0] SSP1_MISO ENET_RXD1...
Page 406 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG P2_1 SGPIO5 U0_RXD EMC_A12...
Page 407 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG P4_5 GPIO2[5] CTOUT_5 LCD_FP...
Page 408 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG P6_12 GPIO2[8] CTOUT_7 EMC_DQMOU...
Page 409 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG PA_1 GPIO4[8] QEI_IDX U2_TXD...
Page 410 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG PD_3 CTOUT_6 EMC_D17 GPIO6[17]...
Page 411 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 190. Pin multiplexing FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG PE_15 CTOUT_0 I2C1_SCL EMC_CKEOUT...
Page 412 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO 17.4 Register description The system control unit contains the registers to configure the pin function of multiplexed digital pins, the EMC clock delays, and the GPIO pin interrupts. Remark: The boot loader configures the pins involved in the boot process (see Section 5.3.2) when the part starts up.
Page 413 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 191. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART boot...
Page 414 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 191. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART boot...
Page 415 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 191. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART boot...
Page 416 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 191. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART boot...
Page 417 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 191. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART boot...
Page 418 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 191. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART boot...
Page 419 4 to 7. 17.4.1 Pin configuration registers for normal-drive pins Each digital pin and each clock pin on the LPC43xx/LPC43Sxx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The pin configuration registers for normal-drive pins control the following pins: •...
Page 420 Reserved 17.4.2 Pin configuration registers for high-drive pins Each digital pin and each clock pin on the LPC43xx/LPC43Sxx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The assigned functions for each pin are listed in Table 190.
Page 421 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO • P8_0 to P8_2 • PA_1 to PA_3 Table 193. Pin configuration registers for high-drive pins (SFS, address 0x4008 60C4 (SFSP1_17) to 0x4008 650C (SFSPA_3) bit description Symbol Value...
Page 422 Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO 17.4.3 Pin configuration registers for high-speed pins Each digital pin and each clock pin on the LPC43xx/LPC43Sxx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The assigned functions for each pin are listed in Table 190.
Page 423 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 195. Pin configuration for pins USB1_DP/USB1_DM register (SFSUSB, address 0x4008 6C80) bit description Symbol Value Description Reset Access value USB_AIM Differential data input AIP/AIM. Going LOW with full speed edge rate...
Page 424 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO C-bus pins register (SFSI2C0, address 0x4008 Table 196. Pin configuration for open-drain I 6C84) bit description …continued Symbol Value Description Reset Access value SCL_EZI Enable the input receiver for the SCL pin.
Page 425 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 197. Pins controlled by the ENAIO0 register ADC function ENAIO0 register bit P4_3 ADC0_0 P4_1 ADC0_1 PF_8 ADC0_2 P7_5 ADC0_3 P7_4 ADC0_4 PF_10 ADC0_5 PB_6 ADC0_6 By default, all pins are connected to their digital function 0 and only the digital pad is available.
Page 426 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 198. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description Symbol Value Description Reset Access value ADC0_6 Select ADC0_6 Digital function selected on pin PB_6. Analog function ADC0_6 selected on pin PB_6.
Page 427 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 200. ADC1 function select register (ENAIO1, address 0x4008 6C8C) bit description Symbol Value Description Reset Access value ADC1_0 Select ADC1_0 Digital function selected on pin PC_3. Analog function ADC1_0 selected on pin PC_3.
Page 428 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO To select the analog function, the pad must be set as follows using the corresponding SFSP register: 1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in input mode.
Page 429 17.4.10 SD/MMC delay register This register provides a programmable delay for the SD/MMC sample and drive inputs and outputs. See the LPC43xx/LPC43Sxx data sheets for recommended settings. Typical setting for SD cards are SAMPLE_DELAY = 0x8 and DRV_DELAY = 0xF.
Page 430 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 205. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description Symbol Value Description Reset value INTPIN0 Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register.
Page 431 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 205. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description Symbol Value Description Reset value 31:29 PORTSEL3 Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.
Page 432 UM10503 NXP Semiconductors Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO Table 206. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description Symbol Value Description Reset value 15:13 PORTSEL5 Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.
Page 433 UM10503 Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Rev. 2.1 — 10 December 2015 User manual 18.1 How to read this chapter Remark: The ADCHS block is only available on the LPC4370. 18.2 Basic configuration The GIMA is configured as follows: •...
Page 434 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) • SCT outputs • I2S0/1 MWS signal • USART0/2/3 RX/TX active signal • USB0/1 SOF signal The following peripheral functions are connected to GIMA outputs: • Timer0/1/2/3 capture inputs •...
Page 435 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 208. GIMA outputs GIMA GIMA output GIMA inputs Reference output connected to T0 capture channel 0 pin CTIN_0 SGPIO3 pin T0_CAP0 Table 211 T0 capture channel 1 pin CTIN_1...
Page 436 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 208. GIMA outputs GIMA GIMA output GIMA inputs Reference output connected to Event router input 14 SCT output 6 or T1 SGPIO12 T1 match Table 237 match channel 2...
Page 437 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) • GIMA outputs 16 to 23: BASE_M4_CLK using SCT branch clock. • GIMA outputs 24: BASE_ADCHS_CLK • GIMA outputs 25 to 27: no synchronization clock required because the event router can capture a signal with edge or level sensitivity.
Page 438 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 210. Register overview: GIMA (base address: 0x400C 7000) Name Access Address Description Reset Reference offset value CAP0_3_IN 0x00C Timer 0 CAP0_3 capture input multiplexer (GIMA Table 214 output 3)
Page 439 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 210. Register overview: GIMA (base address: 0x400C 7000) Name Access Address Description Reset Reference offset value EVENTROUTER_16_IN 0x06C Event router input 16 multiplexer (GIMA output 27) Table 238...
Page 440 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 212. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
Page 441 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.4 Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN) Table 214. Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN, address 0x400C 700C) bit description Symbol Value Description Reset value Invert input Not inverted.
Page 442 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 215. Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN, address 0x400C 7010) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTIN_0...
Page 443 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 217. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
Page 444 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.9 Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN) Table 219. Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN, address 0x400C 7020) bit description Symbol Value Description Reset value Invert input Not inverted.
Page 445 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 220. Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN, address 0x400C 7024) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. CTIN_1...
Page 446 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 222. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled.
Page 447 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.14 Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN) Table 224. Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN, address 0x400C 7034) bit description Symbol Value Description Reset value Invert input Not inverted.
Page 448 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 225. Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN, address 0x400C 7038) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. 0...
Page 449 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 227. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled.
Page 450 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.19 SCT CTIN_2 capture input multiplexer (CTIN_2_IN) Table 229. SCT CTIN_2 capture input multiplexer (CTIN_2_IN, address 0x400C 7048) bit description Symbol Value Description Reset value Invert input Not inverted.
Page 451 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 230. SCT CTIN_3 capture input multiplexer (CTIN_3_IN, address 0x400C 704C) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. CTIN_3 USART0 TX active...
Page 452 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 232. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
Page 453 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.24 SCT CTIN_7 capture input multiplexer (CTIN_7_IN) Table 234. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit description Symbol Value Description Reset value Invert input Not inverted.
Page 454 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) Table 235. ADCHS trigger input multiplexer (ADCHS_TRIGGER_IN, address 0x400C 7060) bit description …continued Symbol Value Description Reset value SELECT Select input. Values 0xA to 0xF are reserved. GPIO6[28] GPIO5[3]...
Page 455 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.27 Event router input 14 multiplexer (EVENTROUTER_14_IN) Table 237. Event router input 14 multiplexer (EVENTROUTER_14_IN, address 0x400C 7068) bit description Symbol Value Description Reset value Invert input Not inverted.
Page 456 UM10503 NXP Semiconductors Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA) 18.4.29 ADC start0 input multiplexer (ADCSTART0_IN) Table 239. ADC start0 input multiplexer (ADCSTART0_IN, address 0x400C 7070) bit description Symbol Value Description Reset value Invert input Not inverted. Input inverted.
Page 457 UM10503 Chapter 19: LPC43xx/LPC43Sxx GPIO Rev. 2.1 — 10 December 2015 User manual 19.1 How to read this chapter All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO...
Page 458 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.3 Features 19.3.1 GPIO pin interrupt features • Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC.
Page 459 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.4.3 GPIO port The GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output.
Page 460 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.5 Register description The GPIO consists of the following blocks: • The GPIO pin interrupts block at address 0x4008 7000. Registers in this block enable the up to 8 pin interrupts selected in the PINTSELn registers (see...
Page 461 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 244. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000) Name Access Address Description Reset value Reference offset PORT_POL4 R/W 0x030 GPIO grouped interrupt port 4 polarity register 0xFFFF FFFF Table 258...
Page 462 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 246. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 241). Name Access Address Description Reset Width Reference offset value...
Page 463 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 246. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 241). Name Access Address Description Reset Width Reference offset value...
Page 464 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 246. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 241). Name Access Address Description Reset Width Reference offset value...
Page 465 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.5.1.3 Pin interrupt level (rising edge) interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 205 Table 206), one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register: •...
Page 466 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 251. Pin interrupt active level (falling edge) interrupt enable register (IENF, address 0x4008 7010) bit description Symbol Description Reset Access value ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt.
Page 467 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 253. Pin interrupt active level (falling edge) interrupt clear register (CIENF, address 0x4008 7018) bit description Symbol Description Reset Access value CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts.
Page 468 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.5.1.10 Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones to this register clears both rising- and falling-edge detection for the pin. For level-sensitive pins, writing ones inverts the corresponding bit in the Active level register, thus switching the active level on the pin.
Page 469 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 258. GPIO grouped interrupt port polarity registers (PORT_POL, addresses 0x4008 8020 (PORT_POL0) to 0x4008 803C (PORT_POL7) (GROUP0 INT) and 0x4008 9020 (PORT_POL0) to 0x4008 903C (PORT_POL7) (GROUP1 INT)) bit description Symbol Description...
Page 470 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Table 260. GPIO port byte pin registers (B, addresses 0x400F 4000 (B0) to 0x400F 00FC (B255)) bit description Symbol Description Reset Access value PBYTE Read: state of the pin GPIOn[m], regardless of direction, masking, or alternate function.
Page 471 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.5.3.4 GPIO port mask registers Each GPIO port has one mask register. The mask registers affect writing and reading the MPORT registers. Zeroes in these registers enable reading and writing; ones disable writing and result in zeros in corresponding positions when reading.
Page 472 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO 19.5.3.7 GPIO port set registers Each GPIO port has one port set register. Output bits can be set by writing ones to these registers, regardless of MASK registers. Reading from these register returns the port’s output bits, regardless of pin directions.
Page 473 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO • The state of a single pin can be read in all bits of a byte, halfword, or word from a Word Pin register. • The state of multiple pins in a port can be read as a byte, halfword, or word from a PORT register.
Page 474 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO Applications in which interrupts can result in Masked GPIO operation, or in task switching among tasks that do Masked GPIO operation, must treat code that uses the Mask register as a protected/restricted region. This can be done by interrupt disabling or by using a semaphore.
Page 475 UM10503 NXP Semiconductors Chapter 19: LPC43xx/LPC43Sxx GPIO The raw interrupt request from each of the two group interrupts is sent to the NVIC, which can be programmed to treat it as level- or edge-sensitive (see Table 78). 19.6.5 Recommended practices The following lists some recommended uses for using the GPIO port registers: •...
Page 476 Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Rev. 2.1 — 10 December 2015 User manual 20.1 How to read this chapter The SGPIO is available on all LPC43xx/LPC43Sxx parts. 20.2 Basic configuration The SGPIO is configured as follows: • Table 270 for clocking and power control.
Page 477 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.4 General description Serial GPIO (SGPIO) offer standard GPIO functionality enhanced with features to accelerate serial stream processing. A data stream on a single SGPIO input or output or on a dual, quad, and byte lane data input/output is processed by using so called slices. Up to 16 slices are supported, and all 16 slices have the same basic feature set with some slices offering additional features.
Page 478 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) – Output clock polarity can be inverted. • Interface – The register memory map supports use of ARM Store Multiple and Load Multiple instructions. Slice functions that control the same features are mapped in consecutive registers.
Page 479 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.5 Pin description Table 271. SGPIO pin description Pin function Direction Description SGPIO[15:0] Serial GPIO input/output UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Page 480 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6 Register description Table 272. Register overview: SGPIO (base address 0x4010 1000) Name Access Address offset Description Reset Reference value OUT_MUX_CFG0 to 0x0000 to 0x003C Pin multiplexer configuration registers. Table 273...
Page 481 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 272. Register overview: SGPIO (base address 0x4010 1000) Name Access Address offset Description Reset Reference value SET_EN_2 0x0F44 Pattern match interrupt set mask Table 306 ENABLE_2 0x0F48 Pattern match interrupt enable...
Page 482 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 273. Pin multiplexer configuration registers (OUT_MUX_CFG[0:15], addresses 0x4010 1000 (OUT_MUX_CFG0) to 0x4010 103C (OUT_MUX_CFG15)) bit description Symbol Value Description Reset Access value P_OUT_CFG Output control of output SGPIOn. All other values are reserved.
Page 483 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 274. Output pin multiplexing SGPIO pin Output mode - register OUT_MUX_CFG, bits P_OUT_CFG (see Table 273) 1011 1010 1001 0111 0110 0101 0011 0010 0001 0000 1000 0100 8-bit 8c 8-bit 8b 8-bit 8a 4-bit 4c 4-bit 4b 4-bit 4a 2-bit 2c 2-bit 2b 2-bit 2a 1-bit...
Page 484 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) dout _doutm1 0000 dout _doutm2 00xx GP IO_RE G 0100 01xx dout dout _doutm4 clk_out 1000 dout _doutm8 10xx reserved 11xx p_out_cfg OUT_MUX _CFGx p_oe_cfg p_oe_cfg dout_oem1 dout_oem2 dout_oem4 dout_oem8 GP IO _OE RE G Fig 46.
Page 485 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 276. SGPIO multiplexer configuration registers (SGPIO_MUX_CFG[0:15], addresses 0x4010 0040 (SGPIO_MUX_CFG0) to 0x4010 007C (SGPIO_MUX_CFG15)) bit description …continued Symbol Value Description Reset Access value CLK_SOURCE_PIN Select source clock pin. _MODE SGPIO8...
Page 486 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 277 defines the input slice configuration for slices A through P. The concatenation order and the concatenation rules determine which slice becomes the input slice to slices A through P. See Section 20.7.2...
Page 487 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 278 for connecting slice data to pins for the various setting of bits PARALLEL_MODE. Table 278. Slice multiplexer configuration registers (SLICE_MUX_CFG[0:15], addresses 0x4010 1080 (SLICE_MUX_CFG0) to 0x4010 10BC (SLICE_MUX_CFG15)) bit...
Page 488 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) At an active shift clock data is right shifted; captured data is shifted in at bit 31, and register data is shifted out from bit 0. Table 279. Slice data registers (REG[0:15], addresses 0x4010 10C0 (REG0) to 0x4010 10FC...
Page 489 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 282. Down counter registers (COUNT[0:15], addresses 0x4010 1180 (COUNT0) to 0x4010 11BC (COUNT15)) bit description Symbol Description Reset Access value 11:0 COUNT Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET.
Page 490 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6.11 Slice I mask register Table 286. Slice I mask register (MASK_I, address 0x4010 1208) bit description Symbol Description Reset Access value 31:0 MASK_I Mask for pattern match function of slice I 0 = No effect.
Page 491 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6.15 GPIO output enable register Table 290. GPIO output enable register (GPIO_OENREG, address 0x4010 1218) bit description Symbol Description Reset Access value 15:0 GPIO_OE Bit i selects the output enable state of SGPIO pin 0 = GPIO output i is tri-stated.
Page 492 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 293. Shift clock interrupt clear mask register (CLR_EN_0, address 0x4010 1F00) bit description Symbol Description Reset Access value 15:0 CLR_SCI 1 = Shift clock interrupt clear mask of slice n.
Page 493 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6.23 Shift clock interrupt set status register This register sets the shift clock interrupt of a slice. Table 298. Shift clock interrupt set status register (SET_STATUS_0, address 0x4010 1F14) bit description...
Page 494 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6.27 Exchange clock interrupt status register The STATUS_1 register bits are set when the shadow and data registers are exchanged. The bits in this registers are set independently of the value of the corresponding ENABLE_1 bits.
Page 495 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6.32 Pattern match interrupt enable Table 307. Pattern match interrupt enable register (ENABLE_2, address 0x4010 1F48) bit description Symbol Description Reset Access value 15:0 ENABLE_PMI Match interrupt enable of slice n.
Page 496 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.6.37 Input bit match interrupt set mask register Table 312. Input interrupt set mask register (SET_EN_3, address 0x4010 1F64) bit description Symbol Description Reset Access value 15:0 SET_EN_INPI 1 = Input interrupt set mask of slice n.
Page 497 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.7 Functional description Serial GPIO (SGPIO) offer standard GPIO functionality enhanced with features to accelerate serial stream processing. The enhanced features are made using so called slices. All 16 slices have the same basic feature set. Some slices offer additional features for pattern matching and processing 2-, 4- or 8-bit wide streams.
Page 498 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) POS_PRESET qualifier PRESET external clock SGPIO_ 8b POS counter CLOCK 12b COUNTer dout shift_clk in multi-lane modes in multi- lane modes output multiple MSBs input multiple LSBs dout from other slices...
Page 499 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.7.1 Example: input for slice A Figure 48, the input for slice A can be selected from the following choices: • Pin - if CONCAT_ENABLE bit = 0 in the SGPIO_MUX_CFG register (Table 276).
Page 500 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) (12) (13) (10) (14) (11) (15) Examples: 4 input slices concatenated 2 output slices selfloop E = external data input mode 8 = 8 slices concatenated mode 4 = 4 slices concatenated mode...
Page 501 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Four slices (A, H, I and P) also support masking the pattern; MASK_x must be set for the pattern bits to be compared (1 is compare). E.g. when looking for pattern 0x1234 XXXX, then REG should be set to 0x1234 XXXX and MASK to 0xFFFF 0000.
Page 502 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) c lk _s lic e D c lk _s lic e H c lk _s lic e O c lk_s lic e P c lk _in c lk _pin SGPIO8 c lk _pin SGPIO9...
Page 503 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 317. Slice I/O multiplexing x = external; cl = clock; q = qualifier SGPIO Pin Input mode Parallel mode 8-bit 4-bit 2-bit 1-bit Clock SGPIO SGPIO SGPIO SGPIO SGPIO SGPIO 20.7.6 Internal connections...
Page 504 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.8.1 Multi-channel I2S 20.8.1.1 I2S slice selection A 5.1 channel I2S output interface in master mode requires 3 data outputs (SD[2:0]), 1 word select output (WS) and 1 clock output (SCK). In slave mode SCK becomes an input.
Page 505 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) word n-1 word n word n+1 right channel left channel right channel Fig 52. I2S configuration 20.8.1.2 I2S slice configuration Using FS = 192 kHz and 32-bit audio samples provides the following parameters: •...
Page 506 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 322. SGPIO setting for I2S 5.1, SLICE_MUX_CFG register SLICE_MUX_CF A,I,E (i=0,8,4) J (i=9) B (i=1) D (i=3) match_mode 0: no 0: no 0: no 0: no clk_gen_mode 0: use COUNTER...
Page 507 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 324. SGPIO setting for I2S 5.1 (master mode, pin 8) PRESETi counter not used counter not used counter not used counter not used COUNTi counter not used counter not used...
Page 508 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) 20.8.2 Camera interface example The camera interface uses the following input signals: • DIN[0:7] Data inputs • HSYNC Horizontal synchronization input • VSYNC Vertical synchronization input • PIXCLX Pixel clock input...
Page 509 UM10503 NXP Semiconductors Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO) Table 328. SGPIO setting for camera interface (SGPIO_MUX_CFG registers) SGPIO_MUX_CFGi A...L M (i=12) G (i=6) ext_clk_enable 1=pin 1=pin 1=pin clk_source_pin_mode 00=Pin 8 00=Pin 8 00=Pin 8 qualifier_mode 11: external pin 00: enable...
Page 510 UM10503 Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) controller Rev. 2.1 — 10 December 2015 User manual 21.1 How to read this chapter The GPDMA is available on all LPC43xx/LPC43Sxxx parts. Remark: The ADCHS is available on parts LPC4370. Remark: The AES DMA request lines are only available on secure parts.
Page 511 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data.
Page 512 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 331. Peripheral connections to the DMA controller and matching flow control signals Peripheral SREQ BREQ Number muxing option (see Table 101) SPIFI SPIFI SCT CTOUT_2 SGPIO14 Timer3 match 1...
Page 513 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 331. Peripheral connections to the DMA controller and matching flow control signals Peripheral SREQ BREQ Number muxing option (see Table 101) SSP0 receive SSP0 receive I2S0 DMA request 1...
Page 514 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) SREQ[15:0] — Single transfer request signals. These cause a single data to be transferred. The DMA controller transfers a single transfer to or from the peripheral. LBREQ[15:0] — Last burst request signals.
Page 515 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 332. Register overview: GPDMA (base address 0x4000 2000) …continued Name Access Address Description Reset value Reference offset SRCADDR0 0x100 DMA Channel 0 Source Address Register 0x0000 0000 Table 347...
Page 516 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 332. Register overview: GPDMA (base address 0x4000 2000) …continued Name Access Address Description Reset value Reference offset CONFIG6 0x1D0 DMA Channel 6 Configuration Register 0x0000 0000 Table 351 Channel 7 registers...
Page 517 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.6.3 DMA Interrupt Terminal Count Request Clear Register The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt requests. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register (IntTCStat) to be cleared.
Page 518 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 337. DMA Interrupt Error Clear Register (INTERRCLR, address 0x4000 2010) bit description Symbol Description Reset Access value INTERRCLR Writing a 1 clears the error interrupt request (IntErrStat) 0x00 for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect.
Page 519 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.6.8 DMA Enabled Channel Register The ENBLDCHNS Register is read-only and indicates which DMA channels are enabled, as indicated by the Enable bit in the CCONFIG Register. A HIGH bit indicates that a DMA channel is enabled.
Page 520 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 342. DMA Software Single Request Register (SOFTSREQ, address 0x4000 2024) bit description Symbol Description Reset Access value 15:0 SOFTSREQ Software single transfer request flags for each of 16 0x00 possible sources.
Page 521 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 344. DMA Software Last Single Request Register (SOFTLSREQ, address 0x4000 202C) bit description Symbol Description Reset Access value 15:0 SOFTLSREQ Software last single transfer request flags for each of 0x00 16 possible sources.
Page 522 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 346. DMA Synchronization Register (SYNC, address 0x4000 2034) bit description Symbol Description Reset Access value 15:0 DMACSYNC Controls the synchronization logic for DMA request 0x00 signals. Each bit represents one set of DMA request...
Page 523 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.6.17 DMA Channel Destination Address registers The eight read/write DESTADDR Registers contain the current destination address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the channel is enabled. When the DMA channel is enabled the register is updated as the destination address is incremented and by following the linked list when a complete packet of data has been transferred.
Page 524 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 350. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description Symbol Value Description Reset Access value 11:0 TRANSFERSIZE Transfer size in number of transfers. A write to this field sets the size of the transfer when the DMA Controller is the flow controller.
Page 525 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 350. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description …continued Symbol Value Description Reset Access value 20:18 SWIDTH Source transfer width. Transfers wider than the AHB master bus width are illegal.
Page 526 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 350. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description …continued Symbol Value Description Reset Access value Terminal count interrupt enable bit. The terminal count interrupt is disabled.
Page 527 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 351. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value SRCPERIPHERAL Source peripheral. This value selects the DMA source request peripheral.
Page 528 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 351. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value 10:6 DESTPERIPHERAL Destination peripheral. This value selects the DMA destination request peripheral.
Page 529 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 351. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value Active: 0 = there is no data in the FIFO of the channel.
Page 530 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.7 Functional description 21.7.1 DMA controller functional description The DMA Controller enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive.
Page 531 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit quantities. This means that when performing mixed-endian activity, where the endianness of the source and destination are different, byte swapping of the data within the 32-bit data bus is observed.
Page 532 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Table 353. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[31:0] 87654321...
Page 533 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.7.1.6.3 Error conditions An error during a DMA transfer is flagged directly by the peripheral by asserting an Error response on the AHB bus during the transfer. The DMA Controller automatically disables the DMA stream after the current transfer has completed, and can optionally generate an error interrupt to the CPU.
Page 534 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.8.1.4 Disabling a DMA channel A DMA channel can be disabled in three ways: • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used.
Page 535 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 21.8.2 Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMA Controller where the packet length is programmed by software before the DMA channel is enabled.
Page 536 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 1. Program and enable the DMA channel. 2. Wait for a DMA request. 3. The DMA Controller starts transferring data when: – The DMA request goes active. – The DMA stream has the highest pending priority.
Page 537 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) – The DMA Controller responds with a DMA acknowledge to the destination peripheral. – The terminal count interrupt is generated (this interrupt can be masked). – If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI, and CCONTROL Registers and go to back to step 2.
Page 538 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 4. For a terminal count interrupt, write a 1 to the relevant bit of the INTTCCLR Register. For an error interrupt write a 1 to the relevant bit of the INTERRCLR Register to clear the interrupt request.
Page 539 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) 3. CLLI 4. CCONTROL Note: The CCONFIG DMA channel Configuration Register is not part of the linked list item. 21.8.5.1.1 Programming the DMA controller for scatter/gather DMA To program the DMA Controller for scatter/gather DMA: 1.
Page 540 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) Linked List Array LLI 1 Source address 0x2000 A200 0x2000 0000 0x2000 A200 Destination address = peripheral 0x2000 0010 Next LLI address Control information = length 3072 3072 bytes of data...
Page 541 UM10503 NXP Semiconductors Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA) • Source and destination burst sizes, 16 transfers. • Next LLI address, 0x2000 0020. A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x2000 0000, is programmed into the DMA Controller.
Page 542 Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Rev. 2.1 — 10 December 2015 User manual 22.1 How to read this chapter The SD/MMC card interface is available on all LPC43xx/LPC43Sxx parts. 22.2 Basic configuration The SD/MMC interface is configured as follows: •...
Page 543 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.4 General description The SD/MMC controller interface consists of the following main functional blocks: • Bus Interface Unit (BIU) - Provides AHB and DMA interfaces for register and data read/writes. • Card Interface Unit (CIU) - Handles the card protocols and provides clock management.
Page 544 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 356. SD/MMC pin description Pin function Direction Description SD_LED LED On signal. This signal cautions the user not to remove the SD card while it is accessed. SD_CMD Command input/output SD_D[7:0]...
Page 545 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 357. Register overview: SDMMC (base address: 0x4000 4000) Name Access Address Description Reset value Reference offset TBBCNT 0x060 Transferred Host to BIU-FIFO Byte Count Table 381 Register DEBNCE 0x064 Debounce Count Register...
Page 546 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 358. Control Register (CTRL, address 0x4000 4000) bit description Symbol Value Description Reset value DMA_RESET Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.
Page 547 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 358. Control Register (CTRL, address 0x4000 4000) bit description Symbol Value Description Reset value SEND_AUTO_STOP_ Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and CCSD send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd.
Page 548 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.2 Power Enable Register Table 359. Power Enable Register (PWREN, address 0x4000 4004) bit description Symbol Description Reset value POWER_ENABLE Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.
Page 549 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.4 SD Clock Source Register Table 361. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description Symbol Description Reset value CLK_SOURCE Clock divider source for SD card. 00 - Clock divider 0...
Page 550 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.7 Card Type Register Table 364. Card Type Register (CTYPE, address 0x4000 4018) bit description Symbol Description Reset value CARD_WIDTH0 Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode...
Page 551 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 367. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description Symbol Description Reset value TXDR Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.
Page 552 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.12 Command Register Table 369. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value CMD_INDEX Command index RESPONSE_EXPECT Response expect None. No response expected from card Expected. Response expected from card...
Page 553 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 369. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value STOP_ABORT_CMD Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state.
Page 554 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 369. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value CCS_EXPECTED CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit.
Page 555 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.14 Response Register 1 Table 371. Response Register 1 (RESP1, address 0x4000 4034) bit description Symbol Description Reset value 31:0 RESPONSE1 Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register.
Page 556 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 374. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description Symbol Description Reset value DRTO Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.
Page 557 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 375. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description Symbol Description Reset value RCRC Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
Page 558 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.19 Status Register Table 376. Status Register (STATUS, address 0x4000 4048) bit description Symbol Description Reset value FIFO_RX_ FIFO reached Receive watermark level; not qualified with data transfer. WATERMARK FIFO_TX_ FIFO reached Transmit watermark level; not qualified with data transfer.
Page 559 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.20 FIFO Threshold Watermark Register Table 377. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Symbol Value Description Reset value 11:0 TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised.
Page 560 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 377. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Symbol Value Description Reset value 30:28 DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter.
Page 561 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.23 Transferred CIU Card Byte Count Register Table 380. Transferred CIU Card Byte Count Register (TCBCNT, address 0x4000 405C) bit description Symbol Description Reset value Number of bytes transferred by CIU unit to card.
Page 562 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.27 Bus Mode Register Table 384. Bus Mode Register (BMOD, address 0x4000 4080) bit description Symbol Value Description Reset value Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write.
Page 563 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.6.29 Descriptor List Base Address Register Table 386. Descriptor List Base Address Register (DBADDR, address 0x4000 4088) bit description Symbol Description Reset value 31:0 Start of Descriptor List. Contains the base address of the First Descriptor.
Page 564 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 387. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description Symbol Description Reset value 12:10 EB Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.
Page 565 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 388. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit description Symbol Description Reset value Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled.
Page 566 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface The card detection signal is debounced based on the number of blocks specified in the Debounce Count Register (DEBNCE). When this signal is connected to the card detect pin of the card slot, then CDETECT register's bit 0 state will be filtered by the number of debounce cycles specified in DEBNCE.
Page 567 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface The condition under which the transfer mode is set to block transfer and byte_count is equal to block size is treated as a single-block data transfer command for both MMC and SD cards. If byte_count = n...
Page 568 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Before issuing a new data transfer command, the software should ensure that the card is not busy due to any previous data transfer command. Before changing the card clock frequency, the software must ensure that there are no data or command transfers in progress.
Page 569 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface One data-transfer requirement between the FIFO and cpu is that the number of transfers should be a multiple of the FIFO data width (F_DATA_WIDTH), which is 32. So if you want to write only 15 bytes to an SD/MMC/CE-ATA card (BYTCNT), the cpu should write 16 bytes to the FIFO or program the DMA to do 16-byte transfers, if DMA mode is enabled.
Page 570 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • Enumerates all connected cards • Sets the RCA for the connected cards • Reads card-specific information • Stores card-specific information locally Enumerate_Card_Stack - Enumerates the card connected on the module. The card can be of the type MMC, CE-ATA, SD, or SDIO.
Page 571 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • CLKDIV @0x08 = 0x0 (bypass of clock divider). • CLKSRC @0x0C = 0x0 • CLKENA @0x10 =0x0 or 0x1. This register enables or disables clock for the card and enables low-power mode, which automatically stops the clock to a card when the card is idle for more than 8 clocks.
Page 572: Start_Cmd
UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface – Check if response_timeout error, response_CRC error, or response error is set. This can be done either by responding to an interrupt raised by these errors or by polling bits 1, 6, and 8 from the RINTSTS register @0x44. If no response error is received, then the response is valid.
Page 573 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface For the data transfer commands, it is important that the same bus width that is programmed in the card should be set in the card type register @0x18. Therefore, in order to change the bus width, you should always use the following supplied APIs as appropriate for the type of card: •...
Page 574: Transfer_Mode
UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 5. Software should look for Receive_FIFO_Data_request and/or data starvation by cpu time-out conditions. In both cases, the software should read data from the FIFO and make space in the FIFO for receiving more data.
Page 575 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 3. Program CMDARG register @0x28 with the data address to which data should be written. 4. Write data in the FIFO; it is usually best to start filling data the full depth of the FIFO.
Page 576: User-Selectable Wait_Prvdata_Complete
UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 394. CMD register settings for Single-block or Multiple-block write Name Value Comments User-selectable Wait_prvdata_complete Before sending command on command line, cpu should wait for completion of any data command in process, if any (recommended to...
Page 577 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • Send STOP command - Can be sent on the command line while a data transfer is in progress; this command can be sent at any time during a data transfer. For information on sending this command, refer to "No-Data Command With or Without...
Page 578 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface The following functions can be implemented by programming the appropriate bits in the CCCR register (Function 0) of the SDIO card. To read from or write to the CCCR register, use the CMD52 command.
Page 579 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface If the DF flag is 0, then in case of a read, the Module waits for data. After the data time-out period, it gives a data time-out error. Table 396. Parameters for CMDARG register...
Page 580 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.7.5.2.2 ATA Task File Transfer ATA task file registers are mapped to addresses 0x00h-0x10h in the MMC register space. RW_REG is used to issue the ATA command, and the ATA task file is transmitted in a single RW_REG MMC command sequence.
Page 581: Comment
UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 398. CMD register settings Name Value Comment start_cmd Css_expect Command Completion Signal is not expected Read_ceata_device 1 – If RW_BLK or RW_REG read update_clock_ registers_only No clock parameters update command card_number Card number in use.
Page 582 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 1. Write the data size in bytes in the BYTCNT register @0x20. 2. Write the block size in bytes in the BLKSIZ register @0x1C. The Module expects a single/multiple block transfer. 3. Program the CMDARG register @0x28 to indicate the Data Unit Count.
Page 583 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • Program the block size (BLKSIZ) register as shown below. Table 403. BLKSIZ register Bits Value Comment 31:16 Reserved bits as zeroes (0) 15:0 512, 1024, 4096 MMC block size can be 512, 1024, or 4096 bytes as negotiated by CPU •...
Page 584 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • IDENTIFY DEVICE - Returns 512-byte data structure to the cpu that describes device-specific information and capabilities. The cpu issues the IDENTIFY DEVICE command only if the MMC block size is set to 512 bytes; any other MMC block size has indeterminate results.
Page 585 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface – Command field of the ATA task file set to E0h – Reserved fields of the task file cleared to 0 • BLKSIZ register bits [15:0] and BYTCNT register - Set to 16 –...
Page 586 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • Generic DMA mode - Simultaneously sets controller_reset, fifo_reset, and dma_reset; clears the RAWINTS register @0x44 by using another write in order to clear any resultant interrupt. If a "graceful" completion of the DMA is required, then it is recommended to poll the status register to see whether the dma request is 0 before resetting the DMA interface control and issuing an additional FIFO reset.
Page 587 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • CRC Error on Command - If a CRC error is detected for a command, the CE-ATA device does not send a response, and a response time-out is expected from the Module. The ATA layer is notified that an MMC transport layer error occurred.
Page 588 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Data Buffer Descriptor A Data Buffer Descriptor B Data Buffer Descriptor C Fig 58. Chain descriptor structure 22.7.6.1 SD/MMC DMA descriptors 22.7.6.1.1 SD/MMC DMA descriptor DESC0 The DES0 descriptor contains control and status information.
Page 589 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 405. SD/MMC DMA DESC0 descriptor Symbol Description 29:6 Reserved Card Error Summary These error bits indicate the status of the transaction to or from the card. These bits are also present in RINTSTS Indicates the logical OR of the following bits: •...
Page 590 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface Table 408. SD/MMC DMA DESC3 descriptor Symbol Description 31:0 BAP2 Buffer Address Pointer 2/ Next Descriptor Address These bits indicate the physical address of the second buffer when the dual-buffer structure is used. If the Second Address Chained (DES0[4]) bit is set, then this address contains the pointer to the physical memory where the Next Descriptor is present.
Page 591 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 22.7.6.6 Transmission The SD/MMC transmission occurs as follows: 1. The Host sets up the Descriptor (DES0-DES3) for transmission and sets the OWN bit (DES0[31]). The Host also prepares the data buffer. 2. The Host programs the write data command in the CMD register in BIU.
Page 592 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface 7. The SD/MMC DMA engine will now wait for a DMA interface request (dw_dma_req) from BIU. This request will be generated based on the programmed receive threshold value. For the last bytes of data which can’t be accessed using a burst, SINGLE transfers are performed on AHB.
Page 593 UM10503 NXP Semiconductors Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface • In case of a write abort, only the current descriptor during which an abort occurred is closed by the SD/MMC DMA . The remaining unread descriptors are not closed by the IDMAC.
Page 594 (EMC) Rev. 2.1 — 10 December 2015 User manual 23.1 How to read this chapter The EMC is available on all LPC43xx/LPC43Sxx parts. The memory and address bus widths depend on package size (see Table 410). Table 410. EMC pinout for different packages...
Page 595 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) • Program the SDRAM Delay value for the EMC_CLKn lines in the EMCDELAYCLK register in the SCU block. (See Section 17.4.9.). Add the SDRAM delay for most SDRAM devices running at frequencies above 96 MHz under typical conditions. Add the SDRAM delay at any frequency to compensate for variations over temperature.
Page 596 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) • Read and write buffers to reduce latency and to improve performance. • Separate reset domains allow the for auto-refresh through a chip reset if desired. • Programmable delay elements allow to fine-tune the EMC timing.
Page 597 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Lower priority requests are only serviced when no higher priority requests are active. Same priority requests are serviced in turn (round-robin arbitration). Static memories are mapped below 0x2000 0000. This memory area is addressed by the M4 I/D-bus.
Page 598 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 412. Memory bank selection Chip select pin Address range Memory type Size of range EMC_CS3 0x1F00 0000 - 0x1FFF FFFF Static 16 MB EMC_DYCS0 0x2800 0000 - 0x2FFF FFFF...
Page 599 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 414. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot 0x00C - Reserved. 0x01C DYNAMICCONTROL 0x020 Controls dynamic memory operation.
Page 600 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 414. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot DYNAMICCONFIG2 0x140 Selects the configuration information for Table 433 dynamic memory chip select 2.
Page 601 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 414. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot STATICWAITTURN1 0x238 Selects the number of bus turnaround Table 442 cycles for chip select 1.
Page 602 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 415. EMC Control register (CONTROL, address 0x4000 5000) bit description Symbol Value Description Reset value EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed.
Page 603 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 416. EMC Status register (STATUS, address 0x4000 5004) bit description Symbol Value Description Reset value Self-refresh acknowledge. This bit indicates the operating mode of the EMC: Normal mode. Self-refresh mode. (POR reset value.)
Page 604 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 418. Dynamic Control register (DYNAMICCONTROL, address 0x4000 5020) bit description Symbol Value Description Reset value Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions.
Page 605 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) While the EMC is running, the refresh cycle time can be adjusted to compensate for a changing EMC_CCLK frequency. The EMC controller might skip one refresh cycle in this case.
Page 606 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 420. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG, address 0x4000 5028) bit description Symbol Value Description Reset value Read data strategy. Do not use. POR reset value. Command delayed by 1/2 EMC_CCLK.
Page 607 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) 23.7.9 Dynamic Memory Self Refresh Exit Time register This register enables you to program the self-refresh exit time, tSREX. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions.
Page 608 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 425. Dynamic Memory Data In to Active Command Time register (DYNAMICDAL, address 0x4000 5040) bit description Symbol Description Reset value TDAL Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles.
Page 609 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) 23.7.14 Dynamic Memory Auto-refresh Period register This register enables you to program the auto-refresh period, and auto-refresh to active command period, tRFC. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions.
Page 610 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 430. Dynamic Memory Active Bank A to Active Bank B Time register (DYNAMICRRD, address 0x4000 5054) bit description Symbol Description Reset value TRRD Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
Page 611 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) For example, for a static memory read/write transfer time of 16 µs, and a EMC_CCLK frequency of 50 MHz, the following value must be programmed into this register: (16 x 10...
Page 612 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Address mappings that are not shown in Table 434 are reserved. Table 434. Address mapping 11:9 8:7 Description 16 bit external bus high-performance address mapping (Row, Bank, Column) 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9...
Page 613 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 434. Address mapping …continued 11:9 8:7 Description 32 bit external bus address mapping (Bank, Row, Column) 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9...
Page 614 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 435. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS[0:3], address 0x4000 5104 (DYNAMICRASCAS0) to 0x4000 5164 (DYNAMICRASCAS3)) bit description Symbol Value Description Reset value RAS latency (active to read/write delay). Reserved.
Page 615 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 436. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200 (STATICCONFIG0) to 0x4000 5260 (STATICCONFIG3)) bit description Symbol Value Description Reset value Reserved, user software should not write ones to reserved bits.
Page 616 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) 23.7.22 Static Memory Write Enable Delay registers These registers enable you to program the delay from the chip select to the write enable. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions.
Page 617 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 439. Static Memory Read Delay registers (STATICWAITRD[0:3], address 0x4000 520C (STATICWAITRD0) to 0x4000 526C (STATICWAITRD3)) bit description Symbol Description Reset value WAITRD Non-page mode read wait states or asynchronous page mode read first 0x1F access wait state.
Page 618 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 441. Static Memory Write Delay registers (STATICWAITWR[0:3], address 0x4000 5214 (STATICWAITWR0) to 0x4000 5274 (STATICWAITWR3)) bit description Symbol Description Reset value WAITWR Write wait states. 0x1F SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time.
Page 619 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) 23.8 Functional description Figure 59 shows a block diagram of the EMC. The functions of the EMC blocks are described in the following sections: • AHB slave register interface. •...
Page 620 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) The EMC dynamic memory interface requires that all EMC_CLK signals are selected on the CLKn pins for 16-bit memory and for 32-bit memory. For static memory larger delays are defined by in steps of one EMC clock cycle by the STATICWAIT registers (see Section 23.7.22...
Page 621 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) • Buffer read requests from memory. Future read requests that hit the buffer read the data from the buffer rather than memory, reducing transaction latency. Convert all read transactions into quadword bursts on the external memory interface.
Page 622 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) Table 443. SDRAM mode register description Address line SDRAM mode Value Description register bit A2:A0 Burst length 1 (M3 = 0) 1 (M3 =1) 2 (M3 = 0) 2 (M3 =1)
Page 623 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) The read address is calculated as follows: • Determine the mode register content MODE: – For a single 16-bit external SDRAM chip set the burst length to 8. For a single 32-bit SDRAM chip set the burst length to 4.
Page 624 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) 23.8.6 External static memory interface External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding StaticConfig register). If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines.
Page 625 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) BLS[3] BLS[2] BLS[1] BLS[0] IO[31:0] D[31:0] A[a_m:0] A[a_b:2] c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 61. 32 bit bank external memory interfaces ( bits MW = 10) 23.8.6.2 16-bit wide memory bank connection...
Page 626 UM10503 NXP Semiconductors Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC) 23.8.6.3 8-bit wide memory bank connection IO[7:0] D[7:0] A[a_m:0] A[a_b:0] Fig 63. 8 bit bank external memory interface (bits MW = 00) UM10503 All information provided in this document is subject to legal disclaimers.
Page 627 Rev. 2.1 — 10 December 2015 User manual 24.1 How to read this chapter The SPIFI is available on all LPC43xx/LPC43Sxx parts. A software driver library is available on LPCware.com. Section 5.3.4.4 “SPIFI boot mode” for details on the SPIFI boot process.
Page 628 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) accesses by the processor and/or DMA channels. Erasure and programming are handled by simple sequences of commands. A software API available on LPCware.com provides set-up, programming, and erase functions. Many SPI flash devices use serial commands for device setup/initialization, and then move to dual or quad commands for normal operation.
Page 629 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) 24.6 Register description The SPIFI register interface supports word accesses. Table 447. Register overview: SPIFI (base address 0x4000 3000) Name Access Address Description Reset value Reference offset CTRL 0x000 SPIFI control register...
Page 630 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) Table 448. SPIFI control register (CTRL, address 0x4000 3000) bit description Symbol Value Description Reset value 26:24 - Reserved. PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.
Page 631 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) Table 449. SPIFI command register (CMD, address 0x4000 3004) bit description Symbol Value Description Reset value 13:0 DATALEN Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command.
Page 632 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) Table 449. SPIFI command register (CMD, address 0x4000 3004) bit description Symbol Value Description Reset value 23:21 FRAMEFORM This field controls the opcode and address fields. Reserved. Opcode. Opcode only, no address.
Page 633 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) 24.6.5 SPIFI cache limit register The SPIFI hardware includes caching of previously-accessed data to improve performance. Software can write an address within the device to this register, to prevent such caching at and above that address. After Reset this register contains the allocated size of the SPIFI memory area, so that all possible accesses are below that value and are thus cacheable.
Page 634 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) Writing to this register will be ignored when a command is in progress or while data has yet to be written or read from the FIFO for a command issued. Use the MCINIT bit of the Status register to verify that the hardware is in Memory mode.
Page 635 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) 24.6.8 SPIFI status register This register indicates the state of the SPIFI. Table 455. SPIFI status register (STAT, address 0x4000 301C) bit description Symbol Description Reset value MCINIT This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register.
Page 636 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) The SPI protocol avoids all issues of set-up and hold times between the clock and data lines by using half of the SCK period to transmit the data. For high clock speeds, it is necessary to sample read data using a feedback clock.
Page 637 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) SPIFI_CS SPIFI_SCK SPIFI_MOSI SPIFI_MISO Opcode 05, input data 02, SPI mode SPIFI_CS SPIFI_SCK IO3:0 IO3:0 driven IO3:0 driven by Master by Slave Opcode AF, input data BF 26 02, both fields quad mode Fig 65.
Page 638 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) Because the SPIFI is an AHB device, software or a DMA channel can read bytes, halfwords, or words from the flash region. Reads from the flash region are delayed by deasserting HREADY when necessary, until the requested bytes are available to be read.
Page 639 UM10503 NXP Semiconductors Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI) • DRQEN in the Control register is 1. • MCINIT is 0. • There are at least 4 bytes in the FIFO for a read operation, or at least 4 empty byte locations in the FIFO for a write/program operation.
Page 640 UM10503 Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Rev. 2.1 — 10 December 2015 User manual 25.1 How to read this chapter The USB0 Host/Device/OTG controller is available on parts LPC436x/LPC43S6x, LPC435x/LPC43S5x, LPC433x/LPC43S3x, and LPC432x. USB frame length adjustment is available for parts with on-chip flash only.
Page 641 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller • Supports auto USB 2.0 mode discovery. • Supports software HNP and SRP for OTG peripherals. • Supports power management • Supports six logical endpoints including one control endpoint for a total of 12 physical endpoints.
Page 642 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.4.3 USB acronyms and abbreviations Table 457. USB related acronyms Acronym Description Analog Transceiver Device Controller Driver device Endpoint Queue Head device Transfer Descriptor End Of Packet End Point Full Speed...
Page 643 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 458. Fixed endpoint configuration Logical Physical Endpoint type Direction endpoint endpoint Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Table 459. USB Packet size Endpoint type Speed Packet size (byte) Control Low-speed Full-speed...
Page 644 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 460. USB0 pin description Pin function Direction Description USB0_VBUS VBUS pin (power on USB cable). This pin includes an internal pull-down resistor of 64 kOhm (typical) ± 16 kOhm. For maximum load C = 6.5 uF and maximum...
Page 645 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 462. Register overview: USB0 OTG controller (register base address 0x4000 6000) Name Access Address Description Reset Reset value Reference offset value after USB0 boot 0x000 - Reserved 0x08F Device/host capability registers...
Page 646 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 462. Register overview: USB0 OTG controller (register base address 0x4000 6000) …continued Name Access Address Description Reset Reset value Reference offset value after USB0 boot BINTERVAL 0x174 Length of virtual frame...
Page 647 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Hardware reset or USBCMD RST bit = 1 IDLE MODE = 00 write 10 to USBMODE write 11 to USBMODE DEVICE HOST MODE = 10 MODE = 11 Fig 67. USB controller modes The following registers and register bits are used for OTG operations.
Page 648 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 463. System bus interface configuration register (SBUSCFG - address 0x4000 6090) bit description Symbol Value Description Access Reset value AHB_BRST The burst length used by the USB controller can be selected using these bits.
Page 649 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 465. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) …continued Symbol Description Reset Access value 15:12 N_CC Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller.
Page 650 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 468. DCCPARAMS (address 0x4000 6124) Symbol Description Reset value Access Device Endpoint Number. These bits are reserved and should be set to zero. Device Capable. Host Capable. 31:9 These bits are reserved and should be set to zero.
Page 651 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 469. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description …continued Symbol Value Description Access Reset value SUTW Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted.
Page 652 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 470. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Symbol Value Description Access Reset value Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the host/device controller when the reset process is complete.
Page 653 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 470. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Symbol Value Description Access Reset value Reserved. ASPE Asynchronous Schedule Park Mode Enable Park mode is disabled.
Page 654 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.6.4.1 Device mode Table 472. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB interrupt R/WC This bit is cleared by software writing a one to it.
Page 655 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 472. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB reset received R/WC This bit is cleared by software writing a one to it.
Page 656 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.6.4.2 Host mode Table 473. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB interrupt (USBINT) R/WC This bit is cleared by software writing a one to it.
Page 657 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 473. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued Symbol Value Description Reset Access value Not used by the Host controller. 11:9 Reserved.
Page 658 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 473. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued Symbol Value Description Reset Access value USB host periodic interrupt (USBHSTPERINT) R/WC This bit is cleared by software writing a one to it.
Page 659 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 474. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description …continued Symbol Description Reset Access value SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt.
Page 660 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 475. USB Interrupt register in host mode (USBINTR_H - address 0x4000 6148) bit description …continued Symbol Description Access Reset value Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold.
Page 661 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.6.6.2 Host mode This register is used by the host controller to index the periodic frame list. The register updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution.
Page 662 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 479. USB Device Address register in device mode (DEVICEADDR - address 0x4000 6154) bit description Symbol Value Description Reset Access value 23:0 Reserved USBADRA Device address advance Any write to USBADR are instantaneous.
Page 663 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 481. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 6158) bit description Symbol Description Reset Access value 10:0 Reserved 31:11 EPBASE31_11 Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 12 Queue Heads (QH).
Page 664 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 484. USB burst size register (BURSTSIZE - address 0x4000 6160) bit description - device/host mode Symbol Description Reset Access value RXPBURST Programmable RX burst length 0x10 This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
Page 665 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 485. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 6164) bit description Symbol Description Reset Access value TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.
Page 666 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.6.13 USB Endpoint NAK register (ENDPTNAK) 25.6.13.1 Device mode This register indicates when the device sends a NAK handshake on an endpoint. Each Tx and Rx endpoint has a bit in the EPTN and EPRN field respectively.
Page 667 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 488. USB Endpoint NAK Enable register (ENDPTNAKEN - address 0x4000 617C) bit description Symbol Description Reset Access value EPRNE Rx endpoint NAK enable 0x00 Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set.
Page 668 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 489. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Symbol Value Description Reset Access value Reserved Force port resume After the device has been in Suspended state for 5 ms or more, software must set this bit to one to drive resume signaling before clearing.
Page 669 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 489. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Symbol Value Description Reset Access value 19:16 PTC3_0 Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode.
Page 670 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.6.15.2 Host mode The host controller uses one port. The register is only reset when power is initially applied or in response to a controller reset. The initial conditions of the port are: •...
Page 671 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 490. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value Port disable/enable change R/WC For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification).
Page 672 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 490. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, Table 491.
Page 673 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 490. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on).
Page 674 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 490. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value WKOC Wake on over-current enable (WKOC_E) Disables the port to wake up on over-current events.
Page 675 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller The status inputs are debounced using a 1 msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the status input register or cause an OTG interrupt.
Page 676 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 492. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Symbol Value Description Reset Access value IDIS USB ID interrupt status R/WC This bit is set when a change on the ID input has been detected.
Page 677 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 492. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Symbol Value Description Reset Access value MS1E 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt.
Page 678 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 493. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved.
Page 679 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 494. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved.
Page 680 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 496. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 61B0) bit description Symbol Description Reset Access value PERB Prime endpoint receive buffer for physical OUT endpoints 5 to 0. R/WS...
Page 681 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 497. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description Symbol Description Reset Access value 15:6 Reserved 21:16 FETB Flush endpoint transmit buffer for physical IN endpoints 5 to 0.
Page 682 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Writing a one will clear the corresponding bit in this register. Table 499. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 61BC) bit description Symbol Description Reset Access value ERCE Endpoint receive complete event for physical OUT endpoints 5 to 0.
Page 683 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 500. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description …continued Symbol Value Description Reset Access value Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host.
Page 684 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 501. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Symbol Value Description Reset Access value Reserved Endpoint type...
Page 685 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 501. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Symbol Value Description Reset Access value Tx data toggle inhibit This bit is only used for test and should always be written as zero.
Page 686 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.7.5 ATX transceiver The USB-OTG has a USB transceiver with UTMI+ interface. It contains the required transceiver OTG functionality; this includes: • VBUS sensing for producing the session-valid and VBUS-valid signals.
Page 687 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller consumption rate, then software can reduce the SOF length using the USB0FLADJ register. The USB bit clock is still running at the normal rate so no bus errors occur. The host only changes when it introduces the next SOF token - earlier or later on a bit-time resolution boundary.
Page 688 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller The hardware assist consists of the following steps: 1. Hardware resets the OTG controller (writes 1 to the RST bit in USBCMD). 2. Hardware selects the device mode (writes 10 to bits CM[1:0] in USBMODE).
Page 689 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller block in the system, the transaction translator function normally associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The embedded transaction translator function is an extension to EHCI interface but makes use of the standard data structures and operational models that exist in the EHCI specification to support full and low speed devices.
Page 690 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.8.1.4 Data structures The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root Hub with an embedded Transaction Translator. Here it is...
Page 691 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.8.1.6 Split state machines The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simply an internal operation to the embedded Transaction Translator.
Page 692 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller There is no data schedule mechanism for these transactions other than micro-frame pipeline. The embedded TT assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior may result.
Page 693 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller • Software writes a ‘1’ to the port reset bit in the PORTSC1 register to reset the device. • Software writes a ‘0’ to the port reset bit in the PORTSC1 register after 10 ms.
Page 694 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Endpoint Transfer Endpoint Queue Heads Descriptors dTD Endpoint dQH5 - IN Endpoint dQH5 - OUT TRANSFER transfer buffer BUFFER pointer TRANSFER BUFFER transfer buffer Endpoint dQH1 - OUT pointer TRANSFER Control Endpoint dQH0 - IN...
Page 695 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller device Queue Head (dQH) transfer overlay offset ENDPOINT CAPABILITIES/CHARACTERISTICS 0x00 0x04 CURRENT dTD POINTER endpoint transfer descriptor (dTD) 0x08 NEXT dTD POINTER NEXT dTD POINTER 0x0C Total_bytes MulO STATUS Total_bytes MulO...
Page 696 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 504. Endpoint capabilities and characteristics Access Bit Name Description 31:30 MULT Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD.
Page 697 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller After an endpoint is readied, the dTD will be copied into this queue head overlay area by the device controller. Until a transfer is expired, software must not write the queue head overlay area or the associated transfer descriptor.
Page 698 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 508. dTD token Access Name Description reserved 30:16 Total_bytes Total bytes This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the...
Page 699 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 508. dTD token …continued Access Name Description 11:10 MultO Multiplier Override (see Section 25.9.2.1 for an example) This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
Page 700 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller In this case three packets are sent: Data2 (8 bytes), Data1 (7 bytes), Data0 (0 bytes). Example 2 MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 2 In this case two packets are sent: Data1 (8 bytes), Data0 (7 bytes).
Page 701 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup packet. The contents of the first setup packet will require a response in accordance with USB device framework command set (see USB Specification Rev.
Page 702 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller The states powered, attach, default FS/HS, suspend FS/HS are implemented in the device controller and are communicated to the DCD using the following status bits: • DCSuspend - see Table 472.
Page 703 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller • After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSC1 to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and DCD can begin enumeration according to the USB2.0 specification Chapter 9 - Device...
Page 704 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Remark: Before resume signaling can be used, the host must enable it by using the Set Feature command defined in USB Device Framework (chapter 9) of the USB 2.0 Specification. 25.10.5 Managing endpoints The USB 2.0 specification defines an endpoint, also called a device endpoint or an...
Page 705 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 510. Device controller endpoint initialization Field Value 10 - bulk 11 - interrupt Endpoint Stall 25.10.5.2 Stalling There are two occasions where the device controller may need to return to the host a STALL: 1.
Page 706 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.10.5.3.1 Data toggle reset The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a ‘1’ to the data toggle reset bit in the ENDPTCTRLx register.
Page 707 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller fetch the operating context needed to handle a request from the host without the need to follow the linked list, starting at the dQH when the host request is received. After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller.
Page 708 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Table 513. Variable length transfer protocol example (ZLT = 1) Bytes (dTD) Max Packet Length (dQH) Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints.
Page 709 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller length protocol then ACK. SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 25.10.8 Control endpoint operational model 25.10.8.1 Setup phase All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase.
Page 710 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Remark: Leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware behavior. • After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet was received on a particular pipe: a.
Page 711 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.10.8.3 Status phase Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT as described above in the data phase.
Page 712 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for device mode does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints.
Page 713 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller # Packets Occurred > 0 AND # Packets Occurred < MULT. • CRC Error [Transaction Error bit is set] Remark: For ISO, when a dTD is retired, the next dTD is primed for the next frame. For continuous (micro) frame to (micro) frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro) frames.
Page 714 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.10.10 Managing queue heads Endpoint Transfer Endpoint Queue Heads Descriptors dTD transfer buffer TRANSFER pointer BUFFER Endpoint dQH0 - Out transfer buffer pointer TRANSFER Endpoint dQH0 - In BUFFER Endpoint dQH1 - Out...
Page 715 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller • Write the Active bit in the status field to “0”. • Write the Halt bit in the status field to “0”. Remark: The DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD’s.
Page 716 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Head Pointer Tail Pointer current Endpoint next completed dTDs queued dTDs Fig 72. Software link pointers 25.10.11.2 Building a transfer descriptor Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer.
Page 717 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME. Linked list is not empty 1. Add dTD to end of the linked list. 2. Read correct prime bit in ENDPTPRIME – if ‘1’ DONE.
Page 718 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.10.11.5 Flushing an endpoint It is necessary for the DCD to flush one or more endpoints on a USB device reset or during a broken control transfer. There may also be application specific requirements to stop transfers in progress.
Page 719 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.10.12 Servicing interrupts The interrupt service routine must consider different types of interrupts for high-frequency and low-frequency, and error operations and specify the priorities accordingly. 25.10.12.1 High-frequency interrupts High frequency interrupts in particular should be handled in the order below. The most important of these is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.
Page 720 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 25.11 System error The USB controller is an AHB bus master and any interaction between the USB controller and the system may experience errors. The type of error may be catastrophic to the USB controller (such as a Master Abort), making it impossible for the USB controller to continue in a coherent manner.
Page 721 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Enable bit in the USBINTR control register. Software then has 7 ms to transition a bus powered device into the Suspended state. In the Suspended state, a USB device has a maximum USB bus power budget of 2.5 mA.
Page 722 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller Host directed Autonomous operational 3 ms Low-power idle request resume interrupt received prepare disconnect Suspend SW sets SW sets user-defined Suspend bit Suspend bit wakeup disconnect Suspend Suspend Lock power states...
Page 723 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller 2. If the host puts resume signaling on the bus, it will clear the Suspend bit and generate a port change interrupt when the resume is finished. Remark: The Suspend interrupt is generated by the USB block whenever it detects that the bus is idle for more than 3 ms.
Page 724 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller external event could clear the suspend bit and start the transceiver clock running again. The software can then initiate a resume by setting the resume bit in the port controller, or force a reconnect by setting the reset bit in the port controller.
Page 725 UM10503 NXP Semiconductors Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller • a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed). • a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed). The vbusvalid and bvalid signals coming from the transceiver are not filtered in the SUSP_CTRL module.
Page 726 UM10503 Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Rev. 2.1 — 10 December 2015 User manual 26.1 How to read this chapter The USB1 Host/Device controller is available on parts LPC436x/LPC43S6x, LPC435x/LPC43S5x, and LPC433x/LPC43S3x. USB frame length adjustment is available for parts with on-chip flash only.
Page 727 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.3 Features • Supports all high-speed USB-compliant peripherals if connected to external ULPI PHY. • Supports all full-speed USB-compliant peripherals. • Complies with Universal Serial Bus specification 2.0. • Complies with Enhanced Host Controller Interface Specification.
Page 728 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller LPC43xx SYSTEM ARM Cortex-M4 MEMORY master slave USB1_VBUS TX-BUFFER INTERNAL (DUAL-PORT RAM) USB1_DP FULL-SPEED USB 2.0 USB1_DM Mobile/ RX-BUFFER GROUND (DUAL-PORT RAM) Fig 76. USB1 block diagram with internal full-speed PHY 26.5 Pin description...
Page 729 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 522. USB1 pin description Pin function Direction Description ULPI_STP ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. ULPI_NXT ULPI link NXT signal. Data flow control signal from the PHY.
Page 730 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 524. Register overview: USB1 host/device controller (register base address 0x4000 7000) …continued Name Access Address Description Reset value Reference offset USBINTR_H 0x148 USB interrupt enable (host mode) 0x0000 0000 Table 536...
Page 731 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.1 Device/host capability registers Table 525. CAPLENGTH register (CAPLENGTH - address 0x4000 7100) bit description Symbol Description Reset value Access CAPLENGTH Indicates offset to add to the register base 0x40 address at the beginning of the Operational...
Page 732 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 527. HCCPARAMS register (HCCPARAMS - address 0x4000 7108) bit description Symbol Description Reset value Access 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. Programmable Frame List Flag. If set to one, then...
Page 733 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.2.1 Device mode Table 530. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description Symbol Value Description Reset Access value Run/Stop Writing a 0 to this bit will cause a detach event.
Page 734 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 530. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value Not used in device mode. 23:16 Interrupt threshold control.
Page 735 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 531. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value This bit controls whether the host controller skips processing the periodic schedule.
Page 736 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 531. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value Bit 2 of the Frame List Size bits. See Table 532.
Page 737 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.3.1 Device mode Table 533. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB interrupt R/WC This bit is cleared by software writing a one to it.
Page 738 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 533. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB reset received R/WC This bit is cleared by software writing a one to it.
Page 739 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.3.2 Host mode Table 534. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB interrupt (USBINT) R/WC This bit is cleared by software writing a one to it.
Page 740 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 534. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued Symbol Value Description Reset Access value Not used by the Host controller. 11:9 Reserved.
Page 741 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 534. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued Symbol Value Description Reset Access value USB host periodic interrupt (USBHSTPERINT) R/WC This bit is cleared by software writing a one to it.
Page 742 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 535. USB Interrupt register in device mode (USBINTR_D - address 0x4000 7148) bit description …continued Symbol Description Reset Access value SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt.
Page 743 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 536. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description …continued Symbol Description Access Reset value Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold.
Page 744 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.5.2 Host mode This register is used by the host controller to index the periodic frame list. The register updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution.
Page 745 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 540. USB Device Address register in device mode (DEVICEADDR - address 0x4000 7154) bit description Symbol Value Description Reset Access value 23:0 reserved USBADRA Device address advance Any write to USBADR are instantaneous.
Page 746 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 542. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 7158) bit description Symbol Description Reset Access value 10:0 reserved 31:11 EPBASE31_11 Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 8 Queue Heads (QH).
Page 747 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 545. USB burst size register in device/host mode (BURSTSIZE - address 0x4000 7160) bit description Symbol Description Reset Access value RXPBURST Programmable RX burst length 0x10 This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
Page 748 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 546. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 7164) bit description Symbol Description Reset Access value TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.
Page 749 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller operations will not be able execute. Undefined behavior will result if ULPISS = 0 and a read or write operation is performed. To execute a wakeup operation, write all 32 bits of the ULPI Viewport where ULPIPORT is constructed appropriately and the ULPIWU bit is a 1 and ULPIRUN bit is a 0.
Page 750 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.12 BINTERVAL register This register defines the bInterval value which determines the length of the virtual frame (see Section 25.7.7). Remark: The BINTERVAL register is not related to the bInterval endpoint descriptor field in the USB specification.
Page 751 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller 26.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN) 26.6.14.1 Device mode Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx and Rx endpoint has a bit in the EPTNE and EPRNE field respectively.
Page 752 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 551. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value Current connect status Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register.
Page 753 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 551. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value 15:14 PIC1_0 Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.
Page 754 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 551. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value 27:26 PSPD Port speed This register field indicates the speed at which the port is operating.
Page 755 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 552. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value Port enable. Ports can only be enabled by the host controller as a part of the reset and enable.
Page 756 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 552. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, Table 553 “Port states as described by the PE and SUSP bits in the...
Page 757 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 552. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on).
Page 758 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 552. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value WKDC Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.
Page 759 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 553. Port states as described by the PE and SUSP bits in the PORTSC1 register PE bit SUSP bit Port state 0 or 1 disabled enabled suspend 26.6.16 USB Mode register (USBMODE) The USBMODE register sets the USB mode for the USB controller.
Page 760 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 554. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved.
Page 761 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 555. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved.
Page 762 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 557. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 71B0) bit description Symbol Description Reset Access value PERB Prime endpoint receive buffer for physical OUT endpoints. R/WS For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction.
Page 763 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 558. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description Symbol Description Reset Access value 15:4 Reserved 19:16 FETB Flush endpoint transmit buffer for physical IN endpoints. R/WC Writing a one to a bit(s) will clear any primed buffers.
Page 764 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Writing a one will clear the corresponding bit in this register. Table 560. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 71BC) bit description Symbol Description Reset Access value ERCE Endpoint receive complete event for physical OUT endpoints.
Page 765 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 561. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description …continued Symbol Value Description Reset Access value Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host.
Page 766 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 562. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Symbol Value Description Reset Access value Reserved Endpoint type...
Page 767 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller Table 562. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Symbol Value Description Reset Access value Tx data toggle inhibit This bit is only used for test and should always be written as zero.
Page 768 UM10503 NXP Semiconductors Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller raw pin status register hence LOW level detection should be configured for this pin to detect when to turn the PLL off. Similarly, to detect resume signaling to leave low power state, software should configure this pin to detect a HIGH level in the event router.
Page 769 UM10503 Chapter 27: LPC43xx/LPC43Sxx USB API Rev. 2.1 — 10 December 2015 User manual 27.1 How to read this chapter The USB ROM API is available on parts LPC4350/30/20 and LPC43S50/S30/S20. 27.2 Introduction The boot ROM contains a USB driver to simplify the USB application development. The USB driver implements the Communication Device Class (CDC), the Human Interface Device (HID), and the Mass Storage Device (MSC) device class.
Page 770 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API – USB descriptors data structure (Table 579 “_USB_CORE_DESCS_T class structure”) – USB device stack initialization parameter data structure (Table 588 “USBD_API_INIT_PARAM class structure”). – USB device stack core API functions structure (Table 591 “USBD_CORE_API class structure”).
Page 771 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API const USBD_DFU_API_T* dfu; const USBD_HID_API_T* hid; const USBD_CDC_API_T* cdc; const uint32_t* reserved6; const uint32_t version; } USBD_API_T; Ptr to USB ROM Driver table Device 1 0x1040 011C Ptr to Function 0 Ptr to Function 1 Ptr to Function 2 …...
Page 772 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 564. _BM_T class structure Member Description Recipient uint8_t _BM_T::Recipient Recipient type. Type uint8_t _BM_T::Type Request type. uint8_t _BM_T::Dir Direction type. 27.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR Table 565. _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR class structure Member Description bFunctionLength uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bFunctionLength...
Page 773 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 568. _CDC_LINE_CODING class structure Member Description dwDTERate uint32_t _CDC_LINE_CODING::dwDTERate bCharFormat uint8_t _CDC_LINE_CODING::bCharFormat bParityType uint8_t _CDC_LINE_CODING::bParityType bDataBits uint8_t _CDC_LINE_CODING::bDataBits 27.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR Table 569. _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR::sUnion bSlaveInterfaces uint8_t _CDC_UNION_1SLAVE_DESCRIPTOR::bSlaveInterfaces[1][1] 27.5.8 _CDC_UNION_DESCRIPTOR...
Page 774 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 572. _HID_DESCRIPTOR class structure Member Description bLength uint8_t _HID_DESCRIPTOR::bLength Size of the descriptor, in bytes. bDescriptorType uint8_t _HID_DESCRIPTOR::bDescriptorType Type of HID descriptor. bcdHID uint16_t _HID_DESCRIPTOR::bcdHID BCD encoded version that the HID descriptor and device complies to.
Page 775 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 575. _MSC_CBW class structure Member Description dSignature uint32_t _MSC_CBW::dSignature dTag uint32_t _MSC_CBW::dTag dDataLength uint32_t _MSC_CBW::dDataLength bmFlags uint8_t _MSC_CBW::bmFlags bLUN uint8_t _MSC_CBW::bLUN bCBLength uint8_t _MSC_CBW::bCBLength uint8_t _MSC_CBW::CB[16][16] 27.5.14 _MSC_CSW Table 576. _MSC_CSW class structure...
Page 776 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 579. _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t * _USB_CORE_DESCS_T::device_desc Pointer to USB device descriptor string_desc uint8_t * _USB_CORE_DESCS_T::string_desc Pointer to array of USB string descriptors full_speed_desc uint8_t * _USB_CORE_DESCS_T::full_speed_desc Pointer to USB device configuration descriptor when device is operating in full speed mode.
Page 777 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 581. _USB_DFU_FUNC_DESCRIPTOR class structure Member Description bLength uint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength bDescriptorType uint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType bmAttributes uint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes wDetachTimeOut uint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut wTransferSize uint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize bcdDFUVersion uint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion 27.5.20 _USB_INTERFACE_DESCRIPTOR Table 582. _USB_INTERFACE_DESCRIPTOR class structure...
Page 778 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 583. _USB_OTHER_SPEED_CONFIGURATION class structure Member Description bLength uint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength Size of descriptor bDescriptorType uint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType Other_speed_Configuration Type wTotalLength uint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength Total length of data returned bNumInterfaces uint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces Number of interfaces supported by this speed configuration...
Page 779 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 585. _USB_STRING_DESCRIPTOR class structure Member Description bLength uint8_t _USB_STRING_DESCRIPTOR::bLength Size of this descriptor in bytes bDescriptorType uint8_t _USB_STRING_DESCRIPTOR::bDescriptorType STRING Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR::bString UNICODE encoded string 27.5.24 _WB_T Table 586. _WB_T class structure...
Page 780 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 587. USBD_API class structure Member Description const USBD_CDC_API_T* USBD_API::cdc Pointer to function table which exposes functions provided by CDC-ACM function driver module. reserved6 const uint32_t* USBD_API::reserved6 Reserved for future function driver module.
Page 781 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 588. USBD_API_INIT_PARAM class structure Member Description USB_Resume_Event USB_CB_T USBD_API_INIT_PARAM::USB_Resume_Event Event for USB wake up or resume. This event fires when a the USB device interface is suspended and the host wakes up the device by supplying Start Of Frame pulses. This is generally hooked to pull the user application out of a low power state and back into normal operating mode.
Page 782 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 588. USBD_API_INIT_PARAM class structure Member Description USB_Configure_Event USB_CB_T USBD_API_INIT_PARAM::USB_Configure_Event Event for USB configuration number changed. This event fires when a the USB host changes the selected configuration number. On receiving configuration change request from host, the stack enables/configures the endpoints needed by the new configuration before calling this callback function.
Page 783 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 589. USBD_CDC_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param, USBD_HANDLE_T *phCDC) Function to initialize CDC function driver module. This function is called by application layer to initialize CDC function driver module.
Page 784 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_CDC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller.
Page 785 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) Communication Interface Class specific set request call-back function. This function is provided by the application software. This function gets called when host sends a CIC management element requests.
Page 786 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description CDC_BulkOUT_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkOUT_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Communication Device Class specific BULK OUT endpoint handler. The application software should provide the BULK OUT endpoint handler. Applications should transfer data depending on the communication protocol type set in descriptors.
Page 787 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description GetEncpsResp ErrorCode_t(* USBD_CDC_INIT_PARAM::GetEncpsResp)(USBD_HANDLE_T hCDC, uint8_t **buffer, uint16_t *len) Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request call-back function. This function is provided by the application software. This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request.
Page 788 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description GetCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::GetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t **pBuffer, uint16_t *len) Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request.
Page 789 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description ClrCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature) Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a CLEAR_COMM_FEATURE request.
Page 790 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description SetCtrlLineState ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state) Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function. This function is provided by the application software. This function gets called when host sends a SET_CONTROL_LINE_STATE request.
Page 791 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding) Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. This function is provided by the application software. This function gets called when host sends a SET_LINE_CODING request.
Page 792 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 590. USBD_CDC_INIT_PARAM class structure Member Description CDC_Ep0_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user override-able function to replace the default CDC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 793 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 591. USBD_CORE_API class structure Member Description RegisterEpHandler ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void *data) Function to register interrupt/event handler for the requested endpoint with USB device stack. The application layer uses this function to register the custom class's EP0 handler. The stack calls all the registered class handlers on any EP0 event before going through default handling of the event.
Page 794 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 591. USBD_CORE_API class structure Member Description DataOutStage void(*void USBD_CORE_API::DataOutStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in data_out state. This function is called by USB stack and the application layer to set the EP0 state machine in data_out state.
Page 795 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 591. USBD_CORE_API class structure Member Description StallEp0 void(*void USBD_CORE_API::StallEp0)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in stall state. This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint.
Page 796 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 592. USBD_DFU_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_DFU_API::GetMemSize)(USBD_DFU_INIT_PARAM_T *param) Function to determine the memory required by the DFU function driver module. This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used by DFU function driver module.
Page 797 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 593. USBD_DFU_INIT_PARAM class structure Member Description wTransferSize uint16_t USBD_DFU_INIT_PARAM::wTransferSize DFU transfer block size in number of bytes. This value should match the value set in DFU descriptor provided as part of the descriptor array (...
Page 798 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 593. USBD_DFU_INIT_PARAM class structure Member Description DFU_Detach void(* USBD_DFU_INIT_PARAM::DFU_Detach)(USBD_HANDLE_T hUsb) DFU detach callback function. This function is provided by the application software. This function gets called after USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH bit in DFU descriptor should define this function.
Page 799 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 594. USBD_HID_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HID_API::GetMemSize)(USBD_HID_INIT_PARAM_T *param) Function to determine the memory required by the HID function driver module. This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used by HID function driver module.
Page 800 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 595. USBD_HID_INIT_PARAM class structure Member Description mem_base uint32_t USBD_HID_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. Also this value should be aligned on 4 byte boundary.
Page 801 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 595. USBD_HID_INIT_PARAM class structure Member Description HID_SetReport ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) HID set report callback function. This function is provided by the application software. This function gets called when host sends a HID_REQUEST_SET_REPORT request.
Page 802 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 595. USBD_HID_INIT_PARAM class structure Member Description HID_SetIdle ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetIdle)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t idleTime) Optional callback function to handle HID_REQUEST_SET_IDLE request. The application software could provide this callback to handle HID_REQUEST_SET_IDLE requests sent by the host.
Page 803 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 595. USBD_HID_INIT_PARAM class structure Member Description HID_EpIn_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpIn_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt IN endpoint event handler. The application software could provide Interrupt IN endpoint event handler. Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member.
Page 804 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 595. USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt OUT endpoint event handler. The application software could provide Interrupt OUT endpoint event handler. Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member.
Page 805 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 595. USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default HID class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 806 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HW_API::GetMemSize)(USBD_API_INIT_PARAM_T *param) Function to determine the memory required by the USB device stack's DCD and core layers. This function is called by application layer before calling pUsbApi->hw->...
Page 807 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description void(*void USBD_HW_API::ISR)(USBD_HANDLE_T hUsb) Function to USB device controller interrupt events. When the user application is active the interrupt handlers are mapped in the user flash space. The user application must provide an interrupt handler for the USB interrupt and call this function in the interrupt handler routine.
Page 808 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description WakeUpCfg void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg) Function to configure USB device controller to walk-up host on remote events. This function is called by application layer to configure the USB device controller to wake up on remote events.
Page 809 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description ConfigEP void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) Function to configure USB Endpoint according to descriptor. This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received by the stack from USB host. All the endpoints associated with the selected configuration are configured.
Page 810 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description EnableEP void(*void USBD_HW_API::EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to enable selected USB endpoint. This function enables interrupts on selected endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
Page 811 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description SetStallEP void(*void USBD_HW_API::SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to STALL selected USB endpoint. Generates STALL signalling for requested endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
Page 812 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description ReadEP uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) Function to read data received on the requested endpoint. This function is called by USB stack and the application layer to read the data received on the requested endpoint.
Page 813 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 596. USBD_HW_API class structure Member Description WriteEP uint32_t(*uint32_t USBD_HW_API::WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt) Function to write data to be sent on the requested endpoint. This function is called by USB stack and the application layer to send data on the requested endpoint.
Page 814 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 597. USBD_MSC_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_MSC_API::GetMemSize)(USBD_MSC_INIT_PARAM_T *param) Function to determine the memory required by the MSC function driver module. This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used by MSC function driver module.
Page 815 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 598. USBD_MSC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_MSC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller.
Page 816 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 598. USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t offset, uint8_t **dst, uint32_t length) MSC Read callback function. This function is provided by the application software. This function gets called when host sends a read command.
Page 817 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 598. USBD_MSC_INIT_PARAM class structure Member Description MSC_Verify ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Verify)(uint32_t offset, uint8_t buf[], uint32_t length) MSC Verify callback function. This function is provided by the application software. This function gets called when host sends a verify command.
Page 818 UM10503 NXP Semiconductors Chapter 27: LPC43xx/LPC43Sxx USB API Table 598. USBD_MSC_INIT_PARAM class structure Member Description MSC_Ep0_Hdlr ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default MSC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 819 UM10503 Chapter 28: LPC43xx/LPC43Sxx Ethernet Rev. 2.1 — 10 December 2015 User manual 28.1 How to read this chapter The Ethernet controller is available on parts LPC437x/LPC43S7x, LPC436x/LPC43S6x, LPC435x/LPC43S5x, and LPC433x/LPC43S3x. The MII is not available on the LQFP144 and TFBGA100 packages.
Page 820 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.4 General description The Ethernet block enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2005 standard. The Ethernet interface contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration.
Page 821 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.5 Pin description Table 600. Ethernet pin description Pin function Direction Description MIIM interface ENET_MDIO Ethernet MIIM Data Input and Output. ENET_MDC Ethernet MIIM Clock. RMII interface ENET_RXD[1:0] Ethernet Receive Data. ENET_TXD[1:0] Ethernet Transmit Data.
Page 822 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.6 Register description Table 601. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address Description Reset value Reference offset MAC_CONFIG 0x0000 MAC configuration register 0x0000 8000 Table 602 MAC_FRAME_FILTER...
Page 823 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 601. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address Description Reset value Reference offset DMA_TRANS_POLL_DEMAND 0x1004 Transmit poll demand 0x0000 0000 Table 632 register DMA_REC_POLL_DEMAND 0x1008 Receive poll demand...
Page 824 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 602. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will...
Page 825 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 602. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously.
Page 826 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 602. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.
Page 827 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 603. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description …continued Symbol Description Reset Access value Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.
Page 828 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet If the corresponding bit value of the register is 1, the frame is accepted. Otherwise, it is rejected. If the PM (Pass All Multicast) bit is set in the MAC_CONFIG register, then all multicast frames are accepted regardless of the multicast hash values.
Page 829 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 606. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description Symbol Description Reset Access value MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear).
Page 830 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 607. CSR clock range values Bits 5:2 CLK_M4_ETHERNET MDC clock 1010 CLK_M4_ETHERNET/16 1011 CLK_M4_ETHERNET/26 1100 CLK_M4_ETHERNET/102 1101 CLK_M4_ETHERNET/124 1110 CLK_M4_ETHERNET/42 1111 CLK_M4_ETHERNET/62 28.6.6 MAC MII Data register The MII Data register stores Write data to be written to the PHY register located at the address specified in the MAC_MII_ADDR register.
Page 831 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 609. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description Symbol Description Reset Access value Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear).
Page 832 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 609. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description …continued Symbol Description Reset Access value DZPQ Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
Page 833 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Remark: Reset values in this register are valid only if the clocks to the Ethernet block are present during the reset operation. Table 611. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description...
Page 834 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.6.10 MAC Remote wake-up frame filter register This is the address through which the remote Wake-up Frame Filter registers (WKUPFMFILTER) are written/read by the Application. WKUPFMFILTER is actually a pointer to eight (not transparent) such WKUPFMFILTER registers. Eight sequential Writes to this address (0x028) will write all WKUPFMFILTER registers.
Page 835 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 613. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description Symbol Description Reset Access value Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read.
Page 836 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 614. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description Symbol Description Reset Access value Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: •...
Page 837 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet If the MAC address registers are configured to be double-synchronized to the MII clock domains, then the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0] (in Big-Endian mode) of the MAC Address Low Register are written to.
Page 838 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 618. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Symbol Description Reset Access value TSENA Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames.
Page 839 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 618. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Symbol Description Reset Access value TSIPENA Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also.
Page 840 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet In Coarse Update mode (TSCFUPDT bit in Table 618), the value in this register is added to the system time every clock cycle. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.
Page 841 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 622. System time nanoseconds register (NANOSECONDS, address 0x4001 070C) bit description Symbol Description Reset Access value 30:0 TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second.
Page 842 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 624. System time nanoseconds update register (NANOSECONDSUPDATE, address 0x4001 0714) bit description Symbol Description Reset Access value 30:0 TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second.
Page 843 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.6.24 Target time nanoseconds register This register contains the higher 32 bits of time to be compared with the system time for interrupt event generation. Table 627. Target time nanoseconds register (TARGETNANOSECONDS, address 0x4001...
Page 844 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 629. Time stamp status register (TIMESTAMPSTAT, address 0x4001 0728) bit description Symbol Description Reset Access value TSSOVF Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF.
Page 845 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 630. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Symbol Description Reset Access value 13:8 Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction.
Page 846 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 630. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Symbol Description Reset Access value Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits.
Page 847 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.6.29 DMA Receive poll demand register The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is given to wake up the RxDMA from SUSPEND state. The RxDMA can go into SUSPEND state only due to the unavailability of descriptors owned by it.
Page 848 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 635. DMA Transmit descriptor list address register (DMA_TRANS_DES_ADDR, address 0x4001 1010) bit description Symbol Description Reset Access value 31:0 Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list.
Page 849 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 636. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA.
Page 850 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 636. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the...
Page 851 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 636. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface).
Page 852 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 637. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued Symbol Description Reset Access value Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).
Page 853 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 637. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued Symbol Description Reset Access value Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear).
Page 854 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 638. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued Symbol Description Reset Access value Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled.
Page 855 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 638. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued Symbol Description Reset Access value Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled.
Page 856 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.6.35 DMA Missed frame and buffer overflow counter register The DMA maintains two counters to track the number of missed frames during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes.
Page 857 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 640. DMA Receive interrupt watchdog timer register (DMA_REC_INT_WDT, address 0x4001 1024) bit description Symbol Description Reset Access value RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer...
Page 858 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 643. DMA Current host transmit buffer address register (DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit description Symbol Description Reset Access value 31:0 Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation.
Page 859 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.1.2 Example for a multicast MAC address MAC: 01-45-a2-6c-30-33 CRC32: 0x2CB41110 Last 2 bytes in binary: 0001 0000 Bit-wise reversal: 0000 1000 First 6 bits: 000010 ( 0=Hash Table Low / 00010 => 0x2 => bit 2 ) In the MAC_HASH_TABLE_LOW register, write a 1 to bit 2.
Page 860 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Filter 0 Byte Mask WKUPFMFILTER0 Filter 1 Byte Mask WKUPFMFILTER1 Filter 2 Byte Mask WKUPFMFILTER2 Filter 3 Byte Mask WKUPFMFILTER3 Filter 3 Filter 2 Filter 1 Filter 0 WKUPFMFILTER4 RSVD RSVD RSVD RSVD...
Page 861 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet PMT supports four programmable filters that allow support of different receive frame patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter CRC-16 matches the incoming examined pattern, then the wake-up frame is received.
Page 862 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.2.4 System considerations during power-down MAC neither gates nor stops clocks when Power-down mode is enabled. Power saving by clock gating must be done outside the core by the application. The receive data path must be clocked with ENET_RX_CLK during Power-down mode because it is involved in magic packet/wake-on-LAN frame detection.
Page 863 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 645. Priority scheme for transmit and receive DMA Bit 27 Bit 15 Bit 14 Bit 1 Priority scheme Rx has priority over Tx in the ratio 4:1. Tx always has priority over Rx.
Page 864 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Fig 81. Networked time synchronization As shown in Figure 81, the PTP uses the following process: 1. The master broadcasts the PTP Sync messages to all its nodes. The Sync message contains the master.s reference time information. The time at which this message leaves the master.s system is t1.
Page 865 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Most of the PTP implementation is done in the software above the UDP layer. However, the hardware support is required to capture the exact time when specific PTP packets enter or leave the Ethernet port at the MII. This timing information must be captured and returned to the software for the proper implementation of PTP with high accuracy.
Page 866 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet addend_val[31:0] addend_updt Addend register Accumulator register Constant value incr_sub_sec_reg Sub-second register incr_sec_reg Second register Fig 82. System update using fine method The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns accuracy.
Page 867 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This value is as follows: FreqCompensationValue0 = 232 / FreqDivisionRatio If MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages, the algorithm described below must be applied.
Page 868 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.4.4 Receive path functions The MAC captures the timestamp of all frames received on the MII. The MAC does not process the received frames to identify the PTP frames in the default mode, that is, when the Advanced Timestamp feature is not selected.
Page 869 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet The minimum PTP clock frequency depends on the time required between two consecutive SFD bytes. Because the MII clock frequency is fixed by IEEE specification, the minimum PTP clock frequency required for proper operation depends upon the operating mode and operating speed of the MAC as shown in Table 4-1.
Page 870 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet P2P TC A P2P TC B Delay Delay Requester Responder Time Time Timestamps known by Delay Requester Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up: Fig 83. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction As shown in...
Page 871 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.5.2 Clock types The Ethernet controller supports the following clock types defined in the IEEE 1588-2008 standard: • Ordinary clock • Boundary clock • End-to-end transparent clock • Peer-to-peer transparent clock 28.7.5.2.1 Ordinary clock The ordinary clock in a domain supports a single copy of the protocol.
Page 872 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet The residence time of a SYNC packet inside the end-to-end transparent clock is updated in the correction field of the associated Follow_Up PTP packet before it is transmitted. Similarly, the residence time of a Delay_Req packet inside the end-to-end transparent clock is updated in the correction field of the associated Delay_Resp PTP packet before it is transmitted.
Page 873 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 650. Message format defined in IEEE 1588-2008 Bits OCTETS OFFSET sequenceId controlField ( logMessageInterva Field is used in version 1. In version 2, messageType field is used for detecting different message types.
Page 874 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 651. IPv4-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Position Matched Value Description PTP Control Field 0x00/0x01/0x02/ 0x00 – SYNC, (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 – Follow_Up 0x03 –...
Page 875 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 652. IPv6-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Position Matched Value Description PTP Control Field 93 ( 0x00/0x01/0x02/ 0x00 – SYNC (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 –...
Page 876 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet The address match of destination addresses (DA) programmed in MAC address 1 to 31 is used if the control bit 18 (TSENMACADDR: Enable MAC address for PTP frame filtering) of the Timestamp Control register is set.
Page 877 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.5.6 Receive path functions When you select the advanced timestamp feature, the MAC processes the received frames to identify valid PTP frames. You can control the snapshot of the time, to be sent to...
Page 878 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet in Ethernet. The controller can be programmed to interrupt the Host CPU for situations such as Frame Transmit and Receive transfer completion, and other normal/error conditions. The DMA and the Host driver communicate through two data structures: •...
Page 879 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Ring Structure Chain Structure Buffer 1 Buffer 1 Descriptor 0 Descriptor 0 Buffer 2 Buffer 1 Descriptor 1 Buffer 2 Buffer 1 Descriptor 1 Buffer 1 Descriptor 2 Buffer 2 Buffer 1 Descriptor 2...
Page 880 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet The Transmit and Receive engines enter the Running state and attempt to acquire descriptors from the respective descriptor lists. The Receive and Transmit engines then begin processing Receive and Transmit operations. The Transmit and Receive processes are independent of each other and can be started or stopped separately.
Page 881 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Example: Buffer write If the Receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of a received frame need to be transferred, then the DMA writes 3 full words from address 0x00000FF0.
Page 882 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.6.2 Transmission 28.7.6.2.1 TxDMA operation: Default (non-OSF) mode The transmit DMA engine in default mode proceeds as follows: 1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit (TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame data.
Page 883 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll demand error? TxDMA suspended bit set? Transfer data from buffer(s) (AHB) error? Frame xfer complete? Close intermediate Wait for Tx status descriptor Write time stamp to...
Page 884 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet immediately polls the Transmit Descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. In OSF mode, the Run state Transmit DMA operates in the following sequence: 1.
Page 885 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll error? demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) (AHB) Time stamp error? present? Frame xfer Second Write time stamp to...
Page 886 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.6.2.3 Transmit frame processing The Transmit DMA expects that the data buffers contain complete Ethernet frames, excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or PAD insertion, the buffer must have complete Ethernet frames (excluding preamble), including the CRC bytes.
Page 887 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet The driver must explicitly issue a Transmit Poll Demand command after rectifying the suspension cause. 28.7.6.2.5 Reception The Receive DMA engine’s reception sequence is shown in Figure 87 and proceeds as follows: 1. The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit (RDES0[31]).
Page 888 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Start RxDMA Start Stop RxDMA (Re-)Fetch next Poll demand / descriptor new frame available (AHB) RxDMA suspended error? Frame transfer Own bit set? complete? Frame data Flush disabled ? available ? Flush the...
Page 889 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet If software has enabled ing through CSR, when a valid value is not Time stamp Time stamp available for the frame (for example, because the receive FIFO was full before the Time could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise...
Page 890 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet descriptor is still owned by the host, by default, the DMA discards the current frame at the top of the MTL Rx FIFO and increments the missed frame counter. If more than one frame is stored in the MTL Rx FIFO, the process repeats.
Page 891 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet 28.7.6.2.10 Error response to DMA For any data transfer initiated by a DMA channel, if the slave replies with an error response, that DMA stops all operations and updates the error bits and the Fatal Bus...
Page 892 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Ctrl Ctrl Status [16:0] TDES0 [30:26] [23:20] Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES1 Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES3...
Page 893 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet SLOT Ctrl Ctrl Reserved for Reserved for Number TDES0 [30:26] [23:20] Status [17:7] Status [3:0] [6:3] Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES1 Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES3 Fig 89.
Page 894 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 654. Transmit descriptor word 0 (TDES0) Symbol Description Excessive Collision When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the DR (Disable Retry) bit in the MAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted.
Page 895 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 654. Transmit descriptor word 0 (TDES0) Symbol Description Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care”...
Page 896 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 656. Transmit descriptor word 2 (TDES2) Symbol Description 31:0 B1ADD Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment. See Section 28.7.6.1.2...
Page 897 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Status [30:0] RDES0 Buffer 2 Byte Count CTRL Buffer 1 Byte Count CTRL RDES1 [30:29] [28:16] [15:14] [12:0] Buffer 1 Address [31:0] RDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] RDES3...
Page 898 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 660. Receive descriptor fields 0 (RDES0) Symbol Description Extended Status Available/Rx MAC Address When Advanced Timestamp is present, this bit, when set, indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when the Last Descriptor bit (RDES0[8]) is set.
Page 899 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 660. Receive descriptor fields 0 (RDES0) Symbol Description Length Error When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset.
Page 900 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 661. Receive descriptor fields 1 (RDES1) Symbol Description 12:0 RBS1 Receive Buffer 1 Size Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16, depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address pointer) is not aligned.
Page 901 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet The extended status written is as shown in Table 664. The extended status is written only when there is status related to IPC or timestamp available. The availability of extended status is indicated by bit-0 of RDES0. This status is available only when Advance Timestamp or IPC Full Offload feature is selected.
Page 902 UM10503 NXP Semiconductors Chapter 28: LPC43xx/LPC43Sxx Ethernet Table 666. Receive descriptor fields 7 (RDES7) Symbol Description 31:0 RTSH Receive Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]).
Page 903 UM10503 Chapter 29: LPC43xx/LPC43Sxx LCD Rev. 2.1 — 10 December 2015 User manual 29.1 How to read this chapter The LCD controller is available on parts LPC4370/LPC43S70, LPC4350/LPC43S50, and LPC436x/LPC43S6x. 29.2 Basic configuration The LCD controller is configured as follows: •...
Page 904 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD • LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 29.4 General description The LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single or dual panel monochrome and color LCDs.
Page 905 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD LCD control signals Timing slave controller interface LCD panel clock Panel clock Upper generator panel LCDCLKIN FIFO Upper Upper Input Upper Pixel panel master FIFO palette panel serializer output interface control (128x32) formatter...
Page 906 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD • Display type: STN monochrome, STN color, or TFT • STN 4 or 8-bit interface mode • STN dual or single panel mode • Little-endian, big-endian, or Windows CE mode • Interrupt generation event 29.4.2 Hardware cursor support...
Page 907 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD • 16 bpp, direct 5:5:5 RGB, with 1 bpp not normally used. This pixel is still output, and can be used as a brightness bit to connect to the Least Significant Bit (LSB) of RGB components of a 6:6:6 TFT panel.
Page 908 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 668. LCD controller pins Pin function Type Function LCDLP Output Line synchronization pulse (STN). Horizontal synchronization pulse (TFT) LCDVD[23:0] Output LCD panel data. Bits used depend on the panel configuration. GP_CLKIN Input General purpose CGU input clock.
Page 909 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 670. Pins used for dual panel STN displays Pin name 4-bit Monochrome 8-bit Monochrome Color (14 pins) (22 pins) (22 pins) LCDVD[11:8] LD[3:0] LD[3:0] LD[3:0] LCDVD[15:12] LD[7:4] LD[7:4] LCDVD[23:16] 29.5.1.3 Signals used for TFT displays...
Page 910 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 672. Register overview: LCD controller (base address: 0x4000 8000) …continued Name Access Address offset Description Reset Reference value 0x00C Line End Control register Table 676 UPBASE 0x010 Upper Panel Frame Base Address register...
Page 911 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 673. Horizontal Timing register (TIMH, address 0x4000 8000) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 912 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD • PCD = 5 (LCDCLK / 7) If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10, data does not corrupt for PCD = 4, the minimum value.
Page 913 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 675. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description Symbol Description Reset value PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this...
Page 914 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 675. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description Symbol Description Reset value Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines.
Page 915 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 676. Line End Control register (LE, address 0x4000 800C) bit description Symbol Description Reset value Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1.
Page 916 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 678. Lower Panel Frame Base register (LPBASE, address 0x4000 8014) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 917 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 679. LCD Control register (CTRL, address 0x4000 8018) bit description …continued Symbol Description Reset value LCDDUAL Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel.
Page 918 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD 29.6.8 Interrupt Mask register The INTMSK register controls whether various LCD interrupts occur.Setting bits in this register enables the corresponding raw interrupt INTRAW status bit values to be passed to the INTSTAT register for processing as interrupts.
Page 919 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 681. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description Symbol Description Reset value VCOMPRIS Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register.
Page 920 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 683. Interrupt Clear register (INTCLR, address 0x4000 8028) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 921 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Each word location contains two palette entries. This means that 128 word locations are used for the palette. When configured for little-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. When configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry.
Page 922 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 687. Cursor Image registers (CRSR_IMG, address 0x4000 8800 (CRSR_IMG0) to 0x4000 8BFC (CRSR_IMG1)) bit description Symbol Description Reset value 31:0 CRSR_IMG Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors.
Page 923 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 689. Cursor Configuration register (CRSR_CFG, address 0x4000 8C04) bit description Symbol Description Reset value CrsrSize Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor.
Page 924 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 691. Cursor Palette register 1 (CRSR_PAL1, address 0x4000 8C0C) bit description Symbol Description Reset value Red color component 15:8 GREEN Green color component 23:16 BLUE Blue color component. 31:24 Reserved, user software should not write ones to reserved bits.
Page 925 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 693. Cursor Clip Position register (CRSR_CLIP, address 0x4000 8C14) bit description Symbol Description Reset value CRSRCLIPX Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor.
Page 926 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD 29.6.24 Cursor Raw Interrupt Status register The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt controller.
Page 927 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD 29.7.1.2 AMBA AHB master interface The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configured to obtain data from any on-chip SRAM on AHB, various types of off-chip static memory, or off-chip SDRAM.
Page 928 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 698 through Table 700 show the structure of the data in each DMA FIFO word corresponding to the endianness and bpp combinations. For each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word.
Page 929 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 699. FIFO bits for Big-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp UM10503 All information provided in this document is subject to legal disclaimers.
Page 930 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 700. FIFO bits for Little-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp Table 701 shows the structure of the data in each DMA FIFO word in RGB mode.
Page 931 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 701. RGB mode data formats FIFO data 24-bit RGB 16-bit (1:5:5:5 RGB) 16-bit (5:6:5 RGB) 16-bit (4:4:4 RGB) p1 intensity bit p1, Blue 4 p1, Blue 4 p1, Blue 3 p1, Blue 3...
Page 932 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Pixel data values can be written and verified through the AHB slave interface. For information on the supported colors, refer to the section on the related panel type earlier in this chapter. The palette RAM is a dual port RAM with independent controls and addresses for each port.
Page 933 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 703. Palette data storage for STN color modes. Bit(s) Name Description Name Description (RGB format) (RGB format) (BGR format) (BGR format) G[0] Unused G[0] Unused R[4:1] Red palette data B[4:1] Blue palette data...
Page 934 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD When the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. When the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image.
Page 935 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD With FrameSync inactive, the cursor responds immediately to any change in the programmed CRSR_XY value. Some transient smearing effects may be visible if the cursor is moved across the LCD scan line. With FrameSync active, the cursor only updates its position after a vertical synchronization has occurred.
Page 936 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD 29.7.5.6 Cursor image format The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode.
Page 937 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 707 shows the buffer to pixel mapping for Cursor 0. Table 707. Buffer to pixel mapping for 32 x 32 pixel cursor format Offset into cursor memory Data bits (8 * y)
Page 938 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 708. Buffer to pixel mapping for 64 x 64 pixel cursor format Offset into cursor memory Data bits (16 * y) (16 * y) +4 (16 * y) + 8 (16 * y) + 12...
Page 939 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 710. Color display driven with 2 2/3 pixel data Byte CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] CLD[0] P2[Green] P2[Red] P1[Blue] P1[Green] P1[Red] P0[Blue] P0[Green] P0[Red] P5[Red] P4q[Blue] P4[Green] P4[Red] P3[Blue] P3[Green]...
Page 940 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD • Next base address update interrupt. • FIFO underflow interrupt. Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the INT_MSK register. These interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked.
Page 941 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD 1. When power is applied, the following signals are held LOW: • LCDLP • LCDDCLK • LCDFP • LCDENAB/ LCDM • LCDVD[23:0] • LCDLE 2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This enables the following signals into their active states: •...
Page 942 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD LCD on sequence LCD off sequence Minimum 0 ms Minimum 0 ms LCD Power Minimum 0 ms Minimum 0 ms LCDLP, LCDCP, LCDFP, LCDAC, LCDLE Contrast Voltage LCDPWR, LCD[23:0] Display specific delay Display specific delay Fig 95.
Page 943 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD 29.8 LCD timing diagrams one horizontal line pixel clock (internal) LCD_TIMH (HSW) LCDLP (line synch pulse) suppressed during LCDLP LCDDCLK (panel clock) 16  LCD_TIMH(PPL)  1 LCD_TIMH (HFP) LCD_TIMH (HBP) horizontal back porch...
Page 944 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD one frame LCDDCLK panel data clock active (panel clock) LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch all horizontal lines for one frame front porch (defined in line clocks)
Page 945 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD one frame LCDDCLK panel data clock active (panel clock) LCDENA data enable (data enable) LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch all horizontal lines for one frame...
Page 946 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 711. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC43xx pin LCD function LPC43xx pin LCD function...
Page 947 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 712. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC43xx pin LCD function LPC43xx pin LCD function...
Page 948 UM10503 NXP Semiconductors Chapter 29: LPC43xx/LPC43Sxx LCD Table 713. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC43xx LPC43xx LPC43xx pin LPC43xx pin used...
Page 949 Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Rev. 2.1 — 10 December 2015 User manual 30.1 How to read this chapter The SCT without the dither engine is available on all flashless LPC43xx/LPC43Sxx parts (LPC4370/50/30/20/10). 30.2 Basic configuration The SCT is configured as follows: •...
Page 950 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) – 16 match/capture registers – 16 events – 32 states 30.4 General description The State Configurable Timer (SCT) allows a wide variety of timing, counting, output modulation, and input capture operations.
Page 951 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) CLK_M4_SCT SCT clock prescaler(s) Fig 100. SCT block diagram SCT clock CLK_M4_SCT prescaler H counter Unified counter prescaler L counter Fig 101. SCT counter and select logic 30.5 Pin description The SCT inputs can originate from the external pins or from several internal sources.
Page 952 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 715. SCT inputs and outputs Description Pin function Internal signal Default (see CTOUTCTRL GIMA, bit (see Table 208) Table 105) SCT inputs SCT input 0 CTIN_0 SGPIO3 SGPIO3_DIV SCT input 1...
Page 953 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 715. SCT inputs and outputs …continued Description Pin function Internal signal Default (see CTOUTCTRL GIMA, bit (see Table 208) Table 105) SCT output 4 ORed with Timer3 match output 3...
Page 954 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.6 Register description The register addresses of the State Configurable Timer are shown in Table 716. For most of the SCT registers, the register function depends on the setting of certain other register bits: 1.
Page 955 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 716. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset STATE_L 0x044 SCT state register low counter 16-bit 0x0000 0000...
Page 956 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 716. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset CAP0_L to CAP15_L 0x180 to CAP alias register (see Section 30.7.9).
Page 957 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 716. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset EVSTATEMSK5 0x328 SCT event state register 5 0x0000 0000 Table 740...
Page 958 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 716. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset OUTPUTSET9 0x548 SCT output 9 set register 0x0000 0000 Table 742...
Page 959 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 717. SCT configuration register (CONFIG - address 0x4000 0000) bit description …continued Symbol Value Description Reset value CLSEL SCT clock select 0000 Rising edges on input 0. Falling edges on input 0.
Page 960 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 718. SCT control register (CTRL - address 0x4000 0004) bit description Symbol Value Description Reset value DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1.
Page 961 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) If UNIFY = 0 in the CONFIG register, this register can be written to as two registers LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.
Page 962 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 721. SCT stop condition register (STOP - address 0x4000 0010) bit description Symbol Description Reset value 15:0 STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
Page 963 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) If UNIFY = 0 in the CONFIG register, this register can be written to as two registers STATE_L and STATE_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.
Page 964 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 725. SCT input register (INPUT - address 0x4000 0048) bit description Symbol Description Reset value AIN3 Real-time status of input 3. AIN4 Real-time status of input 4. AIN5 Real-time status of input 5.
Page 965 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 726. SCT match/capture registers mode register (REGMODE - address 0x4000 004C) bit description Symbol Description Reset value 15:0 REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).
Page 966 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 728. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Value Description Reset value SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
Page 967 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 728. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Value Description Reset value SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
Page 968 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 729. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O2RES Effect of simultaneous set and clear on output 2. No change.
Page 969 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 729. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O10RES Effect of simultaneous set and clear on output 10. No change.
Page 970 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 730. SCT DMA 0 request register (DMAREQ0 - address 0x4000 005C) bit description Symbol Description Reset value 15:0 DEV_0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
Page 971 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.6.17 SCT conflict enable register This register enables the “no change conflict” events specified in the SCT conflict resolution register to request an IRQ. Table 734. SCT conflict enable register (CONEN - address 0x4000 00F8) bit description...
Page 972 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) There is no “write-through” from Reload registers to Match registers. Before starting a counter, software can write one value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle.
Page 973 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1) If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CAPCTRLn_L and CAPCTRLn_H.
Page 974 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) When the UNIFY bit is 0, each event is associated with a particular counter by the HEVENT bit in its event control register. An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register.
Page 975 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 741. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Symbol Value Description Reset value STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
Page 976 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.7 Functional description 30.7.1 Match logic Counter H Match Match Reload Match i H Reg i H UNIFY Match Match Reload Match i L Reg i L Counter L Fig 102. Match logic 30.7.2 Capture logic...
Page 977 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) H matches select L matches MATCHSELi inputs event i select outputs IOSELi OUTSELi IOCONDi COMBMODEi select STATEMASKi H STATE L STATE HEVENTi Fig 104. Event selection 30.7.4 Output generation Figure 105 shows one output slice of the SCT.
Page 978 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.7.6 Clearing the prescaler When enabled by a non-zero PRE field in the Control register, the prescaler acts as a clock divider for the counter, like a fractional part of the counter value. The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons: •...
Page 979 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Remark: The SCT can also be used to launch timed or other event-determined transfers among other peripherals or between other peripherals and memory. It is not necessary to transfer data in and out of the SCT in response to a DMA request.
Page 980 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) Table 745. Alternate address map for DMA halfword access Match register Capture register Standard offset DMA halfword offset MATCHREL1_L CAPCTRL1_L 0x204 0x282 MATCHREL1_H CAPCTRL1_H 0x206 0x2C2 UM10503 All information provided in this document is subject to legal disclaimers.
Page 981 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.7.10 SCT operation In its simplest, single-state configuration, the SCT operates as an event controlled one- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior.
Page 982 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.7.10.1.3 Configure events and event responses 1. Define when each event can occur in the following way in the EVCTRL registers (up to 16, one register per event): – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE.
Page 983 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) 30.7.10.1.4 Configure multiple states 1. In the EVSTATEMASK register for each event (up to 16 events, one register per event), select the state or states (up to 31) in which this event is allowed to occur.
Page 984 UM10503 NXP Semiconductors Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT) – When the counters are stopped, both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again. – When the counter are halted, only a software write to clear the HALT bit can start the counter again.
Page 985 Rev. 2.1 — 10 December 2015 User manual 31.1 How to read this chapter The SCT with dither engine is available on all flash-based LPC43xx/LPC43Sxx parts. The SCT implemented here is identical to the SCT implemented for flashless parts except for the following additions: •...
Page 986 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with – 32 states – Match register 0 to 5 support a fractional component for the dither engine 31.3 Register description The register addresses of the State Configurable Timer are shown in Table 746.
Page 987 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 746. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset DITHER 0x018 SCT dither condition register Table 753 DITHER_L...
Page 988 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 746. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset FRACMAT0 to 5 0x140 to Fractional match registers 0 to 5 for SCT match...
Page 989 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 746. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset CAPCTRL0_L to 0x280 to CAPCTRL alias registers. SCT capture control...
Page 990 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 746. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset EV15_STATE 0x378 SCT event state register 15 0x0000 0000...
Page 991 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 747. SCT configuration register (CONFIG, address 0x4000 0000) bit description Symbol Value Description Reset value UNIFY SCT operation 16-bit.The SCT operates as two 16-bit counters named L and H.
Page 992 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 747. SCT configuration register (CONFIG, address 0x4000 0000) bit description …continued Symbol Value Description Reset value AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event.
Page 993 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 748. SCT control register (CTRL, address 0x4000 0004) bit description Symbol Value Description Reset value 12:5 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock.
Page 994 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 749. SCT limit register (LIMIT, address 0x4000 0008) bit description Symbol Description Reset value 15:0 LIMMSK_L If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
Page 995 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with The bits in this register select which events, if any, clear the STOP bit in the Control register. (Since no events can occur when HALT is 1, only software can clear the HALT bit by writing the Control register.)
Page 996 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 753. SCT dither condition register (DITHER, address 0x4000 0018) bit description Symbol Description Reset value 15:0 DITHMSK_L If bit n is one, the event n causes the dither engine to advance...
Page 997 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with • set and clear outputs • limit, stop, and start the counter • cause interrupts and DMA requests • modify the state variable The value of a state variable is completely under the control of the application. If an application does not use states, the value of the state variable remains zero, which is the default value.
Page 998 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 756. SCT input register (INPUT, address 0x4000 0048) bit description Symbol Description Reset value SIN3 Input 3 state synchronized to the SCT clock. SIN4 Input 4 state synchronized to the SCT clock.
Page 999 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Software can read this register at any time to sense the state of the outputs. Table 758. SCT output register (OUTPUT, address 0x4000 0050) bit description Symbol Description Reset...
Page 1000 UM10503 NXP Semiconductors Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with Table 759. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x4000 0054) bit description Symbol Value Description Reset value SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.

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