Kenwood DV-505 Service Manual page 6

DV-505/DVF-4050/-S
Port No.
12 PIO3(6)
13 PIO3(7) DVD RESET
39 PIO4(0)HP MUTE
40 PIO4(1)
41 PIO4(2)
42 PIO4(3) DAC RESET
43 PIO4(4) PLL CS
44 PIO4(5) DAC CLOCK
45 PIO4(6) DAC DATA
46 PIO4(7) DAC CS
Reserved
20 B WCLK
21 B V4
22 NRSS OUT
103 ADC SCLK
104 ADC LRCK
105 ADC DATA
106 ADC PCMCLK
EMI Interface
161~170 CPU ADR(1~10)
173~183 CPU ADR(11~21)
141~148 CPU DATA(0~7)
151~158 CPU DATA(8~15)
138 CPU RAS1
131 CPU WAIT
130 CPU RW
128 CPU BE(0)
129 CPU BE(1)
139 CPU CAS0
140 CPU CAS1
135 CPU CE(0)
134 CPU CE(1)
133 CPU CE(2)
132 CPU CE(3)
118 CPU PRO CLK
117 CPU OE
Interrupt
127 IRQ(0)
126 IRQ(1)
125 IRQ(2)
Timers
116 PWM0
115 PWM1
114 PWM2
JTAG
113 TCK
112 TDI
111 TDO
110 TMS
109 TRST4
Front-end
16 B DATA
17 B BCLK
6
CIRCUIT DESCRIPTION
Port Name I/O
I/O
I/O
-
-
-
-
-
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I
O
O
O
O
O
O
O
O
O
O
I/O
I
I
I
I/O
I/O
I/O
I
I
O
I
I
I
I
Main Function
PARA DATA(6)/
Unused
UART1 CTS(CTS1)
PARA DATA(7)/
PIO3(7)
UART2 CTS(CTS2)
Unused
Unused
Unused
Unused
Unused
DAC clock
DAC data
PIO4(0~7)
Unused
Connected to GND
Unused
Unused
Unused
Unused
Unused
ADR(1~10)
ADR(11~21)
DATA(0~7)
DATA(8~15)
Unused
Connected to GND
Unused
BYTE 0 ENABLE
BYTE 1 ENABLE
Unused
Unused
Unused
Unused
Chip Sel. BANK2
Chip Sel. BANK3
SDRAM clock
Output enable
Unused
Unused
IRQ(2) (MD IRQ)
Unused HSYNC
Pulse width modula o Boot from ROM3
Unused VSYNC
Test clock
Test data in
Test data out
Test mode select
Test reset
12S data SER Data
12S bit clock SER BCLK
Alternate function
Input Output
COMP OUT1
COMP OUT0
YC(0~7)