Samsung GT-P5100 Service Manual page 88

- UCP300
NC
17 16 15
MEM_BFC MEM_SDC
A
NC MEM_A_8
LKO_1
MEM_A_2 MEM_BFC MEM_CK
B
MEM_A_9
3 LKO_0
MEM_A_1 MEM_A_2
C
xx
0 2
MEM_A_1 MEM_A_2
D
x
1 1
MEM_A_1 MEM_A_2 MEM_RAS
E
x
2 0
MEM_A_1 MEM_BC1
F
VDD_IO18
3 _n
MEM_A_1 MEM_BC3 MEM_A_1 MEM_BE0
G
4 _n 9
MEM_A_1 MEM_A_1 MEM_CS2
H
x
5 7
MEM_A_1 MEM_A_1 MEM_CS0
J
VDD_IO18
6 8
MEM_WA
K
VDD_MIPI VDDCORE
x
IT_n
L
F32K VSS x
MIPI_HSI _ MIPI_HSI _
M
OSC32K VSS
TX_RDY RX_FLG
N
VDD_RTC USB_ID VSS_USB
x
VDD_USB
P
USB_TEST VBUS x
USB_DMI VDD_USBI
R
xx
NUS O
USB_DPL USB_TUN VDD_USB
T
CC_RST
US E _PD
U
NC VSS VDD_IO12 CC_CLK
17 16 15
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Distribution, transmission, or infringement of any content or data from this document without Samsung's written authorization is strictly prohibited.
Bottom View
14 13 12 11 10
MEM_BC0
MEM_A_0 MEM_A_1 MEM_A_2 MEM_A_3 MEM_A_4
LKO _n
MEM_RD_ MEM_WR MEM_BC2
VDD_IO18
E n _n _n
MEM_A_5
x x x
MEM_AD_ MEM_AD_ MEM_AD_ MEM_AD_
VSS
13 12 11 7
VDDCORE MEM_AD_
VDDCORE VDDCORE
_n _EBU 8
MEM_AD_
VSS xx x
15
MEM_BE1 MEM_AD_ MEM_AD
x
_n _n 1 V_n
MEM_CS3 MEM_AD_ MEM_AD_
x
_n _n 0 10
MEM_CS1 MEM_AD_
VSS
x
_n _n 14
VSS VDD_IO18 EINT3
x
MIPI_HSI _ MIPI_HSI _
VSS x VSS
RX_RDY TX_FLG
MIPI_HSI _
xx x
TX_WAKE
MIPI_HSI _ MIPI_HSI _
VDD_IO18 I2C1_SCL
RX_DATA TX_DATA
MIPI_HSI _
RX_WAK SYS_CLK VSS_PLL CLKOUT2 I2C1_SDA
_ANA
E
VDD_PLL
x x x
VDD_DIG
CC_IO VDD_SIM DMINUS
RF
HSIC_USB HSIC_USB
DPLUS ALERT_N
_DATA _STRB
14 13 12 11 10
9 8 765432
MEM_AD_ FCDP_RB
VPLL
9 n
MEM_CAS DSP_AUDI
MEM_A_6 FWP
_n O_IN1
MEM_A_7
x x x
MEM_AD_
VSS
x x
3
MEM_AD_ MEM_AD_
x x
6 5
MEM_AD_
x x TRIG_B
4
MEM_AD_
VSS
x xxx
2
RESERVE
VDDCORE M1
x
D
VSS M2
x x
ETM11_T
ETM11_T
VDDCORE VDD_IO18 RACEPKT
x
RACECLK
ETM11_T ETM11_T
VDD_MM MMCI1_C
RACEPKT x RACEPKT
C MD
5
MMCI1_D MMCI1_D
EINT1 EINT2
x
AT_3
MMCI1_C
VPP CLKOUT0
x x
HW_MON
VSS xx
2
HW_MON
VSS VDDCORE RESET2_N
x
1
XRESET_ Di3_TX_D Di3_TX_D
TCK TRIG_IN
N ATX AT
SYSCLKE Di3_RX_D Di3_RX_D
TMS
N ATX AT
9 8 765432
8-69
Level 3 Repair
1
VDD_VBA
SD2_SW SD2_SW NC
T_SD2
VIO_12 VSS_SD2
x x x
VDD_VSD VDD_VBA
VUSB_PD SD2_FB
x
2 T_SD1
ANAMON SD1_FB SD1_SW
x x
VSS FSS SD1_SW
x x
VDD_VBA VUSB_AN
x VRTC VSS_SD1
T_PMU A
VPMU VSIM
x
AGND ON1 VUSB_IO
x x
RESET_P
M3 M4 WRDWN_ ON2_N VREF
N
ETM11_T
REF_CLK RESET_B
TM_EN RACEPKT
_EN B_N
4 7
ETM11_T ETM11_T ETM11_T
RACEPKT x RACEPKT RACEPKT
6 2 3 1
ETM11_T
MMCI1_D MMCI1_C MMCI1_D
RACEPKT
AT_0 AT_2 LK AT_1
0
I2S2_CLK I2S2_CLK
T_OUT0
x
D 1 0
x T_OUT1 I2S2_TX I2S2_RX
NC I2S2_WA1 I2S2_WA0
x
USIF1_TX USIF1_RX USIF1_SC
TRST_n
D_MTSR D_MRST LK
USIF1_RT USIF1_CT
TDI TDO NC
S_N S_N
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U