Table of Contents
Advertisement
TABLE B1-3. P2 - CPM Expansion - Interconnect Signals
Pin No.
Signal Name
D20
FETHMDIO (PC12)
D21
HREQTRQ
D22
N.C.
D23
D24
HRRQACK
D25
PC7
D26
PC6
D27
SMCTX1(PC5)
D28
SMCRX1(PC4)
D29
HA0
D30
HA1
D31
HA2
D32
HA3
a. The functions in parenthesis, are MSC8101's parallel I/Os.
b. Normally connected to ATMTFCLK on the ADS.
c. MS bit.
d. For that matter, both 100-Base-T and 10-Base-T.
MOTOROLA
Freescale Semiconductor, Inc.
Attribute
I/O, T.S.
Fast-Ethernet Port Management Data I/O. This signal serves as
bidirectional serial data line, qualified by FETHMDC, to allow read
/ write the LXT970's internal registers.
When the Ethernet port is disabled, this line may be used for any
available function of PC12.
O, T.S.
When the HDI16 is enabled and programmed to interface to a
single host request, this pin is the host request output (HREQ).
This pin can be used for host DMA requests in host DMA mode.
When the HDI16 is programmed to interface to a double host
request, this pin is the transmit host request output (HTRQ).
Tristated when HDI16 is disabled. Present as well as at P4
connector.
-
Not connected.
I/O, T.S.
When the HDI16 is enabled and programmed to interface to a
single host request, this pin is the host acknowledge Schmitt
trigger input in host DMA mode (HACK). The polarity of the host
DMA acknowledge is programmable. When the HDI16 is
programmed to interface to a double host request, this pin is the
receive host request output (HRRQ). The direction of this line
may be programmed by BCSR0/1. See
Description" on page 55
I/O, T.S.
MSC8101's Port C (7:6) Parallel I/O lines. May be used to any of
their available functions.
I/O, T.S.
When RS232 port #2 is enabled, this signal is the transmit data
line for SMC1 port. When this port is disabled, this signal may be
used to any available alternate function for PC5.
I/O, T.S.
When RS232 port #2 is enabled, this signal is the receive data
line for SMC1 port. When this port is disabled, this signal may be
used to any available alternate function for PC4.
I
Host Interface Address Line 0. Tristated when Host I/F is
disabled. Present as well as at P4 connector.
I
Host Interface Address Line 1. Tristated when Host I/F is
disabled. Present as well as at P4 connector.
I
Host Interface Address Line 2. Tristated when Host I/F is
disabled. Present as well as at P4 connector.
I
Host Interface Address Line 3. Tristated when Host I/F is
disabled. Present as well as at P4 connector.
MSC8101ADS RevB User's Manual
For More Information On This Product,
Go to: www.freescale.com
Description
TABLE 5-9. "BCSR0
.
B-89
Advertisement
Table of Contents
