NEC PD78052 User Manual
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NEC PD78052 User Manual

Pd78054 series; pd78054y series 8-bit single-chip microcontrollers
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Table of Contents

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User's Manual
PD78054, 78054Y SUBSERIES
8-BIT SINGLE-CHIP MICROCONTROLLERS
PD78052
PD78053
PD78054
PD78P054
PD78055
PD78056
PD78058
PD78P058
PD78052(A)
PD78053(A)
PD78054(A)
Document No. U11747EJ5V0UM00 (5th edition)
Date Published April 1998 N CP (K)
©
1992
Printed in Japan
PD78052Y
PD78053Y
PD78054Y
PD78055Y
PD78056Y
PD78058Y
PD78P058Y

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Summary of Contents for NEC PD78052

  • Page 1 User’s Manual PD78054, 78054Y SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLERS PD78052 PD78053 PD78054 PD78P054 PD78055 PD78056 PD78058 PD78P058 PD78052(A) PD78053(A) PD78054(A) Document No. U11747EJ5V0UM00 (5th edition) Date Published April 1998 N CP (K) © 1992 Printed in Japan PD78052Y PD78053Y PD78054Y PD78055Y...
  • Page 2 [MEMO]...
  • Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
  • Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
  • Page 5 The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
  • Page 6 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
  • Page 7 Page Throughout Addition of PD78052(A),78053(A), 78054(A) to the applicable types Deletion of PD78P054Y from the applicable types Deletion of the following package from the PD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y Subseries: • 80-pin plastic QFP (14 p. 233 Addition of Figure 9-10.
  • Page 8 [MEMO]...
  • Page 9 (common to the 78K/0 Series). PD78054, 78054Y Pin functions Internal block functions Interrupt Other on-chip peripheral functions PREFACE : PD78052, 78053, 78054, 78P054, 78055, 78056, PD78058, 78P058, 78052(A), 78053(A), 78054(A) PD78058Y, 78P058Y Subseries User’s Manual (This manual) CPU functions...
  • Page 10 How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For users who use this document as the manual for the PD78052(A), 78053(A), and 78054(A): The only differences between the to 1.9 Differences between Standard Quality Grade Products and (A) Products).
  • Page 11 Chapter Organization: This manual divides the descriptions for the PD78054 and 78054Y Subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter 1 Outline ( PD78054 Subseries) Chapter 2 Outline ( PD78054Y Subseries) Chapter 3 Pin Function ( PD78054 Subseries) Chapter 4...
  • Page 12 Differences between PD78054 and PD78054Y Subseries: The PD78054 and PD78054Y Subseries are different in the following functions of the serial interface channel 0. Modes of serial interface channel 0 3-wire serial I/O mode 2-wire serial I/O mode SBI (serial bus interface) mode C (Inter IC) bus mode : Supported —...
  • Page 13 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for PD78054 Subseries Document name PD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet PD78052(A), 78053(A), 78054(A) Data Sheet PD78P054, 78P058 Data Sheet PD78054, 78054Y Subseries User’s Manual 78K/0 Series User’s Manual, Instruction...
  • Page 14 Development Tool Documents (User’s Manuals) Document name RA78K0 Assembler Package RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler CC78K0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS™) Base PG-1500 Controller IBM PC Series (PC DOS™) Base IE-78K0-NS IE-78001-R-A IE-780308-NS-EM1...
  • Page 15 Document name IC PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Microcontroller Related Product Guide—Third Party Manufacturers...
  • Page 16 [MEMO]...

  • Page 17: Table Of Contents

    CHAPTER 1 GENERAL ( PD78054 Subseries) ... Features ... Applications ... Ordering Information ... Quality Grade ... Pin Configuration (Top View) ... 78K/0 Series Expansion ... Block Diagram ... Outline of Function ... Differences between Standard Quality Grade Products and (A) Products ... 1.10 Mask Options ...
  • Page 18 3.2.18 3.2.19 3.2.20 (PROM versions only) ... 3.2.21 IC (Mask ROM version only) ... Input/output Circuits and Recommended Connection of Unused Pins ... CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) ... Pin Function List ... 4.1.1 Normal operating mode pins ... 4.1.2 PROM programming mode pins (PROM versions only) ...
  • Page 19 5.3.3 Table indirect addressing ... 5.3.4 Register addressing ... Operand Address Addressing ... 5.4.1 Implied addressing ... 5.4.2 Register addressing ... 5.4.3 Direct addressing ... 5.4.4 Short direct addressing ... 5.4.5 Special-Function Register (SFR) addressing ... 5.4.6 Register indirect addressing ... 5.4.7 Based addressing ...
  • Page 20 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ... Outline of Timers Incorporated in the PD78054, 78054Y Subseries ... 16-Bit Timer/Event Counter Functions ... 16-Bit Timer/Event Counter Configuration ... 16-Bit Timer/Event Counter Control Registers ... 16-Bit Timer/Event Counter Operations ... 8.5.1 Interval timer operations ... 8.5.2 PWM output operations ...
  • Page 21 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT ... 13.1 Buzzer Output Control Circuit Functions ... 13.2 Buzzer Output Control Circuit Configuration ... 13.3 Buzzer Output Function Control Registers ... CHAPTER 14 A/D CONVERTER ... 14.1 A/D Converter Functions ... 14.2 A/D Converter Configuration ... 14.3 A/D Converter Control Registers ...
  • Page 22 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ... 18.1 Serial Interface Channel 1 Functions ... 18.2 Serial Interface Channel 1 Configuration ... 18.3 Serial Interface Channel 1 Control Registers ... 18.4 Serial Interface Channel 1 Operations ... 18.4.1 Operation stop mode ... 18.4.2 3-wire serial I/O mode operation ...
  • Page 23 23.2 Standby Function Operations ... 23.2.1 HALT mode ... 23.2.2 STOP mode ... CHAPTER 24 RESET FUNCTION ... 24.1 Reset Function ... CHAPTER 25 ROM CORRECTION ... 25.1 ROM Correction Functions ... 25.2 ROM Correction Configuration ... 25.3 ROM Correction Control Registers ... 25.4 ROM Correction Application ...
  • Page 24 OS for IBM PC ... Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A ... APPENDIX C EMBEDDED SOFTWARE ... APPENDIX D REGISTER INDEX ... Register Index ... APPENDIX E REVISION HISTORY ...
  • Page 25 Memory Map ( PD78056, 78056Y) ... 5-7. Memory Map ( PD78058, 78058Y) ... 5-8. Memory Map ( PD78P058, PD78P058Y) ... 5-9. Data Memory Addressing ( PD78052, 78052Y) ... 5-10. Data Memory Addressing ( PD78053, 78053Y) ... 5-11. Data Memory Addressing ( PD78054, 78054Y) ... 5-12.
  • Page 26 Figure No. 6-18. P130 and P131 Block Diagram ... 6-19. Port Mode Register Format ... 6-20. Pull-Up Resistor Option Register Format ... 6-21. Memory Expansion Mode Register Format ... 6-22. Key Return Mode Register Format ... 7-1. Block Diagram of Clock Generator ... 7-2.
  • Page 27 Figure No. 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) ... 8-24. Control Register Settings for Pulse Width Measurement by Means of Restart ... 8-25. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) ...
  • Page 28 Figure No. 12-1. Remote Controlled Output Application Example ... 12-2. Clock Output Control Circuit Block Diagram ... 12-3. Timer Clock Select Register 0 Format ... 12-4. Port Mode Register 3 Format ... 13-1. Buzzer Output Control Circuit Block Diagram ... 13-2.
  • Page 29 Figure No. 16-17. Data ... 16-18. Acknowledge Signal ... 16-19. BUSY and READY Signals ... 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) ... 16-21. RELT and CMDD Operations (Slave) ... 16-22. ACKT Operation ... 16-23. ACKE Operations ... 16-24. ACKD Operations ...
  • Page 30 Figure No. 17-26. Slave Wait Release (Reception) ... 17-27. SCK0/SCL/P27 Pin Configuration ... 17-28. SCK0/SCL/P27 Pin Configuration ... 17-29. Logic Circuit of SCL Signal ... 18-1. Serial Interface Channel 1 Block Diagram ... 18-2. Timer Clock Select Register 3 Format ... 18-3.
  • Page 31 Figure No. 19-12. 3-Wire Serial I/O Mode Timing ... 19-13. Circuit of Switching in Transfer Bit Order ... 19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1) ... 19-15. Receive Buffer Register Read Disable Period ... 20-1. Real-time Output Port Block Diagram ... 20-2.
  • Page 32 Figure No. 23-3. HALT Mode Release by RESET Input ... 23-4. STOP Mode Release by Interrupt Request Generation ... 23-5. Release by STOP Mode RESET Input ... 24-1. Block Diagram of Reset Function ... 24-2. Timing of Reset Input by RESET Input ... 24-3.
  • Page 33 Table No. 1-1. Differences between Standard Quality Grade Products and (A) Products ... 1-2. Mask Options of Mask ROM Versions ... 2-1. Mask Options of Mask ROM Versions ... 3-1. Pin Input/Output Circuit Types ... 4-1. Pin Input/Output Circuit Types ... 5-1.
  • Page 34 Table No. 9-8. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges ... 9-9. Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ... 9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ...
  • Page 35 Table No. 19-7. Receive Error Causes ... 20-1. Real-time Output Port Configuration ... 20-2. Operation in Real-time Output Buffer Register Manipulation ... 20-3. Real-time Output Port Operating Mode and Output Trigger ... 21-1. Interrupt Source List ... 21-2. Various Flags Corresponding to Interrupt Request Sources ... 21-3.
  • Page 36 [MEMO]...

  • Page 37: Chapter 1 General ( Pd78054 Subseries)

    CHAPTER 1 GENERAL ( PD78054 Subseries) 1.1 Features On-chip high-capacity ROM and RAM Type Program Memory (ROM) Part Number PD78052 16 Kbytes PD78053 24 Kbytes PD78054 32 Kbytes Note1 PD78P054 32 Kbytes PD78055 40 Kbytes PD78056 48 Kbytes PD78058 60 Kbytes...

  • Page 38: Applications

    CHAPTER 1 OUTLINE ( PD78054 Subseries) 1.2 Applications PD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058: Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. PD78052(A), 78053(A), 78054(A): Control unit for automobile electronics, gas detector/breaker, various safety unit, etc.

  • Page 39: Quality Grade

    Remark indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package 14 mm, Resin thickness: 1.4 mm)

  • Page 40: Pin Configuration (Top View)

    CHAPTER 1 OUTLINE ( PD78054 Subseries) 1.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm) PD78P054GC-3B9 • 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) PD78052GC- -8BT, 78053GC- PD78055GC- -8BT, 78056GC- •...
  • Page 41 CHAPTER 1 OUTLINE ( PD78054 Subseries) Pin Identifications A8 to A15 Address Bus AD0 to AD7 Address/Data Bus ANI0 to ANI7 Analog Input ANO0, ANO1 Analog Output ASCK Asynchronous Serial Clock ASTB Address Strobe Analog Power Supply , AV Analog Reference Voltage REF0 REF1 Analog Ground...
  • Page 42 CHAPTER 1 OUTLINE ( PD78054 Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm) PD78P054GC-3B9 • 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) Note PD78P054GC-8BT , 78P058GC-8BT • 80-pin plastic TQFP (Fine pitch) (12 PD78P054GK-BE9 •...

  • Page 43: Series Expansion

    CHAPTER 1 OUTLINE ( PD78054 Subseries) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Control 100-pin PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 80-pin PD780058 80-pin PD78058F 80-pin PD78054 64-pin PD780034 64-pin...
  • Page 44 CHAPTER 1 OUTLINE ( PD78054 Subseries) The following shows the major differences between subseries products. Function Subseries Name Capacity Control PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch PD78078 48 K to 60 K PD78070A –...

  • Page 45: Block Diagram

    CHAPTER 1 OUTLINE ( PD78054 Subseries) 1.7 Block Diagram TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL...

  • Page 46: Outline Of Function

    Buzzer output Notes 1. The PD78P054 is the PROM version for the PD78052, 78053, and 78054. 2. The PD78P058 is the PROM version for the PD78055, 78056, and 78058. 3. The capacities of the internal PROM and the internal high-speed RAM can be changed using the memory switching register (IMS).
  • Page 47 Test input Supply voltage Operating ambient temperature Package Notes 1. The PD78P054 is the PROM version for the PD78052, 78053, 78054. 2. The PD78P058 is the PROM version for the PD78055, 78056, 78058. 3. The PD78P054 is under development. PD78052 PD78053...

  • Page 48: Differences Between Standard Quality Grade Products And (A) Products

    CHAPTER 1 OUTLINE ( PD78054 Subseries) 1.9 Differences between Standard Quality Grade Products and (A) Products Table 1-1 shows the differences between the standard quality grade products ( PD78052, 78053, 78054) and (A) products ( PD78052(A), 78053(A), 78054(A)). Table 1-1. Differences between Standard Quality Grade Products and (A) Products...

  • Page 49: Chapter 2 General ( Pd78054Y Subseries)

    CHAPTER 2 GENERAL ( PD78054Y Subseries) 2.1 Features On-chip high-capacity ROM and RAM Type Program Memory (ROM) Part Number PD78052Y 16 Kbytes PD78053Y 24 Kbytes PD78054Y 32 Kbytes 40 Kbytes PD78055Y 48 Kbytes PD78056Y 60 Kbytes PD78058Y Note 1 PD78P058Y 60 Kbytes Notes 1.

  • Page 50: Applications

    80-pin ceramic WQFN (14 Remark indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package 14 mm, Resin thickness: 1.4 mm)

  • Page 51: Pin Configuration (Top View)

    CHAPTER 2 OUTLINE ( PD78054Y Subseries) 2.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) PD78052YGC- -8BT, 78053YGC- PD78055YGC- -8BT, 78056YGC- • 80-pin ceramic WQFN (14 PD78P058YKK-T 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P15/ANI5 P16/ANI6 P17/ANI7...
  • Page 52 CHAPTER 2 OUTLINE ( PD78054Y Subseries) Pin Identifications A8 to A15 Address Bus AD0 to AD7 Address/Data Bus ANI0 to ANI7 Analog Input ANO0 to ANO7 : Analog Output ASCK Asynchronous Serial Clock ASTB Address Strobe Analog Power Supply , AV Analog Reference Voltage REF0 REF1...
  • Page 53 CHAPTER 2 OUTLINE ( PD78054Y Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) PD78P058YGC-8BT • 80-pin ceramic WQFN (14 14 mm) PD78P058YKK-T 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Cautions 1.

  • Page 54: Series Expansion

    CHAPTER 2 OUTLINE ( PD78054Y Subseries) 2.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Control 100-pin PD78075B 100-pin PD78078 100-pin PD78070A PD78070AY 100-pin PD780018AY 80-pin PD780058 PD780058Y 80-pin PD78058F PD78058FY 80-pin...
  • Page 55 CHAPTER 2 OUTLINE ( PD78054Y Subseries) Major differences among Y subseries are tabulated below. Function Subseries Capacity Control PD78078Y 48K to 60K PD78070AY — PD780018AY 48K to 60K PD780058Y 24K to 60K PD78058FY 48K to 60K PD78054Y 16K to 60K PD780034Y 8K to 32K PD780024Y PD78018FY 8K to 60K...

  • Page 56: Block Diagram

    CHAPTER 2 OUTLINE ( PD78054Y Subseries) 2.7 Block Diagram TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SCL/P27 SI1/P20 SO1/P21 SERIAL...

  • Page 57: Outline Of Function

    CHAPTER 2 OUTLINE ( PD78054Y Subseries) 2.8 Outline of Function Part Number Item Internal memory High-speed RAM Buffer RAM Expansion RAM Memory space General register Minimum With main system clock selected instruction With subsystem clock selected execution time Instruction set I/O port A/D converter D/A converter...

  • Page 58: Mask Options

    CHAPTER 2 OUTLINE ( PD78054Y Subseries) Part Number Item Maskable Vectored interrupt Non-maskable source Software Test input Supply voltage Operating ambient temperature Package 2.9 Mask Options The mask ROM versions ( PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production.

  • Page 59: Chapter 3 Pin Function ( Pd78054 Subseries)

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Input Input/ Port 0. output 8-bit input/output port. Note1 Input P10 to P17 Port 1. 8-bit input/output port. Input/ Input/output mode can be specified in 1-bit units.
  • Page 60 CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) (1) Port pins (2/3) Pin Name Input/Output Port 3. Input/ 8-bit input/output port. output Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software.
  • Page 61 CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Input/ Port 12. output 8-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software.
  • Page 62 CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output INTP0 INTP1 INTP2 External interrupt request inputs with specifiable valid edges (rising INTP3 Input edge, falling edge, both rising and falling edges). INTP4 INTP5 INTP6 Input...

  • Page 63: Prom Programming Mode Pins (Prom Versions Only)

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input/Output A8 to A15 Output High-order address bus when expanding external memory Strobe signal output for read operation from external memory Output Strobe signal output for write operation to external memory WAIT...

  • Page 64: Description Of Pin Functions

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.

  • Page 65: P10 To P17 (Port 1)

    These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output functions. (a) SI0, SI1, SO0, SO1 Serial interface serial data input/output pins (b) SCK0 and SCK1 Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins...

  • Page 66: P30 To P37 (Port 3)

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires.

  • Page 67: P40 To P47 (Port 4)

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 8-bit units.

  • Page 68: P70 To P72 (Port 7)

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit units.

  • Page 69: P120 To P127 (Port 12)

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 70: Av Dd

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.2.13 AV Analog power supply pin of A/D converter. Always use the same voltage as that of the V converter is not used. 3.2.14 AV This is a ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the V pin even when neither A/D nor D/A converter is used.

  • Page 71: Input/Output Circuits And Recommended Connection Of Unused Pins

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
  • Page 72 CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name P60 to P63 (Mask ROM version) P60 to P63 (PROM version) P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 RESET REF0 REF1 IC (Mask ROM version)

  • Page 73: Pin Input/Output Circuit Of List

    CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) Figure 3-1. Pin Input/Output Circuit of List (1/2) Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-A pullup enable data P-ch output N-ch disable input enable Type 5-E pullup enable data P-ch output N-ch disable Type 8-A...
  • Page 74 CHAPTER 3 PIN FUNCTION ( PD78054 Subseries) Figure 3-1. Pin Input/Output Circuit of List (2/2) Type 12-A pullup enable data P-ch output N-ch disable input P-ch enable analog output voltage N-ch Type 13-B data output disable medium breakdown input buffer Type 13-D P-ch data...

  • Page 75: Chapter 4 Pin Function ( Pd78054Y Subseries)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Input Input/ Port 0. output 8-bit input/output port. Note1 Input P10 to P17 Port 1. 8-bit input/output port. Input/ Input/output mode can be specified in 1-bit units.
  • Page 76 CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) (1) Port pins (2/3) Pin Name Input/Output Port 3. Input/ 8-bit input/output port. output Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software.
  • Page 77 CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Input/ Port 12. output 8-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software.
  • Page 78 CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output INTP0 INTP1 INTP2 External interrupt request inputs with specifiable valid edges (rising INTP3 Input edge, falling edge, both rising and falling edges). INTP4 INTP5 INTP6 Input...

  • Page 79: Prom Programming Mode Pins (Prom Versions Only)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input/Output A8 to A15 Output High-order address bus when expanding external memory Output Strobe signal output for read operation from external memory Strobe signal output for write operation to external memory WAIT...

  • Page 80: Description Of Pin Functions

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.

  • Page 81: P10 To P17 (Port 1)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 82: P30 To P37 (Port 3)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output, and buzzer output. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 83: P50 To P57 (Port 5)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports.

  • Page 84: P70 To P72 (Port 7)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit units.

  • Page 85: P130 And P131 (Port 13)

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2.10 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 2-bit input/output ports.

  • Page 86: X1 And X2

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.2.16 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2. 4.2.17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2.

  • Page 87: Input/Output Circuits And Recommended Connection Of Unused Pins

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1.
  • Page 88 CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name P60 to P63 (Mask ROM version) P60 to P63 (PROM version) P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0 to P131/ANO1 RESET REF0 REF1...

  • Page 89: Pin Input/Output Circuit Of List

    CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) Figure 4-1. Pin Input/Output Circuit of List (1/2) Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-A pullup enable data P-ch output N-ch disable input enable Type 5-E pullup enable data P-ch output N-ch disable Type 8-A...
  • Page 90 CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries) Figure 4-1. Pin Input/Output Circuit of List (2/2) Type 12-A pullup enable data P-ch output N-ch disable input P-ch enable analog output voltage N-ch Type 13-B data output disable medium breakdown input buffer Type 13-D P-ch data...

  • Page 91: Chapter 5 Cpu Architecture

    CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Each product of the PD78054 and 78054Y Subseries can access the memory space of 64 Kbytes. Figures 5-1 to 5-8 show memory maps. Figure 5-1. Memory Map ( PD78052, 78052Y) FFFFH FF00H FEFFH...

  • Page 92: Memory Map ( Pd78053, 78053Y)

    Figure 5-2. Memory Map ( PD78053, 78053Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space FA80H FA7FH External Memory 39552 Program memory space 6000H 5FFFH...

  • Page 93: Memory Map ( Pd78054, 78054Y)

    Figure 5-3. Memory Map ( PD78054, 78054Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM 1024 FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space FA80H FA7FH External Memory 31360 Program memory space 8000H...

  • Page 94: Memory Map ( Pd78P054)

    Figure 5-4. Memory Map ( PD78P054) FFFFH FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space FA80H FA7FH Program memory space 8000H 7FFFH 0000H CHAPTER 5 CPU ARCHITECTURE Special Function Registers (SFRs) 8 bits...

  • Page 95: Memory Map ( Pd78055, 78055Y)

    Figure 5-5. Memory Map ( PD78055, 78055Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM 1024 FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space FA80H FA7FH External Memory 23168 Program memory space A000H...

  • Page 96: Memory Map ( Pd78056, 78056Y)

    Figure 5-6. Memory Map ( PD78056, 78056Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space FA80H FA7FH External Memory 14976 Program memory space C000H BFFFH...

  • Page 97: Memory Map ( Pd78058, 78058Y)

    CHAPTER 5 CPU ARCHITECTURE Figure 5-7. Memory Map ( PD78058, 78058Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM 1024 FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space F800H F7FFH Expansion RAM 1024 F400H...

  • Page 98: Memory Map ( Pd78P058, Pd78P058Y)

    Figure 5-8. Memory Map ( PD78P058, PD78P058Y) FFFFH Special Function Registers (SFRs) FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH Internal Buffer RAM FAC0H Data memory FABFH space F800H F7FFH Expansion RAM 1024 F400H F3FFH F000H EFFFH Program...

  • Page 99: Internal Program Memory Space

    The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC). Each product of the PD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below. Part number PD78052, 78052Y PD78053, 78053Y PD78054, 78054Y PD78055, 78055Y...

  • Page 100: Internal Data Memory Space

    The PD78054 and 78054Y subseries units incorporate the following RAMs. (1) Internal high-speed RAM The PD78054 and 78054Y Subseries are provided with the internal high-speed RAM as shown below. Table 5-3. Internal High-Speed RAM Capacity Part Number PD78052, 78052Y PD78053, 78053Y PD78054, 78054Y PD78P054 PD78055, 78055Y...

  • Page 101: Data Memory Addressing

    (SFRs) and general registers. This area is between FD00H and FFFFH for the PD78052 and 78052Y, and between FB00H and FFFFH for the PD78053, 78053Y, 78054, 78054Y, 78P054, 78055, 78055Y, 78056, 78056Y, 78058, 78058Y, 78P058, and 78P058Y.

  • Page 102: Data Memory Addressing ( Pd78053, 78053Y)

    Figure 5-10. Data Memory Addressing ( PD78053, 78053Y) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM 8 bits FAC0H FABFH...

  • Page 103: Data Memory Addressing ( Pd78054, 78054Y)

    CHAPTER 5 CPU ARCHITECTURE Figure 5-11. Data Memory Addressing ( PD78054, 78054Y) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM...

  • Page 104: Data Memory Addressing ( Pd78P054)

    Figure 5-12. Data Memory Addressing ( PD78P054) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM 8 bits FAC0H FABFH...

  • Page 105: Data Memory Addressing ( Pd78055, 78055Y)

    CHAPTER 5 CPU ARCHITECTURE Figure 5-13. Data Memory Addressing ( PD78055, 78055Y) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM...

  • Page 106: Data Memory Addressing ( Pd78056, 78056Y)

    Figure 5-14. Data Memory Addressing ( PD78056, 78056Y) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM 8 bits FAC0H FABFH...

  • Page 107: Data Memory Addressing ( Pd78058, 78058Y)

    CHAPTER 5 CPU ARCHITECTURE Figure 5-15. Data Memory Addressing ( PD78058, 78058Y) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM...

  • Page 108: Data Memory Addressing ( Pd78P058, 78P058Y)

    Figure 5-16. Data Memory Addressing ( PD78P058, 78P058Y) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM 8 bits FAC0H FABFH...

  • Page 109: Processor Registers

    5.2 Processor Registers The PD78054 and 78054Y subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.

  • Page 110: Internal High-Speed Ram Area

    This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. The following shows the internal high-speed RAM area of each product. Table 5-4. Internal High-Speed RAM Area Part Number PD78052, 78052Y PD78053, 78053Y PD78054, 78054Y PD78P054...

  • Page 111: Stack Pointer Configuration

    Figure 5-19. Stack Pointer Configuration PC15 PC14 PC13 PC12 PC11 PC10 PC9 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-20 and 5-21. Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before instruction execution.

  • Page 112: General Registers

    5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL).

  • Page 113: General Register Configuration

    Figure 5-22. General Register Configuration FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H CHAPTER 5 CPU ARCHITECTURE (a) Absolute Name 16-Bit Processing (b) Function Name 16-Bit Processing 8-Bit Processing 8-Bit Processing...

  • Page 114: Special Function Register (Sfr)

    5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.

  • Page 115: Special-Function Register List

    Table 5-6. Special-Function Register List (1/3) Address Special-Function Register (SFR) Name FF00H Port0 FF01H Port1 FF02H Port2 FF03H Port3 FF04H Port4 FF05H Port5 FF06H Port6 FF07H Port7 FF0CH Port12 FF0DH Port13 FF10H Capture/compare register 00 FF11H FF12H Capture/compare register 01 FF13H FF14H 16-bit timer register...
  • Page 116 Table 5-6. Special-Function Register List (2/3) Address Special-Function Register (SFR) Name FF38H Correction address register 0 FF39H FF3AH Correction address register 1 FF3BH FF40H Timer clock select register 0 FF41H Timer clock select register 1 FF42H Timer clock select register 2 FF43H Timer clock select register 3 FF47H...
  • Page 117 1. The external access area cannot be accessed in SFR addressing. Access the area with direct addressing. 2. The value after reset depends on products. PD78052, 78052Y: 44H, PD78053, 78053Y: C6H, PD78054, 78054Y: C8H, PD78P054: C8H, PD78055, 78055Y: CAH, 78P058Y: CFH 3.

  • Page 118: Instruction Address Addressing

    5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing.

  • Page 119: Immediate Addressing

    5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11 instruction branches to an area of addresses 0800H through 0FFFH.

  • Page 120: Table Indirect Addressing

    5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire memory space.

  • Page 121: Operand Address Addressing

    5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed.

  • Page 122: Register Addressing

    5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

  • Page 123: Direct Addressing

    5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier addr16 [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] saddr16 (low) saddr16 (high) CHAPTER 5 CPU ARCHITECTURE Description Label or 16-bit immediate data...

  • Page 124: Short Direct Addressing

    5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal high-speed RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 125: Special-Function Register (Sfr) Addressing

    5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Special-function register name...

  • Page 126: Register Indirect Addressing

    5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.

  • Page 127: Based Addressing

    5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1).

  • Page 128: Based Indexed Addressing

    5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1).

  • Page 129: Chapter 6 Port Functions

    6.1 Port Functions The PD78054 and 78054Y subseries units incorporate two input ports and sixty-seven input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins. Port 5 Port 6 Port 7...

  • Page 130: Port Functions ( Pd78054 Subseries)

    Table 6-1. Port Functions ( PD78054 subseries) (1/2) Pin Name Port 0. 8-bit input/output port. Port 1. 8-bit input/output port. P10 to P17 Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software. Port 2.
  • Page 131 Table 6-1. Port Functions ( PD78054 subseries) (2/2) Pin Name Port 6. 8-bit input/output port. Input/output mode can be specified in 1-bit units. Port 7. 3-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software. Port 12.

  • Page 132: Port Functions ( Pd78054Y Subseries)

    Table 6-2. Port Functions ( PD78054Y subseries) (1/2) Pin Name Port 0. 8-bit input/output port. Port 1. P10 to P17 8-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software. Port 2.
  • Page 133 Table 6-2. Port Functions ( PD78054Y subseries) (2/2) Pin Name Port 6. 8-bit input/output port. Input/output mode can be specified in 1-bit units. Port 7. 3-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software. Port 12.

  • Page 134: Port Configuration

    6.2 Port Configuration A port consists of the following hardware: Item Control register Port Pull-up resistor Note MM specifies port 4 input/output. 6.2.1 Port 0 Port 0 is an 8-bit input/output port with output latch. P01 to P06 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0).

  • Page 135: P00 And P07 Block Diagram

    CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 and P07 Block Diagram Figure 6-3. P01 to P06 Block Diagram PUO0 PORT Output Latch (P01 to P06) PM01-PM06 PUO : Pull-up resistor option register PM : Port mode register : Port 0 read signal WR : Port 0 write signal P00/INTP0/TI00, P07/XT1...

  • Page 136: Port 1

    6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 137: Port 2 ( Pd78054 Subseries)

    6.2.3 Port 2 ( PD78054 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 138: P22 And P27 Block Diagram

    Figure 6-6. P22 and P27 Block Diagram PUO2 PORT Output Latch (P22, P27) PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal CHAPTER 6 PORT FUNCTIONS Selector P-ch P22/SCK1,...

  • Page 139: Port 2 ( Pd78054Y Subseries)

    6.2.4 Port 2 ( PD78054Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 140: P22 And P27 Block Diagram

    Figure 6-8. P22 and P27 Block Diagram PUO2 PORT Output Latch (P22 and P27) PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal CHAPTER 6 PORT FUNCTIONS Selector P-ch...

  • Page 141: Port 3

    6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 142: Port 4

    6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on- chip pull-up resistor can be used to them in 8-bit units with pull-up resistor option register L (PUOL).

  • Page 143: Port 5

    6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 144: Port 6

    6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or PROM model is used.

  • Page 145: P60 To P63 Block Diagram

    CHAPTER 6 PORT FUNCTIONS Figure 6-13. P60 to P63 Block Diagram PORT Output Latch (P60 to P63) PM60-PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14. P64 to P67 Block Diagram PUO6 PORT Output Latch...

  • Page 146: Port 7

    6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).

  • Page 147: P71 And P72 Block Diagram

    CHAPTER 6 PORT FUNCTIONS Figure 6-16. P71 and P72 Block Diagram PUO7 PORT Output Latch (P71 and P72) PM71, PM72 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 7 read signal WR : Port 7 write signal P-ch Selector P71/SO2/TxD,...

  • Page 148: Port 12

    6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor can be used as an 8-bit unit by means of pull-up resistor option register H (PUOH).

  • Page 149: Port 13

    6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be used as a 2-bit unit by means of pull-up resistor option register H (PUOH).

  • Page 150: Port Function Control Registers

    6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) These registers are used to set port input/output in 1-bit units.

  • Page 151: Port Mode Register And Output Latch Settings When Using Dual-Functions

    Table 6-5. Port Mode Register and Output Latch Settings when Using Dual-Functions Pin Name P02 to P06 Note1 Note1 P10 to P17 P30 to P32 P33, P34 P40 to P47 P50 to P57 P120 to P127 (Note1) P130, P131 Notes 1.

  • Page 152: Port Mode Register Format

    Figure 6-19. Port Mode Register Format Symbol PM06 PM05 PM04 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM12 PM127 PM126...

  • Page 153: Pull-Up Resistor Option Register Format

    (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL.

  • Page 154: Memory Expansion Mode Register Format

    (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-21. Memory Expansion Mode Register Format Symbol Single-chip/Memory MM2 MM1 MM0...

  • Page 155: Key Return Mode Register Format

    (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-22.

  • Page 156: Port Function Operations

    6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 157: Operations On Input/Output Port

    6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
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  • Page 159: Chapter 7 Clock Generator

    CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).

  • Page 160: Block Diagram Of Clock Generator

    Figure 7-1. Block Diagram of Clock Generator XT1/P07 Subsystem Clock Oscillator Main System Clock Scaler Oscillator STOP CHAPTER 7 CLOCK GENERATOR Prescaler MCC FRC CLS CSS PCC2 PCC1 Oscillation Mode Processor Clock Control Register Selection Register Internal Bus Watch Timer, Clock Output Function Prescaler...

  • Page 161: Clock Generator Control Register

    7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor.

  • Page 162: Processor Clock Control Register Format

    Figure 7-3. Processor Clock Control Register Format Symbol <7> <6> <5> <4> CPU CIock (f PCC2 PCC1 PCC0 Other than above Setting prohibited CPU Clock Status Main system clock Subsystem clock Subsystem Clock Feedback Resistor Selection Internal feedback resistor used Internal feedback resistor not used Main System Clock Oscillation Control Oscillation possible...

  • Page 163: Relationship Between Cpu Clock And Minimum Instruction Execution Time

    The fastest instruction of the PD78054 and 78054Y Subseries is executed with two clocks of the CPU clock. Therefore, relationships between the CPU clock (f Table 7-2. Table 7-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (f Remarks 1.

  • Page 164: Oscillation Mode Selection Register Format

    (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock.

  • Page 165: System Clock Oscillator

    7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.

  • Page 166: Subsystem Clock Oscillator

    7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin.
  • Page 167 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Incorrect Oscillator Connection (2/2) (c) Changing high current is too near a signal conductor (e) Signals are fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.

  • Page 168: Scaler

    7.4.3 Scaler The scaler divides the main system clock oscillator output (f 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1 : Connect to V XT2 : Leave open.

  • Page 169: Clock Generator Operations

    7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).

  • Page 170: Main System Clock Operations

    7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.

  • Page 171: Subsystem Clock Operations

    Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
  • Page 172 Set Values before Switchover PCC2 PCC1 PCC0 PCC2 PCC2 PCC1 PCC0 16 instructions 8 instructions 4 instructions 4 instructions 2 instructions 2 instructions 1 instruction 1 instruction 1 instruction 1 instruction Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock. 2.

  • Page 173: System Clock And Cpu Clock Switching Procedure

    7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching RESET Interrupt Request Signal System Clock CPU Clock Minimum Speed Operation Wait (26.2 ms : 5.0 MHz) Internal Reset Operation (1) The CPU is reset by setting the RESET signal to low level after power-on.
  • Page 174 [MEMO]...

  • Page 175: Chapter 8 16-Bit Timer/Event Counter

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated in the PD78054, 78054Y Subseries This chapter explains 16-bit timer/event counter. Before that, the timers incorporated into the PD78054, 78054Y Subseries and related circuits are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output.

  • Page 176: Timer/Event Counter Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operations Operating Interval timer mode External event counter Timer output PWM output Pulse width measurement Function Square-wave output One-shot pulse output Interrupt source Test input Notes 1. Watch timer can perform both watch timer and interval timer functions at the same time. 2.

  • Page 177: 16-Bit Timer/Event Counter Functions

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width measurement can be used at the same time.

  • Page 178: Bit Timer/Event Counter Square-Wave Output Ranges

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 TI00 input cycle — (400 ns) (400 ns) (800 ns) (800 ns)

  • Page 179: 16-Bit Timer/Event Counter Configuration

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-Bit Timer/Event Counter Configuration Item Timer register Register Timer output Control register Note Refer to Figure 21-1. Basic Configuration of Interrupt Function. Figure 8-1.

  • Page 180: Bit Timer/Event Counter Output Control Circuit Block Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram PWM Pulse Output Control Circuit CRC02 INTTM01 CRC00 INTTM00 Edge TI00/P00/ Detection INTP0 Circuit ES11 ES10 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 External Interrupt Mode Register 0 Remark The circuitry enclosed by the dotted line is the output control circuit.

  • Page 181: Intp0/Ti00 Pin Valid Edge And Cr00 Capture Trigger Valid Edge

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0).

  • Page 182: 16-Bit Timer/Event Counter Control Registers

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the capture operation and retains the current data. However, the interrupt request flag (PIF0) is set. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses.

  • Page 183: Timer Clock Selection Register 0 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Symbol <7> CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 TCL0 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 (32.768 kHz) Other than above Setting prohibited 16-Bit Timer Register Count Clock Selection TCL06 TCL05 TCL04 TI00 (Valid edge specifiable) Watch timer output (INTTM 3)
  • Page 184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.

  • Page 185: Bit Timer Mode Control Register Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. 16-Bit Timer Mode Control Register Format Symbol TMC0 TMC03 TMC02 TMC01 OVF0 OVF0 16-Bit Timer Register Overflow Detection Overflow not detected Overflow detected Operating Mode TMC03 TMC02 TMC01 Clear Mode Selection Operation stop (TM0 cleared to 0) PWM mode (free running)

  • Page 186: Capture/Compare Control Register 0 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-5.

  • Page 187: Bit Timer Output Control Register Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-6. 16-Bit Timer Output Control Register Format Symbol <6> <5> <3> OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 Cautions 1. Timer operation must be stopped before setting TOC0 (however, except OSPT). 2. If LVS0 and LVR0 are read after data is set, they will be 0. 3.

  • Page 188: Port Mode Register 3 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH.

  • Page 189: External Interrupt Mode Register 0 Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Symbol INTM0 ES31 ES30 ES21 ES20 ES11 ES10...

  • Page 190: Sampling Clock Select Register Format

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select registers (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction.

  • Page 191: 16-Bit Timer/Event Counter Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.

  • Page 192: Interval Timer Configuration Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM3 TI00/P00/INTP0 Figure 8-12. Interval Timer Operation Timings Count Clock TM0 Count Value 0000 0001 Count Start CR00 INTTM00 Interval Time Remark Interval time = (N + 1) 16-Bit Timer Register (TM0) 0000 0001 Clear...

  • Page 193: Pwm Output Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time TCL06 TCL05 TCL04 MCS = 1 TI00 input cycle Setting prohibited (400 ns) (800 ns) (1.6 s) watch timer output cycle Other than above Setting prohibited Remarks 1.

  • Page 194: Control Register Settings For Pwm Output Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) TMC0 (b) Capture/compare control register 0 (CRC0) CRC0 (c) 16-bit timer output control register (TOC0) OSPT OSPE TOC0 Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with PWM output. See the description of the respective control registers for details.

  • Page 195: Example Of D/A Converter Configuration With Pwm Output

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V ) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. capture/compare register 00 (CR00) value : External switching circuit reference voltage Figure 8-14.

  • Page 196: Ppg Output Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/ compare register 00 (CR00), respectively.

  • Page 197: Pulse Width Measurement Operations

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.

  • Page 198: Configuration Diagram For Pulse Width Measurement By Free-Running Counter

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 TI00/P00/INTP00 Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input...

  • Page 199: Control Register Settings For Two Pulse Width Measurements With Free-Running Counter

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin.
  • Page 200 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input CR00 Captured Value INTP1 OVF0 FFFF...
  • Page 201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set.

  • Page 202: Two Capture Registers (With Rising Edge Specified)

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count Clock TM0 Count Value 0000 0001 FFFF 0000 TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1-D0)

  • Page 203: Control Register Settings For Pulse Width Measurement By Means Of Restart

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).

  • Page 204: External Event Counter Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.

  • Page 205: External Event Counter Configuration Diagram

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram TI00 Valid Edge Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) TI00 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005 CR00 INTTM0 Caution When reading the external event counter count value, TM0 should be read.

  • Page 206: Square-Wave Output Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to the 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1.

  • Page 207: Square-Wave Output Operation Timing

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing Count Clock TM0 Count Value 0000 0001 0002 CR00 INTTM0 TO0 Pin Output Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 TI00 input cycle —...

  • Page 208: One-Shot Pulse Output Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input). (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one-shot pulse is output from the TO0/P30 pin.

  • Page 209: Timing Of One-Shot Pulse Output Operation Using Software Trigger

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 CR01 Set Value CR00 Set Value OSPT INTTM01 INTTM00 TO0 Pin Output Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively.

  • Page 210: Control Register Settings For One-Shot Pulse Output Operation Using External Trigger

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger.
  • Page 211 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34. Timing of One-Shot Pulse Output Operation Using External Trigger (With Rising Edge Specified) Set 08H to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 CR01 Set Value CR00 Set Value TI00 Pin Input INTTM01 INTTM00...

  • Page 212: 16-Bit Timer/Event Counter Operating Precautions

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) starts asynchronously with the count pulse.

  • Page 213: Capture Register Data Retention Timing

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge.

  • Page 214: Operation Timing Of Ovf0 Flag

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. CR00 is set to FFFFH. When TM0 is counted up from FFFFH to 0000H. Figure 8-38.

  • Page 215: Chapter 9 8-Bit Timer/Event Counters 1 And 2

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode).

  • Page 216: Bit Timer/Event Counters 1 And 2 Interval Times

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time MCS = 1 MCS = 0 (400 ns) (800 ns) (800 ns)

  • Page 217: Bit Timer/Event Counters 1 And 2 Square-Wave Output Ranges

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0...

  • Page 218: 16-Bit Timer/Event Counter Mode

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interval Time MCS = 1 MCS = 0...
  • Page 219 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Pulse Width MCS = 1...

  • Page 220: 8-Bit Timer/Event Counters 1 And 2 Configurations

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations Item Timer register Register Timer output Control register...

  • Page 221: Bit Timer/Event Counters 1 And 2 Block Diagram

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram 8-Bit Compare Register (CR10) Match /2-f 8-Bit Timer Register 1 (TM1) TI1/P33 Selector /2-f TI2/P34 Timer Clock Select Register 1 Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counters 1 and 2 output control circuits 1 and 2, respectively.

  • Page 222: Block Diagram Of 8-Bit Timer/Event Counter Output Control Circuit 1

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 LVR1 LVS1 TOC11 INTTM1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 LVR2 LVS2 TOC15...

  • Page 223: 8-Bit Timer/Event Counters 1 And 2 Control Registers

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively).

  • Page 224: Timer Clock Select Register 1 Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-4. Timer Clock Select Register 1 Format Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 8-Bit Timer Register 1 Count Clock Selection TCL13 TCL12 TCL11 TCL10 TI1 falling edge TI1 rising edge Other than above Setting prohibited...

  • Page 225: Bit Timer Mode Control Register 1 Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H.

  • Page 226: Bit Timer Output Control Register Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2.

  • Page 227: Port Mode Register 3 Format

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0.

  • Page 228: 8-Bit Timer/Event Counters 1 And 2 Operations

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).

  • Page 229: Bit Timer/Event Counter 1 Interval Time

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 TI1 input cycle TI1 input cycle (400 ns) (800 ns) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s)

  • Page 230: Bit Timer/Event Counter 2 Interval Time

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time TCL17 TCL16 TCL15 TCL14 MCS = 1 TI2 input cycle TI2 input cycle (400 ns) (800 ns) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s)

  • Page 231: External Event Counter Operation Timings (With Rising Edge Specified)

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input.

  • Page 232: Bit Timer/Event Counters 1 And 2 Square-Wave Output Ranges

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare register 10 and 20 (CR10, CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1.

  • Page 233: Square-Wave Output Operation Timing

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-10. Square-Wave Output Operation Timing Count Clock TM1 Count Value CR10 INTTM1 TO1 Pin Output Note Note The initial value of TO1 pin output can be set with the bits 2 and 3 (LVR1, LVS1) of 8-bit timer output control register (TOC1).

  • Page 234: Interval Timer Operation Timing

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is set with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1), and the overflow signal of 8-bit timer register 1 (TM1) becomes the count clock of 8-bit timer register 2 (TM2).

  • Page 235: Interval Times When 2-Channel 8-Bit Timer/ Event Counters (Tm1 And Tm2) Are Used As 16-Bit Timer/Event Counter

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 TI1 input cycle TI1 input cycle (400 ns) (800 ns) (1.6 s)

  • Page 236: External Event Counter Operation Timings (With Rising Edge Specified)

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2- channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input.

  • Page 237: Square-Wave Output Ranges When 2-Channel 8-Bit Timer/ Event Counters (Tm1 And Tm2 Are Used As 16-Bit Timer/Event Counter

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10, CR20). When setting the count value, set the value of higher 8 bits to CR20 and the value of lower 8 bits to CR10.

  • Page 238: Cautions On 8-Bit Timer/Event Counters 1 And 2

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-13. Square-Wave Output Operation Timing Count Clock TM1, TM2 Count Value 0000 0001 CR10, CR20 INTTM2 TO2 Pin Output Note Note The initial value of TO2 pin output can be set with the bits 6 and 7 (LVR2, LVS2) of 8-bit timer output control register (TOC1).

  • Page 239: Event Counter Operation Timing

    CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit compare register 10 and 20 setting The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H. Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out.
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  • Page 241: Chapter 10 Watch Timer

    10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.

  • Page 242: Watch Timer Configuration

    10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Counter Control register 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer. • Timer clock select register 2 (TCL2) •...

  • Page 243: Watch Timer Block Diagram

    Figure 10-1. Watch Timer Block Diagram TMC21 Clear Prescaler TCL24 Timer Clock Select Register 2 CHAPTER 10 WATCH TIMER 5-Bit Counter Clear TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch Timer Mode Control Register Internal Bus INTWT INTTM3 To 16-Bit Timer/ Event Counter...

  • Page 244: Timer Clock Select Register 2 Format

    Figure 10-2. Timer Clock Select Register 2 Format Symbol TCL2 TCL27 TCL26 TCL25 TCL24 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection TCL24 MCS = 1 (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand.

  • Page 245: Watch Timer Mode Control Register Format

    (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 246: Watch Timer Operations

    10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1.

  • Page 247: Chapter 11 Watchdog Timer

    CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop (runaway) is detected.

  • Page 248: Interval Times

    (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Interval Time Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. MCS : Oscillation mode selection register bit 0 4.

  • Page 249: Watchdog Timer Configuration

    11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Control register Figure 11-1. Watchdog Timer Block Diagram Prescaler TCL22 TCL21 TCL20 Timer Clock Select Register 2 CHAPTER 11 WATCHDOG TIMER Configuration Timer clock select register 2 (TCL2) Watchdog timer mode control register (WDTM) Internal Bus...

  • Page 250: Watchdog Timer Control Registers

    11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction.

  • Page 251: Timer Clock Select Register 2 Format

    Figure 11-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection TCL24 MCS = 1 (39.1 kHz) (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand.

  • Page 252: Watchdog Timer Mode Register Format

    (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register Format <7>...

  • Page 253: Watchdog Timer Operations

    11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).

  • Page 254: Interval Timer Operation

    11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 through 2 (TCL20 through TCL22) of the timer clock select register 2 (TCL2).

  • Page 255: Chapter 12 Clock Output Control Circuit

    CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin.

  • Page 256: Clock Output Control Circuit Configuration

    CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Control register Figure 12-2. Clock Output Control Circuit Block Diagram CLOE TCL03 TCL02 TCL01 TCL00 Timer Clock Select Register 0 Configuration...

  • Page 257: Clock Output Function Control Registers

    CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock.

  • Page 258: Timer Clock Select Register 0 Format

    CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format <7> Symbol CLOE TCL06 TCL05 TCL04 TCL03 TCL0 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 Other than above Setting prohibited 16-Bit Timer Register Count Clock Selection TCL06 TCL05 TCL04 TI00 (Valid edge specifiable) Watch Timer Output (INTTM3)

  • Page 259: Port Mode Register 3 Format

    CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
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  • Page 261: Chapter 13 Buzzer Output Control Circuit

    CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.

  • Page 262: Buzzer Output Function Control Registers

    CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.

  • Page 263: Timer Clock Select Register 2 Format

    CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection TCL24 MCS = 1 (39.1 kHz) (32.768 kHz) Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable...

  • Page 264: Port Mode Register 3 Format

    CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.

  • Page 265: Chapter 14 A/D Converter

    14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).

  • Page 266: A/D Converter Block Diagram

    Figure 14-1. A/D Converter Block Diagram Internal Bus A / D Converter Input Select Register ADIS3 ADIS2 ADIS1 ADIS0 ANI0/P10 ANI1/P11 ANI2/P12 Note 1 Note 2 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 ADM1-ADM3 Edge INTP3/P03 Detector ES40, ES41 Note 3 Trigger Enable TRG FR1 FR0 ADM3 ADM2 ADM1 A /D Converter Mode Register Notes 1.
  • Page 267 (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR).
  • Page 268 (7) AV REF0 This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV and AV The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AV pin to AV level in standby mode.

  • Page 269: A/D Converter Control Registers

    14.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger.

  • Page 270: A/D Converter Mode Register Format

    Figure 14-3. A/D Converter Mode Register Format <7> <6> Symbol ADM3 ADM3 ADM2 ADM1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Time Selection = 5.0 MHz Operation MCS = 1 80/f Setting prohibited 40/f Setting prohibited 50/f...

  • Page 271: A/D Converter Input Select Register Format

    (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H.

  • Page 272: External Interrupt Mode Register 1 Format

    (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-5. External Interrupt Mode Register 1 Format Symbol ES71 ES70...

  • Page 273: A/D Converter Operations

    14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).

  • Page 274: A/D Converter Basic Operation

    Figure 14-6. A/D Converter Basic Operation Sampling Time A/D Converter Sampling Operation Undefined ADCR INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning.

  • Page 275: Input Voltage And Conversion Results

    14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( 256 + 0.5) REF0...

  • Page 276: A/D Converter Operating Mode

    14.4.3 A/D converter operating mode Select one analog input channel from ANI0 to ANI7 with A/D converter input select register (ADIS) and A/D converter mode register (ADM), and start A/D conversion. The following two ways are available to start A/D conversion. •...

  • Page 277: A/D Conversion By Software Start

    (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.

  • Page 278: A/D Converter Cautions

    14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV be cut in order to minimize the overall system power dissipation.

  • Page 279: Analog Input Pin Disposition

    (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-11 in order to reduce noise. Figure 14-11.

  • Page 280: A/D Conversion End Interrupt Request Generation Timing

    (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. If an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may have been set immediately before the ADM rewrite.

  • Page 281: Chapter 15 D/A Converter

    15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the A/D conversion by setting the DACE0 and DACE1 of the D/A converter mode register (DAM). There are two types of modes for the D/A converter, as follows.

  • Page 282: D/A Converter Configuration

    15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Register Control register Figure 15-1. D/A Converter Block Diagram DACS1 Write INTTM2 DACS0 Write INTTM1 REF1 DAM5 DAM4 DACE1 DACE0 D/A Converter Mode Register Internal Bus CHAPTER 15 D/A CONVERTER Configuration...
  • Page 283 (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the values to determine analog voltage output to the ANO0 and ANO1 pins, respectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets these registers to 00H.

  • Page 284: D/A Converter Control Registers

    15.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 15-2.

  • Page 285: Operations Of D/A Converter

    15.4 Operations of D/A Converter (1) Select the channel 0 operating mode and channel 1 operating mode by DAM4 and DAM5 of D/A converter mode register (DAM), respectively. (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to the D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively.

  • Page 286: Cautions Related To D/A Converter

    15.5 Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins.

  • Page 287: Chapter 16 Serial Interface Channel 0 ( Pd78054 Subseries)

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) The PD78054 subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.

  • Page 288: Serial Interface Channel 0 Functions

    This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). The SBI mode conforms to the NEC serial bus format and transmits/receives transfer data discriminating it as three types: “address”, “command”, and “data”.

  • Page 289: Serial Bus Interface (Sbi) System Configuration Example

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level.

  • Page 290: Serial Interface Channel 0 Configuration

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2. Serial Interface Channel 0 Configuration Item Register Control register Note Refer to Figure 6-5. Block Diagram of P20, P21, P23 to P26 and Figure 6-6. Block Diagram of P22, P27. Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA)

  • Page 291: Serial Interface Channel 0 Block Diagram

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Figure 16-2. Serial Interface Channel 0 Block Diagram Serial Operating Mode Register 0 CSIM CSIE0 COI WUP Control Circuit SI0/SB0/ PM25 Output Latch Output Control SO0/SB1/ PM26 Output Control P26 Output Latch SCK0/ PM27 Output...
  • Page 292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
  • Page 293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled also by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.

  • Page 294: Serial Interface Channel 0 Control Registers

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...

  • Page 295: Timer Clock Select Register 3 Format

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Figure 16-3. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34...

  • Page 296: Serial Operating Mode Register 0 Format

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
  • Page 297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Figure 16-4. Serial Operating Mode Register 0 Format (2/2) Wake-up Function Control Note 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode Slave Address Comparison Result Flag Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data...

  • Page 298: Serial Bus Interface Control Register Format

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5.
  • Page 299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Figure 16-5. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable (output with ACKT enable) Acknowledge signal is output in synchronization with the 9th clock Before completion of transfer falling edge of SCK0 (automatically output when ACKE = 1).

  • Page 300: Interrupt Timing Specify Register Format

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.

  • Page 301: Serial Interface Channel 0 Operations

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode •...

  • Page 302: 3-Wire Serial I/O Mode Operation

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
  • Page 303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Symbol <7> <6> <5> CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM...
  • Page 304 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.

  • Page 305: Wire Serial I/O Mode Timings

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.

  • Page 306: Circuit Of Switching In Transfer Bit Order

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 307: Sbi Mode Operation

    16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function.
  • Page 308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available.

  • Page 309: Sbi Transfer Timings

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address, command, and data transfer timings.

  • Page 310: Bus Release Signal

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device.

  • Page 311: Addresses

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses SCK0 SB0 (SB1) Bus Release...

  • Page 312: Commands

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. SCK0 SB0 (SB1) Command Signal SCK0 SB0 (SB1) 8-bit data following a command signal is defined as “command” data. 8-bit data without command signal is defined as “data”.

  • Page 313: Acknowledge Signal

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 SB0 (SB1) [When output in synchronization with 9th clock SCK0] SCK0...

  • Page 314: Busy And Ready Signals

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device that the slave device is ready for data transmission/reception.
  • Page 315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 316 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode. Symbol <7>...
  • Page 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) ACKD Acknowledge Detection Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution. • When CSIE0 = 0 • When RESET input is applied Note BSYE Synchronizing Busy Signal Output Control...
  • Page 318 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> SINT SIC SVAM Notes 1. Bit 6 (CLD) is a read-only bit. 2.

  • Page 319: Relt, Cmdt, Reld, And Cmdd Operations (Master)

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) SIO0 SCK0 SB0 (SB1)

  • Page 320: Ackt Operation

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Figure 16-22. ACKT Operation SCK0 ACK signal is output for SB0 (SB1) a period of one clock just after setting ACKT When set during this period Caution Do not set ACKT before termination of transfer.

  • Page 321: Acke Operations

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 SB0 (SB1) ACKE (b) When set after completion of transfer SCK0 SB0 (SB1) ACKE (c) When ACKE = 0 upon completion of transfer SCK0 SB0 (SB1) ACKE...

  • Page 322: Ackd Operations

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (a) When ACK signal is output at 9th clock of SCK0 SIO0 SCK0 SB0 (SB1) ACKD (b) When ACK signal is output after 9th clock of SCK0 SIO0 SCK0 SB0 (SB1) ACKD (c) Clear timing when transfer start is instructed in BUSY SIO0...

  • Page 323: Various Signals In Sbi Mode

    Output Signal Name Definition Device Bus release SB0 (SB1) rising edge Master signal when SCK0 = 1 (REL) Command SB0 (SB1) falling edge signal Master when SCK0 = 1 (CMD) Low-level signal to be output to SB0 (SB1) during Acknowledge Master/ one-clock period of SCK0 signal...
  • Page 324 Output Signal Name Definition Device Synchronous clock to output address/command/ data, ACK signal, Serial clock synchronous BUSY signal, Master (SCK0) etc. Address/command/ data are transferred with the first eight synchronous clocks. 8-bit data to be transferred in synchronization with Address Master SCK0 after output of REL (A7 to A0)

  • Page 325: Pin Configuration

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ... Serial clock input/output pin <1> Master ... CMOS and push-pull output <2>...
  • Page 326 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master coincides with the address set to SVA when the wake-up function specify bit (WUP) = 1.

  • Page 327: Address Transmission From Master Device To Slave Device (Wup = 1)

    Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) CMDT RELT CMDT Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing CMDD CMDD CMDD Hardware Operation Clear RELD...

  • Page 328: Command Transmission From Master Device To Slave Device

    Figure 16-28. Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter) CMDT Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing CMDD Hardware Operation Write to SIO0 Serial Transmission Command Serial Reception Interrupt Servicing...

  • Page 329: Data Transmission From Master Device To Slave Device

    Figure 16-29. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing Hardware Operation Write to SIO0 Serial Transmission Data Serial Reception Interrupt Servicing (Preparation for the Next Serial Transfer) INTCSI0...

  • Page 330: Data Transmission From Slave Device To Master Device

    Figure 16-30. Data Transmission from Slave Device to Master Device Master Device Processing (Receiver) Program Processing SCK0 Hardware Operation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY Slave Device processing (Transmitter) Write Program Processing to SIO0 BUSY Hardware Operation Clear FFH Write to SIO0...
  • Page 331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...
  • Page 332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (10) Discrimination of slave busy state When device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation. <2>...

  • Page 333: 2-Wire Serial I/O Mode Operation

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
  • Page 334 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
  • Page 336 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> SINT SVAM Notes 1. Bit 6 (CLD) is a read-only bit. 2.

  • Page 337: Wire Serial I/O Mode Timings

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).

  • Page 338: Relt And Cmdt Operations

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.

  • Page 339: Sck0/P27 Pin Output Manipulation

    CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register (SBIC).) SCK0/P27 pin output manipulating procedure is described below.
  • Page 340 [MEMO]...

  • Page 341: Chapter 17 Serial Interface Channel 0 ( Pd78054Y Subseries)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) The PD78054Y subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.

  • Page 342: Serial Interface Channel 0 Functions

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I C (Inter IC) bus mode Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, I operation of serial interface channel 0 is enabled.
  • Page 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (4) I C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I data onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received.

  • Page 344: Serial Interface Channel 0 Configuration

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Register Control register Note Refer to Figure 6-7. Block Diagram of P20, P21, P23 to P26 and Figure 6-8. Block Diagram of P22, P27.

  • Page 345: Serial Interface Channel 0 Block Diagram

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-2. Serial Interface Channel 0 Block Diagram Serial Operating Mode Register 0 CSIM CSIE0 COI WUP BSYE Control Circuit SI0/SB0/ SDA0/P25 PM25 Output Latch Output Control SO0/SB1/ SDA1/P26 PM26 Output Control P26 Output Latch SCK0/...
  • Page 346 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.

  • Page 347: Serial Interface Channel 0 Interrupt Request Signal Generation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 17-3.

  • Page 348: Serial Interface Channel 0 Control Registers

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...

  • Page 349: Timer Clock Select Register 3 Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-3. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 Serial Clock in I Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection...
  • Page 350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.

  • Page 351: Serial Operating Mode Register 0 Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-4. Serial Operating Mode Register 0 Format Symbol <7> <6> <5> CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 Input Clock to SCK0/SCL pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM...

  • Page 352: Serial Bus Interface Control Register Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5.
  • Page 353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-5. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge Signal Output Control Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Used for reception when 8-clock wait mode is selected or for transmission. Enables acknowledge signal automatic output.

  • Page 354: Interrupt Timing Specify Register Format

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
  • Page 355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-6. Interrupt Timing Specify Register Format (2/2) SVAM SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 INTCSI0 Interrupt Cause Selection CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer Note 2 SCK0/SCL Pin Level...

  • Page 356: Serial Interface Channel 0 Operations

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •...

  • Page 357: 3-Wire Serial I/O Mode Operation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
  • Page 358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.

  • Page 359: Wire Serial I/O Mode Timings

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.

  • Page 360: Circuit Of Switching In Transfer Bit Order

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 361: 2-Wire Serial I/O Mode Operation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
  • Page 362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Symbol <7> <6> <5> CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01...
  • Page 363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
  • Page 364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> <3> SINT SVAM CLC WREL WAT1 WAT0 INTCSI0 Interrupt Factor Selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer...

  • Page 365: Wire Serial I/O Mode Timings

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).

  • Page 366: Relt And Cmdt Operations

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.

  • Page 367: I 2 C Bus Mode Operation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.4.4 I C bus mode operation The I C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line.
  • Page 368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (1) I C bus mode functions In the I C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.

  • Page 369: Start Condition

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer.

  • Page 370: Stop Condition

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer. In principle, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data.

  • Page 371: Wait Signal

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers.
  • Page 372 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (3) Register setting The I C mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT Use for stop condition output.
  • Page 374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) ACKE Acknowledge Signal Automatic Output Control Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting Note 2 data. Enabled. After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of SCL clock (automatically output when ACKE = 1).
  • Page 375 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> <3> SINT SVAM CLC WREL WAT1 WAT0 WAT1 WAT0 Interrupt control by wait (See...
  • Page 376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (4) Various signals A list of signals in the I C bus mode is given in Table 17-4. Table 17-4. Signals in I Signal name Description Start condition Definition : Function : Signaled by : Signaled when : Affected flag(s) : CMDD (is set.)

  • Page 377: Pin Configuration

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1>...
  • Page 378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (7) Error detection In the I C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device.

  • Page 379: Data Transmission From Master To Slave (Both Master And Slave Selected 9-Clock Wait)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Address Master device operation SIO0 Address Write SIO0 ACKD CMDD RELD BSYE...
  • Page 380 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (2 of 3) Master device operation SIO0 Address Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0...
  • Page 381 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (3 of 3) Master device operation SIO0 Data Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0...
  • Page 382 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1 of 3) Master device operation SIO0 Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer line...

  • Page 383: Data Transmission From Slave To Master (Both Master And Slave Selected 9-Clock Wait)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (2 of 3) Master device operation SIO0 Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer line...
  • Page 384 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (3 of 3) Master device operation SIO0 Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer line...

  • Page 385: Cautions On Use Of I C Bus Mode

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.4.5 Cautions on use of I C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal.

  • Page 386: Slave Wait Release (Transmission)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.

  • Page 387: Slave Wait Release (Reception)

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register (SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed. When the slave receives data, the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high-impedance state after an instruction that writes data to SIO has been executed.

  • Page 388: Restrictions In I 2 C Bus Mode

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1). This is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore, the wake-up condition cannot be used when the slave receives the undefined number of data from the master.
  • Page 389 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.7; <7> CLR1 P2.5; <8>...

  • Page 390: Sck0/Scl/P27 Pin Output Manipulation

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)).

  • Page 391: Logic Circuit Of Scl Signal

    CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries) Figure 17-29. Logic Circuit of SCL Signal CLC (manipulated by bit manipulation instruction) Wait request signal Serial clock (low while transfer is stopped) Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit. 2.
  • Page 392 [MEMO]...

  • Page 393: Chapter 18 Serial Interface Channel 1

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.

  • Page 394: Serial Interface Channel 1 Configuration

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1. Serial Interface Channel 1 Configuration Item Register Control register Note Refer to Figure 6-5, 6-7 Block Diagram of P20, P21, P23 to P26 and Figure 6-6, 6-8 Block Diagram of P22, P27.

  • Page 395: Serial Interface Channel 1 Block Diagram

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/Receive Buffer RAM Address Pointer (ADTP) ADTI Serial I/O SI1/ Shift Register 1 (SIO1) PM21 SO1/ P21 Output Latch PM23 STB/ Hand- shake BUSY/ SCK1/...
  • Page 396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.

  • Page 397: Serial Interface Channel 1 Control Registers

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) •...

  • Page 398: Timer Clock Select Register 3 Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 Other than above Setting prohibited Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand.

  • Page 399: Serial Operation Mode Register 1 Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.

  • Page 400: Automatic Data Transmit/Receive Control Register Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic transmit/receive enable/disable, the operating mode, strobe output enable/ disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 401: Automatic Data Transmit/Receive Interval Specify Register Format

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 18-5.
  • Page 402 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
  • Page 403 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 Data Transfer Interval Control No control of interval by ADTI Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Notes 1.
  • Page 404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).

  • Page 405: Serial Interface Channel 1 Operations

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.

  • Page 406: 3-Wire Serial I/O Mode Operation

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1).

  • Page 407: Wire Serial I/O Mode Timings

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1. The transmit data is held in the SO1 latch and is output from the SO1 pin.

  • Page 408: Circuit Of Switching In Transfer Bit Order

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-7 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 409: 3-Wire Serial I/O Mode Operation With Automatic Transmit/Receive Function

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
  • Page 410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol <7> <5> CSIM1 CSIE1 DIR Serial Interface Channel 1 Clock Selection CSIM11 CSIM10 Clock externally input to SCK1 pin 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3) Serial Interface Channel 1 Operating Mode Selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function...
  • Page 411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Symbol <7> <6> <5> <4> <3> ADTC ARLD ERCE ERR TRF STRB Notes 1.
  • Page 412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0...
  • Page 413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f is 2/f Minimum = (n+1)
  • Page 414 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 Data Transfer Interval Control No control of interval by ADTI Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Notes 1. The interval is dependent only on CPU processing. 2.
  • Page 415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f is 2/f Minimum = (n+1)
  • Page 416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address. <2>...

  • Page 417: Basic Transmission/Reception Mode Operation Timings

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.

  • Page 418: Basic Transmission/Reception Mode Flowchart

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
  • Page 419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD=0, RE=1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (Refer to Figure 18-10 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 420 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) FADFH FAC5H Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) (c) Completion of transmission/reception...

  • Page 421: Basic Transmission Mode Operation Timings

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.

  • Page 422: Basic Transmission Mode Flowchart

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
  • Page 423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-13 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 424 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-13. Buffer RAM Operation in 6-Byte Transmission FADFH FAC5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) FADFH FAC5H Transmit data 1 (T1)

  • Page 425: Repeat Transmission Mode Operation Timing

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1).

  • Page 426: Repeat Transmission Mode Flowchart

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
  • Page 427 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=1, RE=0) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-16 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16. Buffer RAM Operation in 6-Byte Transmission (b) Upon completion of transmission of 6 bytes FADFH FAC5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6)

  • Page 429: Automatic Transmission/Reception Suspension And Restart

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0. It is suspended upon completion of 8-bit data transfer.

  • Page 430: System Configuration When The Busy Control Option Is Used

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization Control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Busy control Option Busy control is a function which causes the master device’s serial transmission to wait when the slave device outputs a busy signal to the master device, and maintain the wait state while that busy signal is...

  • Page 431: Operation Timings When Using Busy Control Option (Busy0 = 0)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19. Caution Busy control cannot be used at the same time as interval timing control using the auto data send and receive interval instruction register (ADTI).

  • Page 432: Busy Signal And Wait Cancel (When Busy0 = 0)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20. Busy Signal and Wait Cancel (when BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY In the case where the busy (Active High) signal becomes inactive directly when sampled...

  • Page 433: Operation Timings When Using Busy & Strobe Control Option (Busy0 = 0)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) SCK1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY CSIIF1 Caution When TRF is cleared, the SO1 pin becomes low level. Remarks CSIIF1: Interrupt request flag : Bit 3 of the auto data send and receive control register (ADTC) D7 D6 D5 D4 D3 D2 D1 D0...
  • Page 434 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control option is not used, this bit slippage will have an effect on sending of the next byte.

  • Page 435: Automatic Data Transmit/Receive Interval

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in the automatic transmit/receive interval specification register (ADTI) and the CPU processing at the...

  • Page 436: Operation Timing With Automatic Data Transmit/Receive Function Performed By Internal Clock

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the auto send and receive function is operated by the internal clock, interval timing by CPU processing is as follows.

  • Page 437: Interval Timing Through Cpu Processing (When The External Clock Is Operating)

    CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the external clock, it must be selected so that the interval may be longer than the values shown as follows.
  • Page 438 [MEMO]...

  • Page 439: Chapter 19 Serial Interface Channel 2

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.

  • Page 440: Serial Interface Channel 2 Configuration

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1. Serial Interface Channel 2 Configuration Item Register Control register Note Refer to Figure 6-15 Block Diagram of P70 and Figure 6-16 Block Diagram of P71, P72. Configuration Transmit shift register (TXS) Receive shift register (RXS)

  • Page 441: Serial Interface Channel 2 Block Diagram

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1. Serial Interface Channel 2 Block Diagram Receive Buffer Register (RXB/SIO2) Direction Control Circuit Receive Shift RxD/SI2/ Register (RXS) TxD/SO2/ PM71 Reception Control Circuit PM72 ASCK/ SCK2/P72 Serial Operating Mode Register 2 Note See Figure 19-2 for the baud rate generator configuration.

  • Page 442: Baud Rate Generator Block Diagram

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2. Baud Rate Generator Block Diagram CSIE2 Transmit Clock Receive Clock Start Bit Detection Start Bit Sampling Clock 5-Bit Counter Match MDL0-MDL3 Decoder Match 5-Bit Counter TPS3 TPS2 TPS1 TPS0 Baud Rate Generator Control Register Internal Bus ASCK/SCK2/P72...
  • Page 443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation.

  • Page 444: Serial Interface Channel 2 Control Registers

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) •...

  • Page 445: Asynchronous Serial Interface Mode Register Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.

  • Page 446: Serial Interface Channel 2 Operating Mode Settings

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72 TXE RXE SCK CSIE2 CSIM22 CSCK Other than above (2) 3-wire Serial I/O Mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72...

  • Page 447: Asynchronous Serial Interface Status Register Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined.

  • Page 448: Baud Rate Generator Control Register Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 19-6. Baud Rate Generator Control Register Format (1/2) Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0...
  • Page 449 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution When data is written to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, data must not be written to BRGC during a communication operation.

  • Page 450: Relation Between Main System Clock And Baud Rate

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock.
  • Page 451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = (k+16)

  • Page 452: Serial Interface Channel 2 Operation

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
  • Page 453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol <7> <6> ASIM Address After Reset ISRM SCK FF70H Receive Operation Control Receive operation stopped Receive operation enabled...

  • Page 454: Asynchronous Serial Interface (Uart) Mode

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined also by scaling the input clock to the ASCK pin.
  • Page 455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol <7> <6> ASIM Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port.
  • Page 456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. Symbol ASIS Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
  • Page 457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection Remark : 5-bit counter source clock...
  • Page 458 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution When a data is written to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, data must not be written to BRGC during a communication operation.

  • Page 459: Relation Between Main System Clock And Baud Rate

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock.

  • Page 460: Relation Between Asck Pin Input Frequency And Baud Rate (When Brgc Is Set To 00H)

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = (k+16)

  • Page 461: Asynchronous Serial Interface Transmit/Receive Data Format

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format Start One data frame consists of the following bits. • Start bits ... 1 bit •...
  • Page 462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.

  • Page 463: Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated.
  • Page 464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When the bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. When the RxD pin input becomes low, the 5-bit counter of the baud rate generator (refer to Figure 19- 2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output.

  • Page 465: Receive Error Timing

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. When the data reception result error flag is set in the asynchronous serial interface status register (ASIS), a receive error interrupt request (INTSER) is generated.
  • Page 466 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared and the transmission operation is stopped during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1 before executing the next transmission.

  • Page 467: 3-Wire Serial I/O Mode

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
  • Page 468 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. Symbol <7>...
  • Page 469 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection Remark : 5-bit counter source clock...
  • Page 470 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution When a Data is written to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, data must not be written to BRGC during a communication operation.
  • Page 471 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the 3-wire serial I/O mode is used, set BRGC as described below. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1. The serial clock frequency becomes 1/2 of the source clock frequency for the 5-bit counter.

  • Page 472: Wire Serial I/O Mode Timing

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2.

  • Page 473: Circuit Of Switching In Transfer Bit Order

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 474: Limitations When Uart Mode Is Used

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Limitations when UART mode is used In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception error interrupt request (INTSER) has occurred and then cleared. Consequently, the following phenomenon may occur. •...

  • Page 475: Receive Buffer Register Read Disable Period

    CHAPTER 19 SERIAL INTERFACE CHANNEL 2 • In case of parity error Disable the receive buffer register (RXB) from being read for a certain time (T1 + T2 in Figure 19-15) after the reception error interrupt request (INTSER) has occurred. Figure 19-15.
  • Page 476 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] Occurrence of INTSER 7 clocks of CPU clock (MIN.) (time from interrupt request to servicing) UART reception error interrupt (INTSER) servicing Main processing Instructions equivalent to 2205 CPU clocks (MIN.) are necessary. MOV A, RXB RETI...

  • Page 477: Chapter 20 Real-Time Output Port

    CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt requests or external interrupt request generation, then output externally. This is called the real-time output function.

  • Page 478: Real-Time Output Port Block Diagram

    20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Register Control register Figure 20-1. Real-time Output Port Block Diagram Real-time Output Port Control Register EXTR BYTE INTP2 Output Trigger INTTM1 Control Circuit INTTM2...

  • Page 479: Real-Time Output Buffer Register Configuration

    CHAPTER 20 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits 1 channel as the operating mode, data are set to both RTBL and RTBH by writing 8-bit data to either RTBL or RTBH.

  • Page 480: Real-Time Output Port Control Registers

    CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of port 12 pins (P120 through P127) which are multiplexed with real-time output pins (RTP0 through RTP7).

  • Page 481: Real-Time Output Port Control Register Format

    CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 482 CHAPTER 20 REAL-TIME OUTPUT PORT [MEMO]...

  • Page 483: Chapter 21 Interrupt And Test Functions

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.

  • Page 484: Interrupt Sources And Configuration

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration Interrupt sources includes total of 22 non-maskbale, maskable, software interrupts (refer to Table 21-1). Table 21-1. Interrupt Source List (1/2) Note 1 Interrupt Default Type Priority Name Non- – INTWDT maskable INTWDT...
  • Page 485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1. Interrupt Source List (2/2) Note 1 Interrupt Default Type Priority Name Reference time interval signal from Maskable INTTM3 watch timer Generation of 16-bit timer register, INTTM00 capture/compare register (CR00) match signal Generation of 16-bit timer register, INTTM01 capture/compare register (CR01) match signal...

  • Page 486: Basic Configuration Of Interrupt Function

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Interrupt Request (B) Internal maskable interrupt Interrupt Request (C) External maskable interrupt (INTP0) Sampling Clock External Interrupt Mode Select Register Register (INTM0) (SCS) Sampling Edge...
  • Page 487 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) External Interrupt Mode Register (INTM0, INTM1) Interrupt Edge Request Detector (E) Software interrupt Interrupt Request Remark Interrupt request flag Interrupt enable flag ISP : Inservice priority flag MK :...

  • Page 488: Interrupt Function Control Registers

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) •...

  • Page 489: Interrupt Request Flag Register Format

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.

  • Page 490: Interrupt Mask Flag Register Format

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.

  • Page 491: Priority Specify Flag Register Format

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.

  • Page 492: External Interrupt Mode Register 0 Format

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP6. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 21-5.

  • Page 493: External Interrupt Mode Register 1 Format

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-6. External Interrupt Mode Register 1 Format Symbol INTM1 ES71 ES70 ES61 ES60 ES51 After Address Reset ES50 ES41 ES40 FFEDH ES41 ES40 Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 ES50 Falling edge...

  • Page 494: Sampling Clock Select Register Format

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction.

  • Page 495: Noise Eliminator Input/Output Timing (During Rising Edge Detection)

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS When the sampled INTP0 input level is active twice in succession, the noise eliminator sets interrupt request flag (PIF0) to 1. Figure 21-8 shows the noise eliminator input/output timing. Figure 21-8. Noise Eliminator Input/Output Timing (during rising edge detection) (a) When input is less than the sampling cycle (t Sampling Clock INTP0...

  • Page 496: Program Status Word Configuration

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.

  • Page 497: Interrupt Servicing Operations

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupt requests. If a non-maskable interrupt request is acknowledged, the contents of acknowledged interrupt is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.

  • Page 498: Flowchart Of Generation From Non-Maskable Interrupt Request To Acknowledgment

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-10. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment Figure 21-11. Non-Maskable Interrupt Request Acknowledge Timing CPU Instruction Instruction TMIF4 The interrupt request generated during this period is acknowledged at the timing of . Start WDTM4=1 (with watchdog timer...

  • Page 499: Non-Maskable Interrupt Request Acknowledge Operation

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> Request <2> 1 Instruction Execution If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine Request <2>...

  • Page 500: Maskable Interrupt Request Acknowledge Operation

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).

  • Page 501: Interrupt Request Acknowledge Processing Algorithm

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm Interrupt request reserve Any high- priority interrupt request among simultaneously generated PR=0 interrupt requests? Interrupt request reserve IE=1? Interrupt request reserve Vectored interrupt servicing Interrupt request flag Interrupt mask flag Priority specify flag Flag to control acknowledgment of maskable interrupt request (1 = enable, 0 = disable)

  • Page 502: Interrupt Request Acknowledge Timing (Maximum Time)

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) CPU Processing Instruction PR=1) PR=0) Remark 1 clock : Figure 21-15. Interrupt Request Acknowledge Timing (Maximum Time) CPU Processing Instruction PR=1) PR=0) Remark 1 clock : Instruction 8 Clocks : CPU clock)

  • Page 503: Software Interrupt Request Acknowledge Operation

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into PC and branched.

  • Page 504: Multiple Interrupt Example

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (1/2) Example 1. A multiple interrupt is generated at twice Main Processing IE=0 INTxx INTyy (PR=1) (PR=0) While servicing interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and a multiple interrupt is generated.
  • Page 505 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupt is disabled Main Processing INTxx (PR=0) 1 Instruction Execution Because interrupts are disabled during interrupt INTxx servicing (EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated.

  • Page 506: Interrupt Request Reserve

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve In some cases, the acknowledgment of the interrupt request is reserved even an interrupt request is generated during processing of the instruction until the execution of the next instruction is completed. The following shows this type of instructions (interrupt request reserve instruction).

  • Page 507: Test Functions

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.5 Test Functions Upon occurrence of watch timer overflow and the detection of the falling falling edge of port 4, the corresponding test input flag is set (1) and a standby release signal is generated. Unlike in the case of interrupt functions, vector processing is not performed.

  • Page 508: Format Of Interrupt Request Flag Register 1L

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 21-19.

  • Page 509: Test Input Signal Acknowledge Operation

    CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
  • Page 510 [MEMO]...

  • Page 511: Chapter 22 External Device Expansion Function

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe etc.

  • Page 512: Memory Map When Using External Device Expansion Function

    Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map when Using External Device Expansion Function (1/4) (a) Memory map of PD78P054, 78P058, 78P058Y when the PD78052, 78052Y and internal PROM are 16 Kbytes FFFFH...
  • Page 513 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (2/4) (c) Memory map of PD78P054, 78P058, 78P058Y when the PD78054, 78054Y and internal PROM are 32 Kbytes FFFFH FF00H FEFFH Internal High-Speed RAM FB00H FAFFH Reserved...
  • Page 514 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (3/4) (e) Memory map of PD78P058, 78P058Y FFFFH FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH FA80H FA7FH D000H CFFFH C100H C0FFH C000H BFFFH 0000H when the PD78056, 78056Y and internal PROM are 48 Kbytes...
  • Page 515 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (4/4) PD78058, 78058Y, 78P058, 78P058Y Memory map when internal ROM (PROM) size is 56 Kbytes FFFFH FF00H FEFFH Internal High-Speed RAM FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM...

  • Page 516: External Device Expansion Function Control Register

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output of port 4. MM is set with an 1-bit memory or 8-bit memory manipulation instruction.

  • Page 517: Memory Size Switching Register Format

    RAM0 ROM3 Note The values after reset depend on the product. (See Table 22-3) Table 22-3. Values when the Memory Size Switching Register is Reset Part number PD78052, 78052Y PD78053, 78053Y PD78054, 78054Y PD78055, 78055Y PD78056, 78056Y PD78058, 78058Y After...

  • Page 518: External Device Expansion Function Timing

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory.

  • Page 519: Instruction Fetch From External Memory

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0-AD7 Lower Address Operation Code A8-A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0-AD7 Lower Address Operation Code...

  • Page 520: External Memory Read Timing

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5. External Memory Read Timing ASTB AD0-AD7 A8-A15 ASTB AD0-AD7 A8-A15 Internal Wait Signal (1-clock wait) (c) External wait (PW1, PW0 = 1, 1) setting ASTB AD0-AD7 A8-A15 WAIT (a) No wait (PW1, PW0 = 0, 0) setting Lower Address Read Data Higher Address...

  • Page 521: External Memory Write Timing

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z AD0-AD7 Lower Address Write Data Higher Address A8-A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower Address Write Data...

  • Page 522: External Memory Read Modify Write Timing

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower Address Read Data Write Data AD0-AD7 A8-A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Read Data...

  • Page 523: Example Of Connection With Memory

    CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.4 Example of Connection with Memory This section provides PD78054 and external memory connection examples in Figure 22-8. SRAMs are used as the external memory in these diagrams. In addition, the external device expansion function is used in the full-address mode, and the address from 0000H to 7FFFH (32 Kbytes) are allocated for internal ROM, and the addresses after 8000H for SRAM.
  • Page 524 [MEMO]...

  • Page 525: Chapter 23 Standby Function

    CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation.

  • Page 526: Standby Function Control Register

    23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.

  • Page 527: Standby Function Operations

    23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 23-1.

  • Page 528: Halt Mode Clear Upon Interrupt Request Generation

    (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is cleared. If interrupt request acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed.

  • Page 529: Halt Mode Release By Reset Input

    CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input When a RESET signal is input, the HALT mode is released, and as is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 23-3.

  • Page 530: Stop Mode

    23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V to minimize the leakage current at the crystal oscillator.

  • Page 531: Stop Mode Release By Interrupt Request Generation

    CHAPTER 23 STANDBY FUNCTION (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is cleared. If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.

  • Page 532: Release By Stop Mode Reset Input

    (c) Release by RESET input When a RESET signal is input, the STOP mode is released. And after the lapse of oscillation stabilization time, reset operation is carried out. Figure 23-5. Release by STOP Mode RESET Input STOP Instruction RESET Signal Operating Mode...

  • Page 533: Chapter 24 Reset Function

    CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.

  • Page 534: Timing Of Reset Input By Reset Input

    Figure 24-2. Timing of Reset Input by RESET Input Normal Operation RESET Internal Reset Signal Port Pin Figure 24-3. Timing of Reset due to Watchdog Timer Overflow Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Figure 24-4. Timing of Reset Input in STOP Mode by RESET Input STOP Instruction Execution Normal Operation RESET...

  • Page 535: Hardware Status After Reset

    2. When reset in the standby mode, the state before reset is held even after reset. 3. The values after reset depend on the product. PD78052, 78052Y : 44H, PD78053, 78053Y : C6H, PD78054, 78054Y : C8H, PD78P054 : C8H, PD78055, 78055Y : CAH, PD78056, 78056Y : CCH, PD78058, 78058Y : CFH, PD78P058, 78P058Y: CFH 4.
  • Page 536 Table 24-1. Hardware Status after Reset (2/2) Hardware Watch timer Mode control register (TMC2) Clock select register (TCL2) Watchdog timer Mode register (WDTM) Serial interface Clock select register (TCL3) Shift registers (SIO0, SIO1) Mode registers (CSIM0, CSIM1, CSIM2) Serial bus interface control register (SBIC) Slave address register (SVA) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive address pointer (ADTP)

  • Page 537: Chapter 25 Rom Correction

    CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The PD78058, 78058Y subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction.

  • Page 538: Correction Address Registers 0 And 1 Format

    (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1.

  • Page 539: Rom Correction Control Registers

    25.3 ROM Correction Control Registers The ROM correction is controlled with the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1).

  • Page 540: Rom Correction Application

    25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to CORAD0 or CORAD1 generates the correction branch.

  • Page 541: Initialization Routine

    CHAPTER 25 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program. Figure 25-6. Initialization Routine ROM correction Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Note Whether the ROM correction is used or not should be judged by the port input level.

  • Page 542: Rom Correction Operation

    CHAPTER 25 ROM CORRECTION Figure 25-7. ROM Correction Operation Internal ROM program start Does fetch address match with correction address? ROM correction Set correction status flag Correction branch (branch to address F7FDH) Correction program execution...

  • Page 543: Rom Correction Example

    25.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 25-8. ROM Correction Example Internal ROM 0000H 0080H Program start ADD A, #1 1000H MOV B, A 1002H...

  • Page 544: Program Execution Flow

    25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used. Figure 25-9. Program Transition Diagram (when one place is corrected) FFFFH F7FFH F7FDH JUMP xxxxH 0000H (1) Branches to address F7FDH when fetch address matches correction address (2) Branches to correction program (3) Returns to internal ROM program Remark Area filled with diagonal lines : Internal expansion RAM...

  • Page 545: Program Transition Diagram (When Two Places Are Corrected)

    CHAPTER 25 ROM CORRECTION Figure 25-10. Program Transition Diagram (when two places are corrected) FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Correction program 1 xxxxH Destination judge program JUMP Internal ROM Correction place 2 Internal ROM Correction place 1 Internal ROM 0000H (1) Branches to address F7FDH when fetch address matches correction address...

  • Page 546: Cautions On Rom Correction

    25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch is in disabled state).

  • Page 547: Pd78P054, 78P058

    The PD78054, 78054Y subseries include the PD78P054, 78P058, 78P058Y as PROM versions. For purposes of simplification, in this chapter, the description of the PD78P058 applies to both the PD78P058 and 78P058Y. Similarly, the PD78052, 78053, 78054, 78055, 78056, and 78058 are treated as the representative models of the mask ROM products.

  • Page 548: Differences Between Pd78P054 And 78P058

    CS products (not ES products) of the mask ROM versions. Remarks 1. The PD78P054 is a PROM model corresponding to the PD78052, 78053, and 78054. The PD78P058 is a PROM model corresponding to the PD78055, 78056, and 78058.

  • Page 549: Memory Size Switching Register ( Pd78P054)

    ROM2 ROM1 ROM0 ROM3 ROM2 ROM1 Other than above RAM2 RAM1 RAM0 Other than above IMS Setting PD78052 PD78053 PD78054 ROM0 Internal ROM Capacity selection 16 Kbytes 24 Kbytes 32 Kbytes Setting prohibited Internal High-Speed RAM Capacity Selection 512 bytes...

  • Page 550: Memory Size Switching Register ( Pd78P058)

    The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-4. Table 26-4. Examples of Memory Size Switching Register Settings ( PD78P058) Relevant Mask ROM Version PD78052, 78052Y PD78053, 78053Y PD78054, 78054Y PD78055, 78055Y...

  • Page 551: Internal Expansion Ram Size Switching Register

    IXRAM2 IXRAM1 IXRAM0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Other than above Value set to IXS PD78052, 78052Y PD78053, 78053Y PD78054, 78054Y PD78055, 78055Y PD78056, 78056Y PD78058, 78058Y includes “MOV IXS, #0CH” is implemented with the PD78055, 78055Y, 78056, or 78056Y, this instruction is ignored and causes no malfunction.

  • Page 552: Prom Programming

    26.4 PROM Programming The PD78P054 and 78P058 incorporate a 32-Kbyte and 60-Kbyte PROM as program memory, respectively. To write a program into the PD78P054 or 78P058 PROM, make the device enter the PROM programming mode by setting the levels of the V and RESET pins as specified.
  • Page 553 CHAPTER 26 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.

  • Page 554: Prom Write Procedure

    26.4.2 PROM write procedure Figure 26-4. Page Program Mode Flowchart Address = Address + 1 Pass CHAPTER 26 PD78P054, 78P058 Start Address = G = 6.5 V, V = 12.5 V Remark: G = Start address X = 0 N = Last address of program Latch Address = Address + 1 Latch...

  • Page 555: Page Program Mode Timing

    CHAPTER 26 Figure 26-5. Page Program Mode Timing Page Data Latch A2-A16 A0, A1 D0-D7 Data Input +1.5 PD78P054, 78P058 Page Program Program Verify Hi-Z Data Output...

  • Page 556: Byte Program Mode Flowchart

    Figure 26-6. Byte Program Mode Flowchart Address = Address + 1 Pass CHAPTER 26 PD78P054, 78P058 Start Remark: Address = G G = Start address N = Last address of program = 6.5 V, V = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Fail...

  • Page 557: Byte Program Mode Timing

    CHAPTER 26 Figure 26-7. Byte Program Mode Timing A0-A16 D0-D7 Data Input +1.5 Cautions 1. Be sure to apply V before applying V 2. V must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to the V pin may have an adverse affect on device reliability.

  • Page 558: Prom Reading Procedure

    26.4.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V (2) “PROM programming mode” in section 1.5 or 2.5 Pin Configuration (Top View). (2) Supply +5 V to the V and V (3) Input the address of data to be read to pins A0 through A16.

  • Page 559: Erasure Procedure ( Pd78P054Kk-T And 78P058Kk-T Only)

    Storage Temperature For users who do not wish to implement screening by themselves, NEC provides such users with a charged service in which NEC performs a series of processes from writing one-time PROMs and screening them to verifying their contents for users by request. The PROM version devices which provide this service are called QTOP microcontrollers.
  • Page 560 [MEMO]...

  • Page 561: Chapter 27 Instruction Set

    CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the PD78054 and 78054Y subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series User’s Manual, Instruction (U12326E).”...

  • Page 562: Legends Used In Operation List

    27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.

  • Page 563: Description Of "Operation" Column

    27.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter...

  • Page 564: Operation List

    27.2 Operation List Instruction Mnemonic Operands Group r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] 8-bit data [DE], A transfer A, [HL] [HL], A...
  • Page 565 Instruction Mnemonic Operands Group rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX 16-bit MOVW AX, sfrp data sfrp, AX transfer Note 3 AX, rp Note 3 rp, AX AX, !addr16 !addr16, AX Note 3 XCHW AX, rp A, #byte saddr, #byte Note 4 A, r...
  • Page 566 Instruction Mnemonic Operands Group A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A A, saddr 8-bit SUBC operation...
  • Page 567 Instruction Mnemonic Operands Group A, #byte saddr, #byte Note 3 A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte Note 3 A, r r, A A, saddr 8-bit...
  • Page 568 Instruction Mnemonic Operands Group ADDW AX, #word 16-bit SUBW AX, #word operation CMPW AX, #word MULU Multiply/ divide DIVUW saddr Increment/ decrement saddr INCW DECW A, 1 A, 1 RORC A, 1 ROLC A, 1 Rotate ROR4 [HL] ROL4 [HL] ADJBA adjust ADJBS...
  • Page 569 Instruction Mnemonic Operands Group CY, saddr.bit CY, sfr.bit AND1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit XOR1 CY, A.bit manipulate CY, PSW. bit CY, [HL].bit saddr.bit sfr.bit SET1 A.bit PSW.bit...
  • Page 570 Instruction Mnemonic Operands Group CALL !addr16 CALLF !addr11 CALLT [addr5] Call/return RETI RETB PUSH Stack manipulate SP, #word MOVW SP, AX AX, SP !addr16 Uncondi- tional $addr16 branch $addr16 $addr16 Conditional branch $addr16 $addr16 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access. 2.
  • Page 571 Instruction Mnemonic Operands Group saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Conditional saddr.bit, $addr16 branch sfr.bit, $addr16 BTCLR A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 B, $addr16 DBNZ C, $addr16 saddr.

  • Page 572: Instructions Listed By Addressing Type

    27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ CHAPTER 27 INSTRUCTION SET...
  • Page 573 Second Operand Note #byte First Operand MOV MOV MOV MOV MOV MOV MOV MOV ADDC SUBC ADDC SUBC MOV MOV ADDC SUBC B, C MOV MOV saddr MOV MOV ADDC SUBC !addr16 MOV MOV [DE] [HL] [HL + byte] [HL + B] [HL + C] Note Except r = A...
  • Page 574 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word 1st Operand ADDW SUBW CMPW MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand...
  • Page 575 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP CHAPTER 27 INSTRUCTION SET !addr16 !addr11 [addr5]...
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  • Page 577: Appendix A Differences Between Pd78054, 78054Y Subseries And Pd78058F, 78058Fy Subseries

    APPENDIX A DIFFERENCES BETWEEN PD78054, 78054Y SUBSERIES AND PD78058F, 78058FY SUBSERIES Table A-1 shows the major differences between the PD78054, 78054Y Subseries and PD78058F, 78058FY Subseries.

  • Page 578: A-1. Major Differences Between Pd78054, 78054Y Subseries And Pd78058F, 78058Fy Subseries

    None PROM version PD78P054 PD78P058 PD78P058Y Supply voltage Internal ROM capacity PD78052 : 16 Kbytes PD78053 : 24 Kbytes PD78054 : 32 Kbytes PD78P054 : 32 Kbytes PD78055 : 40 Kbytes PD78056 : 48 Kbytes PD78058 : 60 Kbytes PD78P058 : 60 Kbytes...

  • Page 579: Appendix B Development Tools

    APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the PD78054 and 78054Y subseries. Figure B-1 shows the configuration of the development tools.

  • Page 580: B-1. Development Tool Configuration

    Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Language processing software • Assembler package • C compiler package • C library source file • Device file PROM programming tool • PG-1500 controller PROM programming environment PROM programmer Programmer adapter...
  • Page 581 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Language processing software • Assembler package • C compiler package • C library source file • Device file PROM programming tool PROM programming environment PROM programmer Programmer...

  • Page 582: Language Processing Software

    B.1 Language Processing Software RA78K/0 Assembler Package CC78K/0 C Compiler Package Note DF78054 Device File CC78K/0-L C Library Source File Note The DF78054 can commonly be used for all the products of the RA78K/0, CC78K/0, SM78K0, ID78K0- NS, and ID78K0. APPENDIX B DEVELOPMENT TOOLS A program that converts a program written in mnemonic into object codes that microcomputers can process.
  • Page 583 APPENDIX B DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx RA78K0 Sxxxx CC78K0 Sxxxx DF78078 Sxxxx CC78K0-L xxxx Host Machine AA13 PC-9800 series AB13 IBM PC/AT™ and BB13 compatibles 3P16 HP9000 series 700™...

  • Page 584: Prom Writing Tools

    B.2 PROM Writing Tools B.2.1 Hardware PG-1500 PROM Programmer PA-78P054GC PA-78P054GK PA-78P054KK-T PROM Programmer Adapter B.2.2 Software PG-1500 Controller Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx PG1500 xxxx 5A13 PC-9800 series 5B13 IBM PC/AT and compatibles...

  • Page 585: Debugging Tools

    B.3 Debugging Tools B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS Note IE-78K0-NS In-circuit Emulator IE-70000-MC-PS-B Power Supply Adapter Note IE-70000-98-IF-C Interface Adapter Note IE-70000-CD-IF PC Card Interface Note IE-70000-PC-IF-C Interface Adapter Note IE-780308-NS-EM1 Emulation Board NP-80GC Emulation Probe EV-9200GC-80 Conversion Socket (refer to Figure B-2)
  • Page 586 B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A Note 1 IE-78001-R-A In-circuit Emulator IE-70000-98-IF-B or Note 1 IE-70000-98-IF-C Interface Adapter IE-70000-PC-IF-B or Note 1 IE-70000-PC-IF-C Interface adapter IE-78000-R-SV3 Interface Adapter Note 1 IE-780308-NS-EM1 Emulation Board Note 1 IE-78K0-R-EX1 Emulation Probe Conversion Board IE-780308-R-EM Note 2...

  • Page 587: Software

    B.3.2 Software (1/2) SM78K0 System Simulator Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx SM78K0 xxxx AA13 PC-9800 series AB13 IBM PC/AT and BB13 compatible Note Does not support WindowsNT. APPENDIX B DEVELOPMENT TOOLS Capable of debugging in C source level or assembler level while simulating the operation of the target system on the host machine.
  • Page 588 B.3.2 Software (2/2) Note ID78K0-NS Integrated debugger (supporting in-circuit emulator IE-78K0-NS) ID78K0 Integrated Debugger (supporting in-circuit emulator IE-78001-R-A) Note Under development Remark xxxx in the part number differs depending on the host machine and OS used. Sxxxx ID78K0-NS xxxx AA13 PC-9800 series AB13 IBM PC/AT and...

  • Page 589: Os For Ibm Pc

    Table B-2. Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A In-circuit Emulator IE-78000-R IE-78000-R-A Note To upgrade your cabinet, bring it to NEC. APPENDIX B DEVELOPMENT TOOLS Table B-1. OS for IBM PC Version Ver. 5.02 to Ver. 6.3...

  • Page 590: B-2. Ev-9200Gc-80 Drawing (For Reference Only)

    Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawing (For Reference Only) EV-9200GC-80 No.1 pin index APPENDIX B DEVELOPMENT TOOLS ITEM MILLIMETERS 18.0 14.4 14.4 18.0 4-C 2.0 16.0 18.7 16.0 18.7 0.35 EV-9200GC-80-G0 INCHES 0.709 0.567 0.567 0.709 4-C 0.079 0.031...

  • Page 591: B-3. Ev-9200Gc-80 Footprint (For Reference Only)

    APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprint (For Reference Only) Based on EV-9200GC-80 (2) Pad drawing (in mm) ITEM MILLIMETERS 19.7 15.0 0.65 ± 0.02 19=12.35 ± 0.05 0.65 ± 0.02 19=12.35 ± 0.05 15.0 19.7 6.0 ± 0.05 6.0 ±...

  • Page 592: B-4. Tgk-080Sdw Drawing (For Reference) (Unit: Mm)

    Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawing (For Reference) (unit: mm) TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm) I J J J Protrusion : 4 places Note Product by TOKYO ELETECH CORPORATION. APPENDIX B DEVELOPMENT TOOLS M2 screw L L LM ITEM MILLIMETERS...

  • Page 593: Appendix C Embedded Software

    APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the PD78054, 78054Y Subseries, the following embedded software is available. Real-time OS (1/2) RX78K/0 A real-time OS conforming to ITRON specifications. Real-time OS Added with the tool (configurator) to create the RX78K/0 nucleus and multiple information table. Used in combination with separately available Assembler Package (RA78K/0) and Device File (DF78054).
  • Page 594 Real-time OS (2/2) MX78K0 A ITRON specification subset OS. Added with MX78K0 nucleus. Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one executed next.

  • Page 595: Appendix D Register Index

    D.1 Register Index 8-bit timer mode control register (TMC1) ... 225 8-bit timer output control register (TOC1) ... 226 8-bit timer register 1 (TM1) ... 223 8-bit timer register 2 (TM2) ... 223 16-bit timer mode control register (TMC0) ... 184 16-bit timer output control register (TOC0) ...
  • Page 596 IF0H: Interrupt request flag register 0H ... 489 IF0L: Interrupt request flag register 0L ... 489 IF1L: Interrupt request flag register 1L ... 489, 508 IMS: Memory size switching register ... 517, 549, 550 INTM0: External interrupt mode register ... 189, 492 INTM1: External interrupt mode register ...
  • Page 597 PR0H: Priority specify flag register 0H ... 491 PR0L: Priority specify flag register 0L ... 491 PR1L: Priority specify flag register 1L ... 491 PSW: Program status word ... 109, 496 PUOH: Pull-up resistor option register H ... 153 PUOL: Pull-up resistor option register L ...
  • Page 598 [MEMO]...

  • Page 599: Appendix E Revision History

    APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major revisions from previous version P40/AD0-P47/AD7 pin I/O circuit types were changed. Connection method of unused AV Caution on OVF0 flag operations was added. Interval time of interval timer was corrected. Buzzer output frequency was corrected.
  • Page 600 Edition Major revisions from previous version Addition of following package to all devices: edition • 80-pin plastic QFP (14 14 mm, resin thickness: 1.4 mm) (under planning) Addition of following package to PD78058 • 80-pin plastic TQFP (fine pitch) (12 Addition of description to Caution in Figure 8-6.
  • Page 601 The PD78052(A),78053(A), and 78054(A) were added to the edition applicable types. The PD78P054Y was deleted from the applicable types. The following package was deleted from the PD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y Subseries: • 80-pin plastic QFP (14 14 mm, resin thickness 2.7 mm) Figure 9-10.
  • Page 602 [MEMO]...
  • Page 603 NEC Electronics Taiwan Ltd. Fax: 02-719-5951 Excellent Good Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.

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