Cache Behavior - ARM Cortex-A53 MPCore Technical Reference Manual

6.2

Cache behavior

6.2.1 Instruction cache disabled behavior
6.2.2 Instruction cache speculative memory accesses
6.2.3 Data cache disabled behavior
6.2.4 Data cache maintenance considerations
ARM DDI 0500D
ID021414
You cannot disable the L2 and L1 Data caches independently, because they are controlled by the
same enable. See System Control Register on page
filling of the cache is performed.
If the cache reports a hit on a memory location that is marked as Non-Cacheable or Device, this
is called an unexpected cache hit. In this architecturally
return incorrect data. Because the caches are physically addressed, improper translation table
configuration can create this scenario. Disabling the cache can also create this situation.
Non-Cacheable or Device accesses do not lookup in the cache, and therefore ignore any
unexpected cache hit.
If the instruction cache is disabled, fetches cannot access any of the instruction cache arrays. An
exception to this rule is the CP15 instruction cache operations. If the instruction cache is
disabled, the instruction cache maintenance operations can still execute normally.
If the instruction cache is disabled, all instruction fetches to cacheable memory are treated as if
they were non-cacheable. This means that instruction fetches might not be coherent with caches
in other cores, and software must take account of this.
Because there can be several unresolved branches in the pipeline, instruction fetches are
speculative, meaning there is no guarantee that they are executed. A branch or exceptional
instruction in the code stream can cause a pipeline flush, discarding the currently fetched
instructions. Because of the aggressive prefetching behavior, you must not place read-sensitive
devices in the same page as code. Pages with Device memory type attributes are treated as
Non-Cacheable Normal Memory. You must mark pages that contain read-sensitive devices with
the translation table descriptor XN (Execute Never) attribute bit. To avoid speculative fetches
to read-sensitive devices when address translation is disabled, these devices and code that are
fetched must be separated in the physical memory map. See the ARM
Manual ARMv8, for ARMv8-A architecture profile for more information.
If the data cache is disabled, loads and store instructions do not access any of the L2 or L1 Data
cache arrays. An exception to this rule is the CP15 data cache operations. If the data cache is
disabled, the data cache maintenance operations can still execute normally.
If the data cache is disabled, all loads and store instructions to cacheable memory are treated as
if they were non-cacheable. This means that they are not coherent with the caches in this core
or the caches in other cores, and software must take account of this.
DCIMVAC operations in AArch32 and DC IVAC instructions in AArch64 perform an
invalidate of the target address. If the data is dirty in the executing core then a clean is performed
before the invalidate.
DCISW operations in AArch32 and DC ISW instructions in AArch64 perform both a clean and
invalidate of the target set/way. The values of HCR.SWIO and HCR_EL2.SWIO have no effect.
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Level 1 Memory System
4-191. On a cache miss, critical word-first
case, the cache might
UNPREDICTABLE
Architecture Reference
®
6-3