ARM Cortex-R4 Technical Reference Manual

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Cortex

-R4 and Cortex-R4F

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Revision: r1p4

Technical Reference Manual

ARM DDI 0363G (ID073015)

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Page 2 This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Chapter 3 Programmers Model About the programmers model ..................3-2 Modes of operation and execution ................3-3 Memory model ......................3-4 Data structures ......................3-5 Registers ........................3-6 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 4 Power management 10-3 Chapter 11 FPU Programmers Model 11.1 About the FPU programmers model 11-2 11.2 General-purpose registers 11-3 11.3 System registers 11-4 11.4 Modes of operation 11-11 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 5 C.14 RFE and SRS instructions C-24 C.15 Synchronization instructions C-25 C.16 Coprocessor instructions C-26 C.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions C-27 C.18 Miscellaneous instructions C-28 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 6 Floating-point single-precision data processing instructions C-32 C.22 Floating-point double-precision data processing instructions C-33 C.23 Dual issue C-34 Appendix D ECC Schemes ECC scheme selection guidelines D-2 Appendix E Revisions ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 7: Preface
Preface This preface introduces the Cortex-R4 and Cortex-R4F Technical Reference Manual. It contains the following sections: • About this book on page viii • Feedback on page xii. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015...
Page 8: About This Book
The Cortex-R4F processor is a Cortex-R4 processor that includes the optional Floating Point Unit (FPU) extension. • In this book, references to the Cortex-R4 processor also apply to the Cortex-R4F processor, unless the context makes it clear that this is not the case. Product revision status The rnpn identifier indicates the revision status of the product described in this book, where: Identifies the major revision of the product.
Page 9 Introduces special terminology, denotes cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 10: Timing Diagrams
LOW for active-LOW signals. Lower-case n At the start or end of a signal name denotes an active-LOW signal. Additional reading This section lists publications by ARM and by third parties. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015...
Page 11: Other Publications
, for embedded software development resources including the http://onarm.com Cortex Microcontroller Software Interface Standard (CMSIS). ARM publications This book contains information that is specific to the Cortex-R4 processor. See the following documents for other relevant information: • AMBA AXI Protocol Specification (ARM IHI 0022) •...
Page 12: Feedback
Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version.
Page 13 Configurable options on page 1-6 • Test features on page 1-10 • Product documentation, architecture and design flow on page 1-11 • Product revisions on page 1-13 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 14: Chapter 1 Introduction
RAM, in addition to caches for higher performance to general memory. Error Checking and Correction (ECC) is used on the Cortex-R4 processor ports and in Level 1 (L1) memories to provide improved reliability and address safety-critical applications.
Page 15: Compliance
The Cortex-R4 processor implements the ETM v3.3 architecture profile. See the CoreSight ETM-R4 Technical Reference Manual. 1.2.3 Advanced Microcontroller Bus Architecture This Cortex-R4 processor complies with the AMBA 3 protocol. See AMBA AXI Protocol Specification and AMBA 3 APB Protocol Specification. 1.2.4 Debug architecture The Cortex-R4 processor implements the ARMv7 Debug architecture that includes support for CoreSight.
Page 16: Features
• Low interrupt latency. • Non-maskable interrupt. • Optional Floating Point Unit (FPU). The Cortex-R4F processor is a Cortex-R4 processor that includes the FPU. • A Harvard L1 memory system with: — optional Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking memories —...
Page 17: Interfaces
All the processor AMBA interfaces conform to one of the following AMBA 3 specifications: • AMBA AXI Protocol Specification • AMBA APB Protocol Specification. The debug interfaces are CoreSight compliant, see the CoreSight Architecture Specification. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 18: Configurable Options
No error checking Build Parity error checking 32-bit ECC error checking 64-bit ECC error checking 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 19 AXI bus parity generated/ checked Breakpoints 2-8 breakpoint register pairs Build Watchpoints 1-8 watchpoint registers Build ATCM at reset Disabled Base address Build and pin Enabled Base address configured ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 20 ACTLR.B0TCMPCEN/ BTCM parity check enable, for B0TCM and B1TCM independently ACTLR.B1TCMPCEN ACTLR.ATCMPCEN ATCM ECC check enable ACTLR.B0TCMPCEN/ BTCM ECC check enabled, for B0TCM and B1TCM together ACTLR.B1TCMPCEN ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 21 DCCMOUT[7:0] and DCCMOUT2[7:0] enable the comparators to communicate with the rest of the SoC. Contact your system integrator for more information about these signals. ARM provides example comparison logic, but you can change this during implementation. If you are implementing a redundant processor configuration, contact ARM for more information.
Page 22: Test Features
TCMs for the processor to execute. See Accessing RAMs using the AXI slave interface on page 9-24 for more information about how to access the RAMs using the AXI slave interface. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 1-10 ID073015 Non-Confidential...
Page 23: Product Documentation, Architecture And Design Flow
Introduction Product documentation, architecture and design flow This section describes the Cortex-R4 processor books, how they relate to the design flow, and the relevant architectural standards and protocols. It contains the following sections: • Documentation • Design flow on page 1-12.
Page 24 Introduction 1.7.2 Design flow The Cortex-R4 processor is delivered as synthesizable RTL. Before it can be used in a product, it must go through the following processes: Implementation The implementer configures and synthesizes the RTL to produce a hard macrocell. This might include integrating RAMs into the design.
Page 25: Product Revisions
The Revision field of the Peripheral ID Register 2 changes to . See Peripheral ID Register 2 functions on page 12-40. • Various engineering errata fixes. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 1-13 ID073015 Non-Confidential...
Page 26: Functional Description
This chapter describes the functionality of the processor. It contains the following sections: • About the functions on page 2-2 • Interfaces on page 2-9 • Clocking and resets on page 2-11 • Operation on page 2-15. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 27: About The Functions
Load/Store Unit (LSU) for data memory transfers. The PFU and LSU interface to the L1 memory system that contains L1 instruction and data caches and an interface to a L2 system. The L1 memory can also contain optional TCM interfaces. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 28: Branch Prediction
It decodes and executes instructions, operating on data held in the registers in accordance with the ARM architecture. Instructions are fed to the DPU from the PFU through a buffer. The DPU performs instructions that require data to be transferred to or from the memory system by interfacing to the LSU.
Page 29 Error correction and detection To increase the tolerance of the system to soft memory faults, you can configure the caches for either: • parity generation and error correction/detection ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 30 The Embedded Trace Macrocell (ETM) interface enables you to connect an external ETM unit to the processor for real-time code tracing of the core in an embedded system. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 31: Interrupt Handling
System identification control and configuration on page 4-2. 2.1.8 Interrupt handling Interrupt handling in the processor is compatible with previous ARM architectures, but has several additional features to improve interrupt performance for real-time applications. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved.
Page 32: Exception Processing
Functional Description VIC port The core has a dedicated port that enables an external interrupt controller, such as the ARM PrimeCell Vectored Interrupt Controller (VIC), to supply a vector address along with an Interrupt Request (IRQ) signal. This provides faster interrupt entry, but you can disable it for compatibility with earlier interrupt controllers.
Page 33 Standby mode. For more information on the power management features, see Chapter 10 Power Control. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 34: Interfaces
2.2.7 APB Debug interface AMBA APBv3 is used for debugging purposes. CoreSight is the ARM architecture for multi-processor trace and debug. CoreSight defines what debug and trace components are required and how they are connected. See the CoreSight Architecture Specification for more information.
Page 35 The test interface provides support for test during manufacture of the processor using Memory Built-In Self Test (MBIST). MBIST signals on page A-21 describes the test interface signals. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-10 ID073015 Non-Confidential...
Page 36: Clocking And Resets
Unless otherwise stated, whenever nRESET is asserted, it must be held asserted for at least four CLKIN cycles to ensure correct reset operation. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-11 ID073015...
Page 37: Normal Operation
CLKIN nRESET nSYSPORESET Figure 2-2 Power-on reset ARM recommends that you assert the nRESET signal for at least four CLKIN cycles to ensure correct reset behavior. It is not necessary to assert PRESETDBGn on power-up. Processor reset A processor or warm reset initializes the majority of the processor, excluding the CoreSight logic.
Page 38 All clocks can be stopped indefinitely without loss of state. Three additional clock inputs, CLKIN2, DUALCLKIN, and DUALCLKIN2, are related to the dual-redundant core functionality, if included. If you are integrating a Cortex-R4 macrocell with dual-redundant core, contact the implementer of that macrocell for information about how to connect the clock inputs.
Page 39 Functional Description CLKIN STANDBYWFI CPU_CLK ATCEN0 ATCM_CLK Figure 2-4 Standby, wake-up ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-14 ID073015 Non-Confidential...
Page 40: Operation
PC-relative load instruction. The Current Program Status Register (CPSR) is given a known value on reset. See the ARM Architecture Reference Manual for more information. The reset values for the CP15 registers...
Page 41 The processor does not initialize the TCM RAMs. It is not essential to initialize all the memory attached to the TCM interface but ARM recommends that you do. In addition, the main application might require you to preload instructions or data into the TCM. This section describes various ways that you can perform data preloading.
Page 42 Write to the TCM using any store instructions, or any AXI write transactions. The processor performs read-modify-write accesses to ensure that all writes are to 64-bit aligned quantities, even though error checking is turned off. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-17 ID073015 Non-Confidential...
Page 44 Exceptions on page 3-14 • Acceleration of execution environments on page 3-25 • Unaligned and mixed-endian data access support on page 3-26 • Big-endian instruction support on page 3-27. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 45: Chapter 3 Programmers Model
Reference Manual. This chapter describes some of the main features of the architecture but, for a complete description, see the ARM Architecture Reference Manual. This chapter also makes reference to older versions of the ARM architecture that the processor does not implement. These references are included to contrast the behavior of the Cortex-R4 processor with other processors you might have used that implement an older version of the architecture.
Page 46: Modes Of Operation And Execution
Operating modes In each state there are seven modes of operation: • User (USR) mode is the usual mode for the execution of ARM or Thumb programs. It is used for executing most application programs. • Fast interrupt (FIQ) mode is entered on taking a fast interrupt.
Page 47: Memory Model
Figure 3-2 shows little-endian format. Memory Register Address A[31:0] 24 23 16 15 lsbyte msbyte Figure 3-2 Little-endian format ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 48: Data Structures
Unaligned and mixed-endian data access support on page 3-26. Note You cannot use , or instructions to access 32-bit quantities if they are not LDRD STRD 32-bit aligned. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 49: Registers
3.5.1 The register set In the processor the same register set is used in both the ARM and Thumb states. Sixteen general registers and one or two status registers are accessible at any time. In Privileged modes, alternative mode-specific banked registers become available.
Page 50 Programmers Model For more information, see the ARM Architecture Reference Manual. In Privileged modes, another register, the Saved Program Status Register (SPSR), is accessible. This contains the condition code flags, status bits, and current mode bits saved as a result of the exception that caused entry to the current mode.
Page 51 The instruction enables you to add high register values to low register values. For more information, see the ARM Architecture Reference Manual. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 52: Program Status Registers
In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits. The exceptions are: •...
Page 53 In Thumb state, the processor can only execute the Branch instruction conditionally. Other instructions can be made conditional by placing them in the If-Then (IT) block. For more information about conditional execution in Thumb state, see the ARM Architecture Reference Manual.
Page 54 Programmers Model For more information on the operation of the IT execution state bits, see the ARM Architecture Reference Manual. 3.6.4 The J bit The J bit in the CPSR returns 0 when read. Note You cannot use an to change the J bit in the CPSR.
Page 55 3.6.7 The E bit ARM and Thumb instructions are provided to set and clear the E bit. The E bit controls load/store endianness. See the ARM Architecture Reference Manual for information on where the E bit is used. 3.6.8 The A bit The A bit is set automatically by certain exceptions and is written by privileged software.
Page 56 User mode, as described in Exceptions on page 3-14. Bits in Figure 3-4 on page 3-9 that are in this category are A, I, F, and M[4:0]. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-13 ID073015 Non-Confidential...
Page 57: Exceptions
3.7.1 Exception entry and exit summary Table 3-4 summarizes the PC value preserved in the relevant R14 on exception entry, and the instruction that ARM recommends for exiting the exception handler. Table 3-4 Exception entry and exit Previous state Exception...
Page 58 For more information about the IT instruction and Undefined instruction, and an example of the exception handler code, see the ARM Architecture Reference Manual.
Page 59 Forces the PC to fetch the next instruction from the reset vector address. Reverts to ARM state or Thumb state depending on the state of the TEINIT pin, and resumes execution. After reset, all register values except the PC and CPSR are indeterminate.
Page 60 LOW until the processor acknowledges the interrupt request from the software handler. Irrespective of whether exception entry is from ARM state or Thumb state, an FIQ handler returns from the interrupt by executing: SUBS PC, R14_fiq, #4 If Non-Maskable Fast Interrupts (NMFIs) are not enabled, you can mask FIQ exceptions by setting the CPSR.F bit to b1.
Page 61: Interrupt Controller
SoC peripheral that is developed, tested, and licensed by ARM. You can use the VIC port to connect a PL192 VIC to the processor. See the ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual for more information about the PL192 VIC.
Page 62 Program status registers on page 3-9. For information on the V and VE bits that Figure 3-5 shows, see c1, System Control Register on page 4-37. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-19 ID073015 Non-Confidential...
Page 63 Register (r14_abt) to determine which instruction generated the abort, and the value in the Saved Program Status Register (SPSR_abt) to determine the state of the processor when the abort occurred. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-20 ID073015 Non-Confidential...
Page 65 MOVS PC, R14_svc This action restores the PC and CPSR, and returns to the instruction following the SVC. IRQs are disabled when a software interrupt occurs. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-22 ID073015 Non-Confidential...
Page 66 SPSR are correct for the instruction following the SVC. This means that the SVC handler does not have to perform any special action to accommodate the IT instruction. For more information on the IT instruction, see the ARM Architecture Reference Manual.
Page 67: Exception Vectors
0x00 Undefined instruction Undefined Unchanged Unchanged 0x04 Software interrupt Supervisor Unchanged Unchanged 0x08 Abort (prefetch) Abort Unchanged 0x0C Abort (data) Abort Unchanged 0x10 Unchanged 0x18 0x1C ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-24 ID073015 Non-Confidential...
Page 68: Acceleration Of Execution Environments
Ignore writes MCR p14, 7, <Rd>, c1, c0, 0 Note Because no hardware acceleration is present in the processor, when the instruction is used, instruction is invoked. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-25 ID073015 Non-Confidential...
Page 69: Unaligned And Mixed-Endian Data Access Support
The processor supports byte-invariant big-endianness BE-8 and little-endianness LE. The processor does not support word-invariant big-endianness BE-32. Bit [7] of c1, Control Register is always 0. For more information on unaligned and mixed-endian data access support, see the ARM Architecture Reference Manual. ARM DDI 0363G Copyright ©...
Page 70: Big-Endian Instruction Support
CFGIE pin is still reflected in the SCTLR but the instruction format is always little-endian. The Build Options Register indicates whether the processor is built with instruction endianness control. See Build Options Registers on page 4-77. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-27 ID073015 Non-Confidential...
Page 71: System Control
It contains the following sections: • About system control on page 4-2 • Register summary on page 4-7 • Register descriptions on page 4-9. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 72: About System Control
Read-only Read/write Write-only Accessible in User mode Figure 4-1 System control and configuration registers Some of the functionality depends on how you set external signals at reset. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 73 The cache control and configuration registers consist of three read-only registers, one read/write register, and a number of write-only registers. Figure 4-3 on page 4-4 shows the arrangement of the registers in this functional group. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 74 • count events. The system performance monitor consists of 12 read/write registers. Figure 4-5 on page 4-5 shows the arrangement of registers in this functional group. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 75: System Validation
It can generate interrupts when the number of events reaches a given value. For more information on the programmers model of the performance counters see the ARM Architecture Reference Manual. See...
Page 76 System Control You can only change the cache size to a size supported by the cache RAMs implemented in your design. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 77: Register Summary
Build Options 1 Register on page 4-77 Build Options 2 c15, Build Options 2 Register on page 4-78 Software compatibility Thread And Process ID c13, Thread and Process ID Registers on page 4-65 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 78 Chapter 6 Events and Performance Monitor monitoring Validation System validation Validation Registers on page 4-66 a. Known as the ID Code Register on previous designs. Returns the device ID code. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 79: Register Descriptions
CRn, Opcode_1, CRm, Opcode_2. For more information on using the system control coprocessor and the general method of how to access CP15 registers, see the ARM Architecture Reference Manual. 4.3.1 Register allocation...
Page 80 MPU Region Size and Read/write page 4-53 0x00000000 Enable Undefined MPU Region Access Read/write page 4-54 0x00000000 Control Undefined MPU Memory Region Read/write page 4-57 0x00000000 Number ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-10 ID073015 Non-Confidential...
Page 81 4-59 physical address Clean data cache line by Write-only page 4-59 Set/Way Undefined Data Synchronization Write-only page 4-61 Barrier Data Memory Barrier Write-only page 4-61 Undefined ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-11 ID073015 Non-Confidential...
Page 82 Read/write Unpredictable page 6-13 Selection Undefined Cycle Count Read/write page 6-13 0x00000000 Event Select Read/write Unpredictable page 6-14 Performance Monitor Read/write page 6-15 0x00000000 Count Undefined ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-12 ID073015 Non-Confidential...
Page 83 Unpredictable page 4-71 nVAL Reset Enable Clear Read/write Unpredictable page 4-72 nVAL Debug Request Read/write Unpredictable page 4-73 Enable Clear Build Options 1 Read-only page 4-77 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-13 ID073015 Non-Confidential...
Page 84 Table 4-3 on page 4-15. Figure 4-7 shows the MIDR bit assignments. 20 19 16 15 Implementer Variant Architecture Primary part number Revision Figure 4-7 MIDR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-14 ID073015 Non-Confidential...
Page 85 Table 4-4 on page 4-16. Figure 4-8 shows the CTR bit assignments. 28 27 24 23 Reserved DMinLine Reserved IMinLine Figure 4-8 CTR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-15 ID073015 Non-Confidential...
Page 86 4-17. Figure 4-9 shows the TCMTR bit assignments. 31 30 29 28 19 18 16 15 Reserved BTCM Reserved ATCM Figure 4-9 TCMTR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-16 ID073015 Non-Confidential...
Page 87 TCM interfaces, can be considered equivalent to those defined in the ARM architecture. • The ARM architecture requires only the ITCM to be accessible from both instruction and data sides. In the Cortex-R4 processor, both ATCM and BTCM are accessible from both instruction and data sides. 4.3.5 c0, MPU Type Register...
Page 88 Privileged mode only. Configurations Available in all processor configurations. Attributes Table 4-7 on page 4-19. Figure 4-11 on page 4-19 shows the PFR0 bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-18 ID073015 Non-Confidential...
Page 89 Table 4-8 on page 4-20. Figure 4-12 shows the PFR1 bit assignments. 12 11 Reserved Microcontroller programmer’s model Security extension ARMv4 Programmer’s model Figure 4-12 PFR1 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-19 ID073015 Non-Confidential...
Page 90 Trace debug model – memory mapped Trace debug model – coprocessor Core debug model – memory mapped Secure debug model Core debug model – coprocessor Figure 4-13 ID_DFR0 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-20 ID073015 Non-Confidential...
Page 91 Memory Model Feature Register 1 on page 4-23 • c0, Memory Model Feature Register 2 on page 4-24 • c0, Memory Model Feature Register 3 on page 4-25. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-21 ID073015 Non-Confidential...
Page 92 Indicates support for Virtual Memory System Architecture (VMSA): = no support. To access the ID_MMFR0 read CP15 with: MRC p15, 0, <Rd>, c0, c1, 4 ; Read ID_MMFR0. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-22 ID073015 Non-Confidential...
Page 93 L1 cache line maintenance Indicates support for L1 cache line maintenance operations by Set and Way, operations - Set and Way unified architecture: (unified) = no support. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-23 ID073015 Non-Confidential...
Page 94 TLB maintenance operations (Harward) L1 cache maintenance range operations (Harward) L1 background prefetch cache operations L1 foreground prefetch cache operations Figure 4-16 ID_MMFR2 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-24 ID073015 Non-Confidential...
Page 95 Privileged mode only. Configurations Available in all processor configurations. Attributes Table 4-13 on page 4-26. Figure 4-17 on page 4-26 shows the ID_MMFR3 bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-25 ID073015 Non-Confidential...
Page 96 • Invalidate instruction cache by address • Invalidate all instruction cache entries. a. Both of these operations are NOP on Cortex-R4. To access the ID_MMFR3 read CP15 with: MRC p15, 0, <Rd>, c0, c1, 7 ; Read ID_MMFR3. 4.3.11 Instruction Set Attributes Registers The processor has eight Instruction Set Attributes Registers, ISAR0 to ISAR7, but three of these are unused.
Page 97 = no support. [15:12] Compare and branch Indicates support for combined compare and branch instructions: instructions = the processor supports combined compare and branch instructions, CBNZ ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-27 ID073015 Non-Confidential...
Page 98 12 11 Jazelle instructions Interworking instructions Immediate instructions ITE instructions Extend instructions Exception 2 instructions Exception 1 instructions Endian instructions Figure 4-19 ID_ISAR1 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-28 ID073015 Non-Confidential...
Page 99 , and T bit in PSRs • , and PC loads have BX behavior • data-processing instructions in the ARM instruction set with the PC as the destination and the S bit clear have BX-like behavior. [23:20] Immediate Indicates support for immediate instructions:...
Page 100 SMMLA SMMLAR SMMLS , and SMMLSR SMPUL SMPULR SMUAD SMUADX SMUSD SMUSDX [15:12] Multiply Indicates support for multiply instructions: instructions = the processor supports , and ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-30 ID073015 Non-Confidential...
Page 101 ThumbEE extension True NOP instructions Thumb copy instructions Table branch instructions Synchronization primitive instructions SVC instructions SIMD instructions Saturate instructions Figure 4-21 ID_ISAR3 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-31 ID073015 Non-Confidential...
Page 102 Privileged mode only. Configurations Available in all processor configurations. Attributes Table 4-18 on page 4-33. Figure 4-22 on page 4-33 shows the ID_ISAR4 bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-32 ID073015 Non-Confidential...
Page 103 Privileged mode only. Configurations Available in all processor configurations. Attributes In the processor, ID_ISAR5 is read as 0x00000000 To access the ID_ISAR5, read CP15 with: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-33 ID073015 Non-Confidential...
Page 104 = write-back support available [29] Indicates support available for read allocation: = read allocation support available [28] Indicates support available for write allocation: = write allocation support available ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-34 ID073015 Non-Confidential...
Page 105 Usage constraints The CLIDR is: • a read-only register • accessible in Privileged mode only. Configurations Available in all processor configurations. Attributes Table 4-21 on page 4-36. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-35 ID073015 Non-Confidential...
Page 106 Holds the value that the processor uses to select the CSSELR to use. Usage constraints The CSSELR is: • a read/write register • accessible in Privileged mode only. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-36 ID073015 Non-Confidential...
Page 107 SCTLR from User mode result in an Undefined Instruction exception. Configurations Available in all processor configurations. Attributes Table 4-23 on page 4-38. Figure 4-26 on page 4-38 shows the SCTLR bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-37 ID073015 Non-Confidential...
Page 108 The reset value of this bit is 0. [23:22] SBO. [21] Fast Interrupts enable. On the processor Fast Interrupts are always enabled. This bit is SBO. [20] SBZ. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-38 ID073015 Non-Confidential...
Page 109 1 = MPU enabled. If no MPU is implemented, this bit is SBZ. To use the SCTLR, ARM recommends that you use a read-modify-write technique. To access the SCTLR, read or write CP15 with: MRC p15, 0, <Rd>, c1, c0, 0 ; Read SCTLR MCR p15, 0, <Rd>, c1, c0, 0 ;...
Page 110 • accessible in Privileged mode only • ARM recommends that any instruction that changes bits [31:28] or [7] is followed by an instruction to ensure that the changes have taken effect before any dependent instructions are executed.
Page 111 Disable Low Interrupt Latency (LIL) on load/store multiples: 0 = Enable LIL on load/store multiples. This is the reset value. 1 = Disable LIL on all load/store multiples. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-41 ID073015 Non-Confidential...
Page 112 1 = ORA forced for OWA regions. Force write-through (WT) for write-back (WB) regions: 0 = No forcing of WT. This is the reset value. 1 = WT forced for WB regions. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-42 ID073015 Non-Confidential...
Page 113 • performance features • error and parity logic. Usage constraints The Secondary Auxiliary Control Register is: • a read/write register • accessible in Privileged mode only. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-43 ID073015 Non-Confidential...
Page 114 System Control • ARM recommends that any instruction that changes bits [20:16] is followed by an instruction to ensure that the changes have taken effect before any dependent instructions are executed. Configurations Available in all processor configurations. Attributes Table 4-25.
Page 115 = Propagate floating-point input denormal exception flag to output FPIDC. FPSCR.IDC [7:4] SBZ. BTCMECC Correction for internal ECC logic on BTCM ports: = Enabled. This is the reset value. = Disabled. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-45 ID073015 Non-Confidential...
Page 116 FPU exists in the processor. Configurations Available in all processor configurations. Attributes Table 4-26 on page 4-47. Figure 4-29 on page 4-47 shows the CPACR bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-46 ID073015 Non-Confidential...
Page 117 0b10110 Unpredictable Synchronous Parity/ECC Error 0b11001 Valid Asynchronous Parity/ECC Error 0b11000 Unpredictable Lowest Debug Event 0b00010 Unchanged All other encodings for these FSR bits are Reserved. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-47 ID073015 Non-Confidential...
Page 118 To use the DFSR read or write CP15 with: MRC p15, 0, <Rd>, c5, c0, 0 ; Read DFSR MCR p15, 0, <Rd>, c5, c0, 0 ; Write DFSR ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-48 ID073015 Non-Confidential...
Page 119 MCR p15, 0, <Rd>, c5, c0, 1 ; Write IFSR c5, Auxiliary Fault Status Registers The processor has two auxiliary fault status registers: • the Auxiliary Data Fault Status Register (ADFSR) ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-49 ID073015 Non-Confidential...
Page 120 This field is only valid for data cache store parity/ECC errors. On the AIFSR, and for TCM accesses, this field SBZ. To access the auxiliary fault status registers, read or write CP15 with: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-50 ID073015...
Page 121 A write to this register sets the IFAR to the value of the data written. This is useful for a debugger to restore the value of the IFAR. 4.3.20 c6, MPU memory region programming registers The MPU memory region programming registers program the MPU regions. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-51 ID073015 Non-Confidential...
Page 122 Table 4-31 on page 4-53. Figure 4-33 shows the MPU Region Base Address Registers bit assignments. Base address Reserved Figure 4-33 MPU Region Base Address Registers bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-52 ID073015 Non-Confidential...
Page 123 MPU Region Size and Enable Registers bit assignments. Reserved Sub-region disable Region size Reserved Enable Figure 4-34 MPU Region Size and Enable Registers bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-53 ID073015 Non-Confidential...
Page 124 Use these registers if the processor is configured with an MPU. Attributes Table 4-33 on page 4-55. Figure 4-35 on page 4-55 shows the MPU Region Access Control Registers bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-54 ID073015 Non-Confidential...
Page 125 S bit Normal Outer and Inner write-back, no write-allocate. S bit Outer and Inner Non-cacheable. Normal S bit Reserved. Outer and Inner write-back, write-allocate. Normal S bit ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-55 ID073015 Non-Confidential...
Page 126 Writes in User mode generate permission faults b011 Read/write Read/write Full access b100 Reserved b101 Read-only No access Privileged read-only b110 Read-only Read-only Privileged/User read-only b111 Reserved ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-56 ID073015 Non-Confidential...
Page 127 Writing this register with a value greater than or equal to the number of regions from the MPUIR is Unpredictable. Associated MPU Region Register accesses are also Unpredictable. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-57 ID073015...
Page 128 Invalidate Branch Predictor Array Line using MVA, CRm= c5, Opcode_2 = 7. The Wait For Interrupt ( ) instruction provides the Wait For Interrupt function. For more information see the ARM Architecture Reference Manual. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-58 ID073015 Non-Confidential...
Page 129: Invalidate And Clean Operations
This processor does not contain an address-based branch predictor array. Invalidate and clean operations The terms that describe the invalidate, clean, and prefetch operations are defined in the ARM Architecture Reference Manual. You can perform invalidate and clean operations on: •...
Page 130 Table 4-40 Invalidate and clean operations bit assignments Bits Name Function [31:5] Address Specifies the address to invalidate or clean [4:0] ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-60 ID073015 Non-Confidential...
Page 131 To access the Data Synchronization Barrier operation, write CP15 with: MCR p15, 0, <Rd>, c7, c10, 4 ; Data Synchronization Barrier operation For more information about memory barriers, see the ARM Architecture Reference Manual. Data Memory Barrier operation The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin.
Page 132 Figure 4-41 shows the ATCM Region Register bit assignments. 12 11 2 1 0 Base address Reserved Size Reserved Enable Figure 4-41 ATCM Region Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-62 ID073015 Non-Confidential...
Page 133 Privileged mode only. Configurations Available in all processor configurations. Attributes Table 4-43 on page 4-64. Figure 4-42 on page 4-64 shows the Slave Port Control Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-63 ID073015 Non-Confidential...
Page 134 Privileged mode only. Configurations Available in all processor configurations. Attributes The CONTEXTIDR, bits [31:0] contain the process ID number. To use the CONTEXTIDR, read or write CP15 with: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-64 ID073015 Non-Confidential...
Page 135 You must clear the contents of all Thread and Process ID registers on process switches to prevent data leaking from one process to another. This is important to ensure the security of data. The reset value of these registers is 0. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-65 ID073015 Non-Confidential...
Page 136 IRQ Enable Set Register bit assignments. Table 4-44 nVAL IRQ Enable Set Register bit assignments Bits Name Function [31] PMCCNTR overflow IRQ request [30: 3] UNP or SBZP ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-66 ID073015 Non-Confidential...
Page 137 3 2 1 0 Reserved Cycle count overflow FIQ request enable Performance monitor counter overflow FIQ request enables Figure 4-44 nVAL FIQ Enable Set Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-67 ID073015 Non-Confidential...
Page 138 Configurations Available in all processor configurations. Attributes Table 4-46 on page 4-69. Figure 4-45 on page 4-69 shows the nVAL Reset Enable Set Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-68 ID073015 Non-Confidential...
Page 139 Available in all processor configurations. Attributes Table 4-47 on page 4-70. Figure 4-46 on page 4-70 shows the VAL Debug Request Enable Set Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-69 ID073015 Non-Confidential...
Page 140 Configurations Available in all processor configurations. Attributes Table 4-48 on page 4-71. Figure 4-47 on page 4-71 shows the nVAL IRQ Enable Clear Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-70 ID073015 Non-Confidential...
Page 141 Configurations Available in all processor configurations. Attributes Table 4-49 on page 4-72. Figure 4-48 on page 4-72 shows the nVAL FIQ Enable Clear Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-71 ID073015 Non-Confidential...
Page 142 Configurations Available in all processor configurations. Attributes Table 4-50 on page 4-73. Figure 4-49 on page 4-73 shows the nVAL Reset Enable Clear Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-72 ID073015 Non-Confidential...
Page 143 Available in all processor configurations. Attributes Table 4-51 on page 4-74. Figure 4-50 on page 4-74 shows the VAL Debug Request Enable Clear Register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-73 ID073015 Non-Confidential...
Page 144 Table 4-52 on page 4-75. Figure 4-51 shows the Cache Size Override Register bit assignments. 16 15 Dcache Reserved Icache Figure 4-51 Cache Size Override Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-74 ID073015 Non-Confidential...
Page 145 ECC errors in the instruction cache — single-bit ECC errors in the data cache — parity or multi-bit errors in the data cache when write-through behavior is forced ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-75 ID073015 Non-Confidential...
Page 146 CFLR bit assignments, when it indicates a correctable TCM error. 26 25 24 23 22 3 2 1 0 Reserved Side Address[22:3] Type Reserved Reserved Figure 4-53 CFLR - TCM, bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-76 ID073015 Non-Confidential...
Page 147 Attributes Table 4-56 on page 4-78. Figure 4-54 shows the Build Options 1 Register bit assignments. TCM_HI_INIT_ADDR Reserved Figure 4-54 Build Options 1 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-77 ID073015 Non-Confidential...
Page 148 ATCM_ES BTCM_ES NO_IE NO_FPU NO_MPU MPU_REGIONS BREAK_POINTS WATCH_POINTS NO_A_TCM_INF NO_B0_TCM_INF NO_B1_TCM_INF TCMBUSPARITY NO_SLAVE ICACHE_ES DCACHE_ES N0_HARD_ERROR_CACHE AXIBUSPARITY RESERVED Figure 4-55 Build Options 2 Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-78 ID073015 Non-Confidential...
Page 149 Indicates the number of break points implemented in the processor, minus 1. [16:14] WATCH_POINTS Indicates the number of watch points implemented in the processor, minus 1. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-79 ID073015 Non-Confidential...
Page 150 The value of this bit is Unpredictable in revision r1p0 of the processor. To access the Build Options 2 Register, write CP15 with: MRC p15, 0, <Rd>, c15, c2, 1 ; read Build Options 2 Register ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-80 ID073015 Non-Confidential...
Page 151: About The Prefetch Unit
About the prefetch unit on page 5-2 • Branch prediction on page 5-3 • Return stack on page 5-5 • Controlling instruction prefetch and program flow prediction on page 5-6. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 152 The PFU fetches instructions from the memory system under the control of the DPU, and the internal coprocessors CP14 and CP15. In ARM state the memory system can supply up to two instructions per cycle. In Thumb state the memory system can supply up to four instructions per cycle.
Page 153: Branch Prediction
2-bit hint indicates if the next branch must be predicted taken or predicted not-taken based on the behavior of previous branches. The history table contains 256 entries. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 154: Return Stack
The DPU resolves branches that the dynamic branch predictor predicts at the Wr-stage of the pipeline. A misprediction causes the PFU to flush the pipeline and fetch the correct instruction stream. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 155 The return stack consists of a 4-entry circular buffer. When the PFU detects a taken procedure call instruction, the PFU pushes the return address onto the return stack. The instructions that the PFU recognizes as procedure calls are, in both the ARM and Thumb instruction sets: •...
Page 156: Controlling Instruction Prefetch And Program Flow Prediction
Prefetch Unit Controlling instruction prefetch and program flow prediction In the Cortex-R4 processor, the Z-bit, bit [11] of the SCTLR, does not control the program flow prediction. The Z-bit is read-as-one, writes-ignored and instead a number of control bits in the ACTLR control the program flow and prefetch features.
Page 157: About The Events
About the events on page 6-2 • About the PMU on page 6-6 • Performance monitoring registers on page 6-7 • Event bus interface on page 6-19. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 158: About The Pmu
This event occurs for every instruction that explicitly writes data, including Instruction architecturally executed. 0x08 Dual-issued pair of instructions architecturally executed. 0x5e Exception taken. 0x09 This event occurs on each exception taken. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 159 , Strongly-ordered memory access, or similar events. The number of cycles FIQ interrupts are disabled. 0x46 The number of cycles IRQ interrupts are disabled. 0x47 ETMEXTOUT[0]. 0x48 ETMEXTOUT[1]. 0x49 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 160 B0TCM multi-bit ECC error. 0x65 [39] B1TCM multi-bit ECC error. 0x66 [40] ATCM single-bit ECC error. 0x67 [41] B0TCM single-bit ECC error. 0x68 [42] B1TCM single-bit ECC error. 0x69 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 161 TCM correctable ECC error reported by AXI slave interface. 0x6D Cycle count 0xFF a. This event is only generated for by revisions r1p2 and later of the processor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 162: Performance Monitoring Registers
NIDEN inputs are asserted. The PMCCNTR Register is always enabled regardless of whether non-invasive debug is enabled, unless the DP bit of the PMCR register is set. See Performance Monitor Control Register on page 6-7. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 163 Figure 6-1 shows the PMCR bit assignments. 24 23 16 15 4 3 2 1 0 IDCODE Reserved D C P E Figure 6-1 PMCR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 164 Usage constraints The PMCNTENSET Register is: • accessible in: — Privileged mode — User mode only when the PMUSERENR.EN bit is set to 1, c9, User Enable Register on page 6-15. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 165 Count Enable Clear Register The PMCNTENCLR Register characteristics are: Purpose Disables any of the Event Count Registers. Usage constraints The PMCNTENCLR Register is: • accessible in: — Privileged mode ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 166 PMCR is clear, even though their settings are ignored. The PMCNTENCLR Register can be used to clear the enabled flags for individual counters even when all counters are disabled in the PMCR Register. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-10 ID073015 Non-Confidential...
Page 167 • disabling the overflowed counter in the PMCNTENCLR Register • disabling all counters in the PMCR Register • resetting the overflowed counter using the PMCR Register. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-11 ID073015 Non-Confidential...
Page 168 To access the PMSWINC Register, read or write CP15 with: MRC p15, 0, <Rd>, c9, c12, 4 ; Read PMSWINC Register MCR p15, 0, <Rd>, c9, c12, 4 ; Write PMSWINC Register ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-12 ID073015 Non-Confidential...
Page 169 MCR p15, 0, <Rd>, c9, c12, 5 ; Write PMSELR Register 6.3.7 c9, Cycle Count Register The PMCCNTR Register characteristics are: Purpose Counts clock cycles. Usage constraints The PMCCNTR Register: • Is a 32-bit read/write register. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-13 ID073015 Non-Confidential...
Page 170 Name Function [31:8] RAZ or SBZP. [7:0] Event number selected, see Table 6-1 on page 6-2 for values. The reset value of this field is Unpredictable. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-14 ID073015 Non-Confidential...
Page 171 Configurations Available in all processor configurations. Attributes Table 6-9 on page 6-16. Figure 6-8 on page 6-16 shows the PMUSERENR bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-15 ID073015 Non-Confidential...
Page 172 Privileged mode only. Configurations Available in all processor configurations. Attributes Table 6-10 on page 6-17. Figure 6-9 on page 6-17 shows the PMINTENSET bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-16 ID073015 Non-Confidential...
Page 173 This is the only mechanism that signals this interrupt to the processor. Note ARM expects that the Performance Monitor interrupt request signal, nPMUIRQ, connects to a system interrupt controller. 6.3.12...
Page 174 To access the PMINTENCLR Register, read or write CP15 with: MRC p15, 0, <Rd>, c9, c14, 2 ; Read PMINTENCLR Register MCR p15, 0, <Rd>, c9, c14, 2 ; Write PMINTENCLR Register ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-18 ID073015 Non-Confidential...
Page 175: Event Bus Interface
The processor also has two event input pins, ETMEXTOUT[1:0]. This bus is normally intended for connection to the ETM, and enables the Cortex-R4 performance monitor to count events generated by the ETM. These inputs can alternatively be used for composite events generated external to the processor.
Page 176: Memory Protection Unit
Region attributes on page 7-8 • MPU interaction with memory system on page 7-9 • MPU faults on page 7-10 • MPU software-accessible registers on page 7-11. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 177: About The Mpu
About the MPU The MPU works with the L1 memory system to control accesses to and from L1 and external memory. For a full architectural description of the MPU, see the ARM Architecture Reference Manual. The MPU enables you to partition memory into regions and set individual protection attributes for each region.
Page 178 All region sizes between 256 bytes and 4GB support eight subregions. Region sizes of less than 256 bytes do not support subregions, and the subregion disable field is SBZ/UNP for regions of less than 256 bytes in size. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 179 To ensure correct operation, only a memory region that has permission for data read access can execute instructions. For more information, see the ARM Architecture Reference Manual. For information about how to program access permissions, see Table 4-36 on page 4-56.
Page 180 If the current process overflows the stack it uses, a write access by the processor to the disabled subregion causes the MPU to raise a background fault. 0x4000 Stack 0x0800 Guard region 0x0000 Figure 7-3 Overlapping subregion of memory ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 181 Access permissions for an address in a TCM region are preserved from the MPU region that the address also belongs to. For more information, see About the TCMs on page 8-13. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 182: Memory Types
Memory Protection Unit Memory types The ARM architecture defines a set of memory types with characteristics that are suited to particular devices. There are three mutually exclusive memory type attributes: • Strongly-ordered • Device • Normal. MPU memory regions can each be assigned a memory type attribute.
Page 183: Region Attributes
Note In earlier versions of the ARM architecture, the TEX, C, and B bits were known as the Type Extension, Cacheable and Bufferable bits. These names no longer adequately describe the function of the B, C, and TEX bits.
Page 184: Mpu Interaction With Memory System
Fetch from default memory map Fetch from default memory map Fetch from default memory map Fetch from default memory map Table 7-1 on page 7-2 shows the default memory map. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 185: Mpu Faults
Architecture Reference Manual for information. In addition, strict alignment can be required for all data accesses by setting the A-bit in the SCTLR. See c1, System Control Register on page 4-37. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 7-10 ID073015 Non-Confidential...
Page 186: Mpu Software-Accessible Registers
When the MPU is not present, the c6, MPU memory region programming registers on page 4-51 read as zero and ignore writes in Privileged mode. No Undefined Instruction exceptions are taken. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 7-11 ID073015 Non-Confidential...
Page 187 About the caches on page 8-18 • Internal exclusive monitor on page 8-34 • Memory types and L1 memory system behavior on page 8-35 • Error detection events on page 8-36. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 188: About The L1 Memory System
, can be used with the appropriate memory monitoring LDREX STREX to provide inter-process or inter-processor synchronization and semaphores. See the ARM Architecture Reference Manual for more information. The internal monitor can handle some exclusive monitoring internally to the processor, see Internal exclusive monitor on page 8-34 more information.
Page 189 Interconnect Memory Prefetch Unit Load Store Unit Protection Unit (PFU) (LSU) (MPU) AXI slave Data Processing Unit (DPU) AXI bus Figure 8-1 L1 memory system block diagram ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 190: About The Error Detection And Correction Schemes
In silicon devices, stray radiation and other effects can cause the data stored in a RAM to be corrupted. The TCMs and caches on the Cortex-R4 processor can be configured to detect and correct errors that can occur in the RAMs. Extra, redundant data is computed by the processor and stored in the RAMs alongside the real data.
Page 191 The processor contains features that enable it to recover from some hard errors. If you are implementing the processor and require these features, contact ARM to discuss the features and your requirements.
Page 192 AXI slave interface. The processor uses correct-and-retry correction when it detects a correctable ECC error on a TCM read made by the instruction side or data side. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 193: Fault Handling
MPU fault occurs on an access that is not in the TCM, and is Non-cacheable, or has generated a cache-miss, the AXI transactions for that access are not performed. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 194 A retry request from the TCM port is considered to be a recoverable error. All correctable ECC faults are also considered to be recoverable. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 195 Note When a prefetch abort has occurred, ARM recommends that you do not use the link register value for determining the aborting address, because 32-bit Thumb instructions do not have to be word aligned and can cause an abort on either halfword.
Page 196 Some types of abort are fatal to the system, and others can be fixed, and program execution resumed. For example, an MPU ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-10 ID073015...
Page 198 Instead, the sticky synchronous abort flag in the DBGDSCR is set. See CP14 c1, Debug Status and Control Register on page 12-14. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-12 ID073015 Non-Confidential...
Page 199: About The Tcms
XN permissions are applied to TCM accesses to that address. None of the other device or Strongly-ordered behaviors apply to an address in a TCM region. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-13 ID073015 Non-Confidential...
Page 200 Both the BTCM ports must have the same error scheme. The following sections describe these error schemes: • Handling TCM parity errors on page 8-15 • Handling TCM ECC errors on page 8-15. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-14 ID073015 Non-Confidential...
Page 201 PFU, with the AXI slave having lowest priority. When a higher-priority device is accessing a TCM port, an access from a lower-priority device must stall. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-15 ID073015 Non-Confidential...
Page 202 TCM ports to be of 64-bits of data. This feature is also known as Read-Modify-Write (RMW), because it causes the processor to generate read-modify-write ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-16 ID073015...
Page 203 TCMs. Although the Cortex-R4 processor can use semaphores in the TCMs for inter-process synchronization, you must not use the AXI slave interface to write to TCM semaphores. The processor has no logic to preserve its own exclusivity against such writes.
Page 204: About The Caches
See Cache error detection and correction on page 8-20 for more information. For more information on the general rules about memory attributes and behavior, see the ARM Architecture Reference Manual. 8.5.1 Store buffer The cache controller includes a store buffer to hold data before it is written to the cache RAMs or passed to the AXI master interface.
Page 205 All cache maintenance operations are done through the system control coprocessor, CP15. The system control coprocessor operations supported for the data cache are: • Invalidate all • Invalidate by address (MVA) ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-19 ID073015 Non-Confidential...
Page 206 RAMs. Each RAM normally includes a decoder that enables access to that data and, if an error occurs in this logic, it is not normally detected by these error ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-20 ID073015...
Page 207 Level One Memory System detection schemes. The processor includes features that enable it to detect some address decoder faults. If you are implementing the processor and require these features, contact ARM to discuss the features and your requirements. Handling cache parity errors...
Page 208 If required, software can use events and the CFLR to monitor the errors that are detected and corrected. See Error detection events on page 8-36 Correctable Fault Location Register on page 4-75. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-22 ID073015 Non-Confidential...
Page 209 • Invalidate all data cache on page 8-24 • Invalidate instruction cache by address on page 8-24 • Invalidate data cache by address on page 8-24 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-23 ID073015 Non-Confidential...
Page 210 WSTRBM AXI signal deasserted. If there is a correctable error, the line has the error corrected inline before it is written back to memory. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-24 ID073015...
Page 211 When force write-through is enabled, the dirty bit is ignored. If the tag or dirty RAM has an uncorrectable error, the data is not written to memory. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-25 ID073015...
Page 212 A cache line is marked as valid by bit [22] of the tag RAM. Each valid bit is associated with a whole cache line, so evictions always occur on the entire line. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-26 ID073015...
Page 213 Figure 8-3 on page 8-28 shows this. • Select the appropriate bank RAM for sequential read operations. Figure 8-4 on page 8-28 shows this. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-27 ID073015 Non-Confidential...
Page 214 Data RAM sizes without parity or ECC implemented on page 8-29 • Data RAM sizes with parity implemented on page 8-29 • Data RAM sizes with ECC implemented on page 8-30. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-28 ID073015 Non-Confidential...
Page 215 4 banks 72 bits 1024 lines or 8 banks 36 bits 1024 lines 64KB, 4 16KB ways 4 banks 72 bits 2048 lines or 8 banks 36 bits 2048 lines ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-29 ID073015 Non-Confidential...
Page 216 4 banks 72 bits 1024 lines or 8 banks 36 bits 1024 lines 64KB, 4 16KB ways 4 banks 72 bits 2048 lines or 8 banks 36 bits 2048 lines ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-30 ID073015 Non-Confidential...
Page 217 MCR p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache MCR p15, 0, r0, c7, c5, 0 ; Invalidate entire instruction cache MCR p15, 0, r1, c1, c0, 0 ; enabled cache RAMs ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-31 ID073015 Non-Confidential...
Page 218 ACTLR must only be changed when both caches are turned off and the entire cache must be invalidated after the change. ARM recommends the following code sequence to perform the change: MRC p15, 0, r0, c1, c0, 0 ; Read SCTLR BIC r0, r0, #0x1 <<...
Page 219 ; Enable data cache bit ORR r0, r0, #0x1 << 12 ; Enable instruction cache bit MCR p15, 0, r0, c1, c0, 0 ; Write SCTLR ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-33 ID073015 Non-Confidential...
Page 220: Internal Exclusive Monitor
The internal exclusive monitor holds exclusivity state for the Cortex-R4 processor only. It does not record the address of the memory that a load-exclusive access was performed to. Any store exclusive access performed when the state is open fails. If the state is exclusive, the access passes if it is to non-shared memory but, if it is to shared memory, the access must be performed as an exclusive using the L2 memory interface.
Page 221: Memory Types And L1 Memory System Behavior
Table 8-17 Memory types and associated behavior Internal Locked Memory type Can be cached Merging Restartable exclusives swaps Normal Shared Partially Non-shared Device Shared Partially Non-shared Strongly-ordered Shared Partially ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-35 ID073015 Non-Confidential...
Page 222: Error Detection Events
See Correctable Fault Location Register on page 4-75 for more information. Every correctable error that is recorded in the CFLR also ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-36 ID073015 Non-Confidential...
Page 223 CLFR does not record whether the error occurred in the data RAM or tag/dirty RAM. This distinction is only made by the events. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-37 ID073015...
Page 224 AXI slave interface on page 9-20 • Enabling or disabling AXI slave accesses on page 9-23 • Accessing RAMs using the AXI slave interface on page 9-24. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 225: About The L2 Interface
RAMs. You can use the AXI slave interface for DMA access into and out of the TCMs or to perform software test of the TCMs and cache RAMs. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 226: Axi Master Interface
In this section, AXI slave describes the AXI slave in the external system that is connected to the Cortex-R4 AXI master port. This might not be the Cortex-R4 AXI slave port. The following sections describe the attributes of the AXI master interface, and provide information about the types of burst generated: •...
Page 227 The LFBs are 256 bits wide so that an entire cache line can be written to the cache RAMs in one cycle. While the LFB is being filled from L2 memory, its bytes can be merged with write data from the STB. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 228: Memory Attributes
The EVB is removed if cache RAMs are not implemented for the processor. 9.2.5 Memory attributes The Cortex-R4 AXI master interface uses the ARCACHEM, AWCACHEM, ARUSERM, and AWUSERM signals to indicate the memory attributes of the transfer, as returned by the MPU.
Page 229 Device or Strongly-ordered memory generates an alignment fault and therefore does not cause any AXI transfer. This means that the access examples given in this chapter never show unaligned accesses to Device or Strongly-ordered memory. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 230: Axi Master Interface Transfers
This section describes the types of AXI transaction that the Cortex-R4 AXI master does not generate. If you are designing an AXI slave to work only with the Cortex-R4 processor, and there are no other AXI masters in your system, you can take...
Page 231 Level Two Interface 9.3.1 Restrictions on AXI transfers The Cortex-R4 AXI master interface applies the following restrictions to the AXI transactions it generates: • A burst never transfers more than 32 bytes. • The burst length is never more than 8 transfers.
Page 232 0x00 (word 1) Incr 32-bit 1 data transfer 0x04 Note A load of a word from Strongly-ordered or Device memory addresses , or generates an alignment fault. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 233 32-bit 5 data transfers 0x08 0x08 (word 3) Incr 32-bit 5 data transfers 0x0C 0x0C Note A load-multiple from address , or generates an alignment fault. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-10 ID073015 Non-Confidential...
Page 234 (halfword 3) Incr 16-bit 1 data transfer b11000000 0x06 Note A store of a halfword to Strongly-ordered or Device memory addresses , or generates an alignment fault. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-11 ID073015 Non-Confidential...
Page 235 7 data transfers b00001111 0x00 0x00 (word 1) Incr 32-bit 7 data transfers b11110000 0x04 0x04 Note A store-multiple to address , or generates an alignment fault. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-12 ID073015 Non-Confidential...
Page 236 1 data transfer 0x00 (byte 1) Incr 32-bit 1 data transfer 0x00 (byte 2) Incr 64-bit 1 data transfer 0x00 (byte 3) Incr 32-bit 2 data transfers 0x03 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-13 ID073015 Non-Confidential...
Page 237 2 data transfers 0x10 0x10 Incr 32-bit 1 data transfer 0x00 (word 5) Incr 64-bit 2 data transfers 0x14 0x14 Incr 64-bit 1 data transfer 0x00 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-14 ID073015 Non-Confidential...
Page 238 0x05 (byte 6) Incr 16-bit 1 data transfer b11000000 0x06 (byte 7) Incr 8-bit 1 data transfer b10000000 0x07 Incr 8-bit 1 data transfer b00000001 0x08 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-15 ID073015 Non-Confidential...
Page 239 64-bit read transfers, as shown in Table 9-19. Table 9-19 AXI transaction splitting, all six words in same cache line ARADDRM ARBURSTM ARSIZEM ARLENM Incr 64-bit 3 data transfers 0x1008 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-16 ID073015 Non-Confidential...
Page 240 It can do this to best use its ability to merge accesses. The instruction sequence in Example 9-1 on page 9-18 shows the merging of writes. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-17 ID073015 Non-Confidential...
Page 241 • The write transfers have occurred out of order with respect to the original program order. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-18 ID073015 Non-Confidential...
Page 242 AXI write transactions occur until the cache line is evicted and performs a write-back transaction. See Cache line write-back (eviction) on page 9-13. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-19 ID073015 Non-Confidential...
Page 243: Axi Slave Interface
RAMs is accessed within the caches. The AXI access is given a SLVERR error response when access to nonexistent cache RAM is indicated. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-20 ID073015 Non-Confidential...
Page 244 9.4.5 AXI slave control By default, both privileged and non-privileged accesses can be made to the Cortex-R4 TCM RAMs through the AXI slave port. To disable non-privileged accesses, you can set bit [1] in the Slave Port Control Register. You can disable all slave accesses by setting bit [0] of the register.
Page 245 All write data must be presented to the AXI slave interface in order Read data reorder depth The AXI slave interface returns all read data in order, even if the bursts have different IDs ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-22 ID073015 Non-Confidential...
Page 246: Enabling Or Disabling Axi Slave Accesses
MCR p15, 0, R1, c1, c0, 1 ; disabled AXI slave accesses to the cache RAMs Fetch from cached memory Fetch from cached memory Fetch from cached memory Fetch from cached memory ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-23 ID073015 Non-Confidential...
Page 247: Accessing Rams Using The Axi Slave Interface
Cache RAM access on page 9-26. Note Because AWUSERS and AWADDRS work in the same way as ARUSERS and ARADDRS, the following sections only describe ARUSERS and ARADDRS. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-24 ID073015 Non-Confidential...
Page 248 An access to the TCM RAMs is given a SLVERR error response if: • It is outside the physical size of the targeted TCM RAM, that is, bits of ARADDRS[22:MSB+1] are non-zero. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-25 ID073015 Non-Confidential...
Page 249 Not used, generates an error 1000 ARADDRS[22:21] != 00 Not used, generates an error Table 9-30 Cache tag/valid RAM bank/address decode Inputs RAM bank Cache selected ARADDRS[18:15] 0001 Bank 0 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-26 ID073015 Non-Confidential...
Page 250 Table 9-33 on page 9-28 shows the format when parity is implemented • Table 9-34 on page 9-28 shows the instruction cache format when ECC is implemented ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-27 ID073015 Non-Confidential...
Page 251 If accessing bits [15:0] of the data, bits [19:16] hold the lower half of the ECC code. If accessing bits [47:32] of the data, bits [19:16] hold the upper half of the ECC code. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-28 ID073015 Non-Confidential...
Page 252 [63:55] Not used, read-as-zero [54] Valid, way 2/3 [53:32] Tag value, way 2/3 [31:23] Not used, read-as-zero [22] Valid, way 0/1 [21:0] Tag value, way 0/1 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-29 ID073015 Non-Confidential...
Page 253 Table 9-40 Tag register format for writes, with parity Data bit Description [63:24] Not used, read-as-zero [23] Parity. all ways [22] Valid, all ways [21:0] Tag value, all ways ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-30 ID073015 Non-Confidential...
Page 255 Dirty value, way 3 [23] Not used, read-as-zero [22:19] ECC, way 2 [18:17] Outer attributes, way 2 [16] Dirty value, way 2 [15] Not used, read-as-zero ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-32 ID073015 Non-Confidential...
Page 256 MSBs for that read or write access are ignored. For example, accessing 0x10000000 0x00000000 addresses in the cache RAM accesses the same physical location . This means that such accesses are aliased and no errors are generated. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-33 ID073015 Non-Confidential...
Page 257: About Power Control
This chapter describes the processor power control functions. It contains the following sections: • About power control on page 10-2 • Power management on page 10-3. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 10-1 ID073015 Non-Confidential...
Page 258 In the processor, extensive use is also made of gated clocks and gates to disable inputs to unused functional blocks. Only the logic actively in use to perform a calculation consumes any dynamic power. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 10-2 ID073015 Non-Confidential...
Page 259: Power Management
RAMs, is powered down. In dormant mode, the processor state, apart from the cache and TCM state, is stored to memory before entry into this mode, and restored after exit. For more information on how to implement and use dormant mode in your design, contact ARM. 10.2.4...
Page 260 The STANDBYWFI signal can also signal that the processor is ready to have its power state changed. STANDBYWFI is asserted in response to a operation. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 10-4 ID073015 Non-Confidential...
Page 261 FPU Programmers Model This chapter describes the programmers model of the Floating Point Unit (FPU). The Cortex-R4F processor is a Cortex-R4 processor that includes the optional FPU. In this chapter, the generic term processor means only the Cortex-R4F processor. This chapter contains the following sections: •...
Page 262: About The Fpu Programmers Model
Manual for information on the VFPv3 instruction set. 11.1.1 FPU functionality The FPU is an implementation of the ARM Vector Floating Point v3 architecture, with 16 double-precision registers (VFPv3-D16). It provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.
Page 263: General-Purpose Registers
FPU Programmers Model 11.2 General-purpose registers The FPU implements a VFP register bank. This bank is distinct from the ARM register bank. You can reference the VFP register bank using two explicitly aliased views. Figure 11-1 shows the two views of the register bank and the way the word and doubleword registers overlap.
Page 264: System Registers
For a VFP system register to be accessible, it must follow the rules in Table 11-2 and the VFP must also be accessible according to the CPACR. See c1, Coprocessor Access Register on page 4-46 for more information. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-4 ID073015 Non-Confidential...
Page 265 Implementer ARM Limited: 0x41 [23] Hardware or software 0 = hardware implementation [22:16] Subarchitecture version VFP architecture v3 or later with Common VFP subarchitecture v2 0x02 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-5 ID073015 Non-Confidential...
Page 266 = r1p0 = r1p1 = r1p2 = r1p3 = r1p4 a. For information about the Common VFP subarchitecture see the ARM Architecture Reference Manual. 11.3.2 Floating-Point Status and Control Register, FPSCR The FPSCR Register characteristics are: Purpose Provides all necessary User level control of the floating-point system.
Page 267 Underflow cumulative flag, resets to zero Overflow cumulative flag, resets to zero Division by Zero cumulative flag, resets to zero Invalid Operation cumulative flag, resets to zero ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-7 ID073015 Non-Confidential...
Page 268 • are accessible in Privileged modes only. • ARM recommends that any software attempting to determine the presence or absence of double-precision floating point hardware support uses the MVFR1 register. Configurations Use this register if the device is configured as a Cortex-R4F processor.
Page 269 Bits Name Function [31:20] Reserved [19:16] Single-precision floating-point operations supported for VFP: = not supported 0b0000 [15:12] Integer operations supported for VFP: = not supported 0b0000 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-9 ID073015 Non-Confidential...
Page 270 Load and store instructions supported for VFP: = not supported 0b0000 [7:4] Propagation of NaN values supported for VFP: [3:0] Full denormal arithmetic supported for VFP: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-10 ID073015 Non-Confidential...
Page 271: Modes Of Operation
Propagation of the fraction bits is maintained only by , and operations. All other VABS VNEG VMOV operations ignore any information in the fraction bits of an input NaN. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-11 ID073015 Non-Confidential...
Page 272: Compliance With The Ieee 754 Standard
[51] = 1 bits [21:0] are all zeros bits [50:0] are all zeros Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows: • In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference Manual.
Page 273 IEEE 754 standard to generate Underflow exceptions. In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE 754 standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual for information on flush-to-zero mode.
Page 274 You can mask each of these outputs masked by setting the corresponding bit in the Secondary Auxiliary Control Register. c1, Auxiliary Control Register on page 4-40 for more information. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-14 ID073015 Non-Confidential...
Page 275 Cache debug on page 12-53 • External debug interface on page 12-54 • Using the debug functionality on page 12-57 • Debugging systems with energy management capabilities on page 12-74. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-1 ID073015 Non-Confidential...
Page 276: Debug Systems
The debug target is the lowest level of the system. An example of a debug target is a development system with a Cortex-R4 test chip or a silicon part with a Cortex-R4 macrocell. The debug target must implement some system support for the protocol converter to access the processor debug unit using the Advanced Peripheral Bus (APB) slave port.
Page 277: About The Debug Unit
The state of the processor is preserved in the same manner as all ARM exceptions. The monitor target communicates with the debugger to access processor and coprocessor state, and to access memory contents and peripherals. Monitor debug-mode requires a debug monitor program to interface between the debug hardware and the software debugger.
Page 278 Watchpoint Control Registers on page 12-28 • a bidirectional Debug Communication Channel (DCC), see Debug communications channel on page 12-58 • all other state information associated with the debug unit. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-4 ID073015 Non-Confidential...
Page 279: Debug Register Interface
You can access the processor debug register map using the APB slave port. This is the only way to get full access to the processor debug capability. ARM recommends that if your system requires the processor to access its own debug registers, you choose a system interconnect structure that enables the processor to access the APB slave port by executing load and stores to an appropriate area of physical memory.
Page 280 Vector Catch Register on page 12-20 0x01C 0x020 DBGECR Not implemented in this processor. Reads as zero. 0x024 DBGDSCCR Debug State Cache Control Register on page 12-21. 0x028 0x02C c12-c31 0x030-0x07C ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-6 ID073015 Non-Confidential...
Page 281 Processor ID Registers on page 12-35 0xD00 0xDFC c896-c927 0xE00 0xE7C c928-c959 Chapter 13 Integration Test Registers 0xE80 0xEFC c960-c1023 Management registers on page 12-35 0xF00-0xFFC ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-7 ID073015 Non-Confidential...
Page 282 The Vector Catch Register (DBGVCR) sets breakpoints on exception vectors as instruction addresses. The Watchpoint Fault Address Register (DBGWFAR) reads an address and a processor state dependent offset, +8 for ARM and +4 for Thumb. 12.3.6 Power domains The processor has a single power domain. Therefore, it does not support the Event Catch Register, the OS Lock, or the OS Save and Restore functionality.
Page 283 Debug Locks permission You can lock the APB slave port so that access to some debug registers is restricted. ARM architecture v7 defines two locks: Software lock The external debugger can set this lock to prevent software from modifying the debug registers settings.
Page 284: Debug Register Descriptions
CP14 c0, Debug ID Register The DBGDIDR Register characteristics are: Purpose Identifies the debug architecture version and specifies the number of debug resources that the processor implements. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-10 ID073015 Non-Confidential...
Page 285 DBGDIDR[3:0] is the same as CP15 c0 bits [3:0] • DBGDIDR[7:4] is the same as CP15 c0 bits [23:20]. c0, Main ID Register on page 4-14 for more information of CP15 c0, MIDR. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-11 ID073015 Non-Confidential...
Page 286 1 if DBGROMADDR[31:12] is set to a valid value. To use the DBGDRAR Register, read CP14 c0 with: MRC p14, 0, <Rd>, c1, c0, 0 ; Read DBGDRAR Register ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-12 ID073015 Non-Confidential...
Page 287 1 if DBGSELFADDR[31:12] is tied off to a valid value. To use the DBGDSAR Register, read CP14 c0 with: MRC p14, 0, <Rd>, c2, c0, 0 ; Read DBGDSAR Register ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-13 ID073015 Non-Confidential...
Page 288 DBGDTRTX over the CP14 interface. If this bit is set and the processor attempts to write to the DBGDTRTX, the register contents are overwritten and the DTRRXfull flag remains set. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-14 ID073015 Non-Confidential...
Page 289 Non-blocking mode is the default setting. Improper use of the other modes might result in the debug access bus becoming deadlocked. DTR access mode on page 12-18 for more information. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-15 ID073015 Non-Confidential...
Page 290 Some systems rely on DBGACK to determine whether data accesses are application or debugger generated. This bit is 0 on reset. RAZ on reads, SBZP on writes. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-16 ID073015 Non-Confidential...
Page 291 For example, a PRESETDBGn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DBGDSCR[18] to a 0 and DBGDSCR[1:0] to 10. To use the Debug Status and Control Register, read or write CP14 c1 with: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-17 ID073015 Non-Confidential...
Page 292 12.4.6 Data Transfer Register The DTR consists of two separate physical registers: • the DBGDTRRX (Read Data Transfer Register) • the DBGDTRTX (Write Data Transfer Register). ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-18 ID073015 Non-Confidential...
Page 293 Available in all processor configurations. Attributes Table 12-12 on page 12-20. Figure 12-6 shows the DBGWFAR bit assignments. Address Reserved Figure 12-6 DBGWFAR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-19 ID073015 Non-Confidential...
Page 294 Function [31:1] Address This is the address of the watchpointed instruction. When a watchpoint occurs in ARM state, the DBGWFAR contains the address of the instruction causing it plus an offset of . When a watchpoint occurs in Thumb state, the offset is plus RAZ.
Page 295 Instruction cache line-fill Data cache line-fill Figure 12-8 DBGDSCCR Register bit assignments For information on the usage model of the DBGDSCCR register, see Cache debug on page 12-53. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-21 ID073015 Non-Confidential...
Page 296 The DBGITR is a write-only register. Reads from the DBGITR return an Unpredictable value. The Instruction Transfer Register, bits [31:0] contain the ARM instruction for the processor to execute while in debug state. The reset value of this register is Unpredictable.
Page 297 DBGBVRy. A pair of breakpoint registers, DBGBVRy/DBGBCRy, is called a Breakpoint Register Pair (BRP). DBGBVR0-7 are paired with DBGBCR0-7 to make BRP0-7. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-23 ID073015 Non-Confidential...
Page 298 5 4 3 2 1 0 Byte Breakpoint Linked BRP Reserved address address mask select Reserved Reserved Secure state access control Reserved Figure 12-10 DBGBCR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-24 ID073015 Non-Confidential...
Page 299 Unpredictable whether a breakpoint debug event is generated. [15:14] Secure state RAZ or SBZP. access control [13:9] Do not modify on writes. On reads, the value returns zero. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-25 ID073015 Non-Confidential...
Page 300 DBGBCR[22] to 1 and DBGBCR[8:5] to b0000. b. Writing a value to DBGBCR[8:5] so that DBGBCR[8] is not equal to DBGBCR[7] or DBGBCR[6] is not equal to DBGBCR[5] has Unpredictable results. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-26 ID073015 Non-Confidential...
Page 301 For a data address and context ID pair, a WRP and a BRP with context ID comparison capability must be linked. A debug event is generated when both the data address and the context ID pair match simultaneously. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-27 ID073015 Non-Confidential...
Page 302 21 20 19 16 15 14 13 Watchpoint Linked BRP Byte address select address mask Reserved Reserved Reserved Secure state access control Figure 12-11 DBGWCR Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-28 ID073015 Non-Confidential...
Page 303 Unpredictable. • To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a debugger sets DBGWCR[28:24] to b00111, and DBGWCR[12:5] to b11111111. This is compatible with both ARMv7 debug compliant implementations that have an 8-bit DBGWCR[12:5] and with those that have a 4-bit DBGWCR[8:5] byte address select field.
Page 304 12.4.16 Operating System Lock Status Register The DBGOSLSR contains status information about the locked debug registers. Figure 12-12 on page 12-31 shows the DBGOSLSR bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-30 ID073015 Non-Confidential...
Page 305 Table 12-22 DBGAUTHSTATUS Register bit assignments Bits Name Value Function [31:8] Secure non-invasive debug Implemented features implemented Secure non-invasive debug DBGEN || NIDEN Non-invasive debug enable field features enabled ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-31 ID073015 Non-Confidential...
Page 306 Invasive debug enable field features enabled [3:0] Not implemented Non-secure debug features a. Cortex-R4 does not implement the Security Extensions, so all the debug features are considered secure. 12.4.18 Device Power-down and Reset Control Register The DBGPRCR Register characteristics are: Purpose Controls reset and power-down related functionality.
Page 307 Sticky reset status Reset status Sticky power-down status Power-down status Figure 12-15 DBGPRSR Register bit assignments Table 12-24 on page 12-34 shows the DBGPRSR bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-33 ID073015 Non-Confidential...
Page 308 0 = the processor is not held in reset 1 = the processor is held in reset. Sticky power-down status Reserved. Always zero. Power-down status Reserved. Always one. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-34 ID073015 Non-Confidential...
Page 309: Management Registers
Table 12-26 Processor Identification Registers Offset (hex) Register number Mnemonic Function MIDR Main ID Register 0xD00 Cache Type Register 0xD04 TCMTR TCM Type Register 0xD08 Alias of MIDR 0xD0C ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-35 ID073015 Non-Confidential...
Page 310 0 to a CLAIM bit has no effect. Configurations Available in all processor configurations. Attributes Table 12-27 on page 12-37. Figure 12-16 on page 12-37 shows the DBGCLAIMSET bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-36 ID073015 Non-Confidential...
Page 311 Writing b1 to a specific claim tag clear bit clears that claim tag. Writing b0 has no effect. Reading this register returns the claim tag value. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-37 ID073015 Non-Confidential...
Page 312 Indicates that the OS lock functionality is implemented. This bit always reads 1. 12.5.5 Device Type Register The DBGDEVTYPE Register characteristics are: Purpose Indicates the type of debug component. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-38 ID073015 Non-Confidential...
Page 313 Reserved 0xFDC 1016 Peripheral Identification Register 0 0xFE0 1017 Peripheral Identification Register 1 0xFE4 1018 Peripheral Identification Register 2 0xFE8 1019 Peripheral Identification Register 3 0xFEC ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-39 ID073015 Non-Confidential...
Page 314 4 bits Indicates the manufacturer revision number. This number starts at and increments by the integrated circuit manufacturer on metal fixes. For the Cortex-R4 processor, the initial value is but this value can be changed by the manufacturer. Customer 4 bits Indicates an endorsed modification to the device.
Page 315 Component Identification Register 0 0xFF0 0x0D 1021 Component Identification Register 1 0xFF4 0x90 1022 Component Identification Register 2 0xFF8 0x05 1023 Component Identification Register 3 0xFFC 0xB1 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-41 ID073015 Non-Confidential...
Page 316: Debug Events
— The instruction is committed for execution. These debug events are generated whether the instruction passes or fails its condition code. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-42 ID073015 Non-Confidential...
Page 317 If the watchpointed access is subject to a synchronous data abort, then the synchronous abort takes priority over the watchpoint because it is a higher priority exception. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-43 ID073015...
Page 318: Debug Exception
Debug exception or other kind of Data Abort exception. If the cause is a Debug exception, the Data Abort handler must branch to the debug monitor. The R14_abt register holds the address of the instruction to restart. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-44 ID073015 Non-Confidential...
Page 319 The processor ignores vector catch debug events on the Prefetch or Data Abort vectors while in Monitor debug-mode because these events would otherwise put the processor in an unrecoverable state. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-45 ID073015 Non-Confidential...
Page 320 Failure to follow these guidelines can lead to debug events occurring before the handler is able to save the context of the abort. This causes the corresponding registers to be overwritten, and results in Unpredictable software behavior. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-46 ID073015 Non-Confidential...
Page 321: Debug State
Address of the instruction where the execution resumes. This is several instructions after the one that hit the watchpoint. instruction RA+8 RA+4 instruction address. BKPT BKPT ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-47 ID073015 Non-Confidential...
Page 322 • The PC is frozen on entry to debug state. That is, it does not increment on the execution of ARM instructions. However, the processor still updates the PC as a response to instructions that explicitly modify the PC. •...
Page 323 While the processor is in debug state, it always decodes instructions from the DBGITR as per the ARM instruction set, regardless of the value of the T and J bits of the CPSR. The following restrictions apply to instructions executed through the DBGITR while in debug state: •...
Page 324: Coprocessor Instructions
• PC, CPSR, SPSR_und, and R14_und are unchanged • the processor remains in debug state • DBGDSCR[8], sticky Undefined bit, is set. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-50 ID073015 Non-Confidential...
Page 325 CPSR. The CPSR IT execution state bit is restarted with the value applying to the first instruction on restart. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-51 ID073015...
Page 327: Cache Debug
You can obtain cache usage profiling information using the Performance Monitoring Unit (PMU). The processor can count cache accesses and misses over a period of time. See Chapter 6 Events and Performance Monitor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-53 ID073015 Non-Confidential...
Page 328: External Debug Interface
DBGROMADDR must be tied off to zero and DBGROMADDRV must be tied LOW. The value of these signals can be read from CP14 c0, Debug ROM Address Register on page 12-12. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-54 ID073015 Non-Confidential...
Page 329 LOW. Changing the authentication signals The NIDEN, and DBGEN input signals are either tied off to some fixed value or controlled by some external device. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-55 ID073015 Non-Confidential...
Page 330 DBGITR while in debug state. The values of the DBGEN and NIDEN signals can be determined by polling DBGDSCR[17:16], DBGDSCR[15:14], or the Authentication Status Register. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-56 ID073015 Non-Confidential...
Page 331: Using The Debug Functionality
This section provides some examples of using the processor debug functionality, both from the point of view of a software engineer writing code to run on an ARM processor and of a developer creating debug tools for the processor. In the former case, examples are given in ARM assembly language.
Page 332 • The mechanism for forcing the processor to execute ARM instructions, when the processor is in debug state. For more information, see Executing instructions in debug state on page 12-49.
Page 333 (dscr & (1<<29)); // Step 2. Read the value from DBGDTRTX. dtr_val := ReadDebugRegister(35); return dtr_val; Example 12-5 on page 12-60 shows the code for host-to-target data transfer. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-59 ID073015 Non-Confidential...
Page 334 Programming simple breakpoints and the byte address select When programming a simple breakpoint, you must set the byte address select bits in the control register appropriately. For a breakpoint in ARM state, this is simple. For Thumb state, you must calculate the value based on the address.
Page 335 In practice, a data object spans a range of addresses but is aligned to a boundary corresponding to its size, so you must set the byte address select bits in the same way as for a breakpoint. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-61 ID073015 Non-Confidential...
Page 336 Using the byte address select bits, certain unaligned objects up to a doubleword (64 bits) can be watched in a single watchpoint. However, this cannot cover all cases, and in many cases a second watchpoint might be required. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-62 ID073015 Non-Confidential...
Page 337 With high-level stepping, the instruction is decoded to determine the address of the next instruction and a breakpoint is set at that address. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-63 ID073015...
Page 338 // Step 1. Read the DBGDSCR to determine the cause of debug entry. state->dscr := ReadDebugRegister(34); // Step 2. Issue a DataSynchronizationBarrier instruction if required; // this is not required by Cortex-R4 but is required for ARMv7 // debug. if ((state->dscr & (1<<19)) == 0) ExecuteARMInstruction(0xEE070F9A) // Step 3.
Page 339 // set the T bit to Thumb state state->pc := state->pc - 4; elseif (state->cpsr & (1<<24)) // Set the J bit to Jazelle state. Note: ARM Cortex-R4 does not support // Jazelle state but ARMv7 debug does. state->pc := state->pc - IMPLEMENTATION DEFINED value;...
Page 340 // Step 2. Read the register value through DBGDTRTX. reg_val := ReadDCC(); return reg_val; Example 12-14 shows a similar sequence for writing an ARM register. Example 12-14 Writing an ARM register WriteRegister(int Rd, uint32 reg_val) // Step 1. Write the register value to DBGDTRRX.
Page 341 := ReadRegister(0); // Step 4. Restore the value of R0. WriteRegister(0, saved_r0); return cpsr_val; Note You can use similar sequences to read the SPSR in Privileged modes. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-67 ID073015 Non-Confidential...
Page 342 // Step 1. Check the DBGDSCR for a sticky abort. dscr := ReadDebugRegister(34); if (dscr & ((1<<6) + (1<<7)) // Step 2. Clear the sticky flag by writing DBGDRCR[2]. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-68 ID073015 Non-Confidential...
Page 343 A faster method is available for reading and writing words using the direct memory access function of the DCC. See Fast memory read/write on page 12-71. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-69 ID073015 Non-Confidential...
Page 344 // Step 2. Read the register value through the DCC. Read stalls until // DBGDTRTX is ready reg_val := ReadDebugRegister(32); return reg_val; Example 12-24 on page 12-71 shows the sequence to write registers in stall mode. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-70 ID073015 Non-Confidential...
Page 345 // Step 8. Need to wait for the final instruction to complete. If there // was an abort, this completes immediately. dscr := ReadDebugRegister(34); until (dscr & (1<<24)); ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-71 ID073015 Non-Confidential...
Page 346 Accessing coprocessor registers The sequence for accessing coprocessor registers is the same for the PC and CPSR. That is, you must first execute an instruction to transfer the register to an ARM register, then read the value back through the DTR.
Page 347 // Step 3. Read the value of R0 that now contains the CP register. CP15c1 := ReadRegister(0); // Step 4. Restore the value of R0. WriteRegister(0, saved_r0); return CP15c1; ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-73 ID073015 Non-Confidential...
Page 348: Debugging Systems With Energy Management Capabilities
• The emulation does not model state lost during power down, making it possible to miss errors in the state storage and recovery routines. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-74 ID073015 Non-Confidential...
Page 349 DBGNOPWRDWN signal to 1 might not cause the processor to power up. The effect of setting DBGNOPWRDWN to 1 when the processor is already powered down is implementation-defined, and is up to the system designer. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-75 ID073015 Non-Confidential...
Page 350 About Integration Test Registers on page 13-2 • Summary of the processor registers used for integration testing on page 13-3 • Processor integration testing on page 13-4. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-1 ID073015 Non-Confidential...
Page 351: About Integration Test Registers
When programming the Integration Test Registers you must enable all the changes at the same time. For more information about the Integration Test Registers and the Integration Mode Control Register, see the ARM Architecture Reference Manual. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-2 ID073015 Non-Confidential...
Page 352: Summary Of The Processor Registers Used For Integration Testing
0xEFC Inputs) on page 13-7 Integration Mode Control Register DBGITCTRL 0xF00 Integration Mode Control Register on page 13-8 a. See the register description for this value. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-3 ID073015 Non-Confidential...
Page 353: Processor Integration Testing
This section describes the behavior and use of the Integration Test Registers that are in the processor. It also describes the Integration Mode Control Register that controls the use of the Integration Test Registers. For more information about the DBGITCTRL, see the ARM Architecture Reference Manual.
Page 354 • ARM strongly recommends that the processor is halted while in debug state, because toggling input and output pins might have an unwanted effect on the operation of the processor. You must not set the DBGITCTRL Register until the processor has halted.
Page 355 Set value of the ETMIA[1] output pin. ETMICTL[13] Set value of the ETMICTL[13] output pin. ETMICTL[0] Set value of the ETMICTL[0] output pin. a. Not available on r0px revisions of the processor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-6 ID073015 Non-Confidential...
Page 356 Set value of the DBGACK output pin. 13.3.5 DBGITMISCIN Register (Miscellaneous Inputs) The DBGITMISCIN Register at offset is read-only. Figure 13-3 on page 13-8 shows the OxEFC register bit assignments. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-7 ID073015 Non-Confidential...
Page 357 The DBGITCTRL Register, register at offset , is read/write. Figure 13-4 shows the 0x3C0 0xF00 register bit assignments. Reserved INTMODE Figure 13-4 DBGITCTRL Register bit assignments ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-8 ID073015 Non-Confidential...
Page 359: Signal Descriptions
ETM interface signals on page A-19 • Test signals on page A-20 • MBIST signals on page A-21 • Validation signals on page A-22 • FPU signals on page A-23. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 360: About The Processor Signal Descriptions
Reset Means the input must only be changed under reset. Clocking is listed for all outputs, though some are typically synchronized into a different clock before use. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 361: Global Signals
Indicates that the processor is in Standby mode and the processor clock is stopped. You can use this signal for TCMs RAM clock gating. a. Not available in r0px revisions of the processor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 362: Configuration Signals
= 32KB b0111 = 64KB b1000 = 128KB b1001 = 256KB b1010 = 512KB b1011 = 1MB b1100 = 2MB b1101 = 4MB b1110 = 8MB. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 363 Selects between odd and even parity for caches, TCMs, and Reset buses. See Chapter 8 Level One Memory System: Tie LOW for even parity Tie HIGH for odd parity. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 364 If the BTCM is configured with ECC, bit[2] and bit[1] must be the same value. b. Not used if 32-bit ECC is included. c. Not available in r0px revisions of the processor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 365: Interrupt Signals, Including Vic Interface Signals
This signal is level-sensitive and must be held LOW until a suitable interrupt response is received from the processor. d. When IRQADDRVSYNCEN is tied LOW. e. When IRQADDRVSYCNEN is tied HIGH. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 366: L2 Interface Signals
Protection type. Only bit [0] is used from the 3-bit AXI bus. AWREADYM Input CLKIN Address ready. The slave uses this signal to indicate that it can accept the address. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 367 Identification tag for the read address group of signals ARLENM [3:0] Output CLKIN Instruction fetch burst length. ARLOCKM[1:0] Output CLKIN Lock signal. ARPROTM[2:0] Output CLKIN Protection signals provide addition information about a bus access. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 368 Parity bit for read address channel RPARITYM Input CLKIN Parity bit for read data channel AXIMPARERR[1:0] Output CLKIN Parity error indication for read data, bit [1], and write response, bit[0], channels ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-10 ID073015 Non-Confidential...
Page 369 Read Address Channel ARADDRS[22:0] Input CLKIN Instruction fetch burst start address. ARBURSTS[1:0] Input CLKIN Burst type. ARIDS[7:0] Input CLKIN Identification tag for the read address group of signals. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-11 ID073015 Non-Confidential...
Page 370 Parity bit for read data channel AXISPARERR[2:0] Output CLKIN Parity error indication for read address, bit [2], write data, bit [1], and write address, bit [0], channels. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-12 ID073015 Non-Confidential...
Page 371: Tcm Interface Signals
Data from B0TCM B0TCPARITYIN [13:0] Input CLKIN Parity or ECC code from B0TCM B0TCERROR Input CLKIN Error detected by B0TCM B0TCWAIT Input CLKIN Wait from B0TCM ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-13 ID073015 Non-Confidential...
Page 372 Write enable for B1TCM B1TCEN0 Output CLKIN Enable for B1TCM lower word, bit range [31:0] B1TCEN1 Output CLKIN Enable for B1TCM upper word, bit range [64:32] ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-14 ID073015 Non-Confidential...
Page 373 The MBIST interface has no way of signaling a wait. If it is accessing the TCM, and the TCM signals a wait, the AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to indicate this. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-15 ID073015 Non-Confidential...
Page 374: Redundant Processor Signals
Dual core compare logic extra input control bus DCCMOUT2[7:0] Output Dual core compare logic extra output control bus a. Implementation-defined. b. Not available in r0px revisions of the processor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-16 ID073015 Non-Confidential...
Page 375: Debug Interface Signals
DBGDTRTX empty DBGRESTART Input External restart request DBGRESTARTED Output CLKIN Handshake for DBGRESTART DBGNOPWRDWN Output PCLKDBG No power-down request DBGROMADDR[31:12] Input Tie-off Debug ROM physical address ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-17 ID073015 Non-Confidential...
Page 376 Debug ROM physical address valid DBGSELFADDR[31:12] Input Tie-off Debug self-address offset DBGSELFADDRV Input Tie-off Debug self-address offset valid a. Not available in r0px revisions of the processor. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-18 ID073015 Non-Confidential...
Page 377: Etm Interface Signals
Performance monitor unit output ETMPWRUP Input CLKIN Power up ETM interface nETMWFIREADY Input CLKIN ETM FIFO is empty, core can enter WFI state ETMEXTOUT[1:0] Input CLKIN ETM detected events ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-19 ID073015 Non-Confidential...
Page 378: Test Signals
Table A-15 shows the test signals. Table A-15 Test signals Signal Direction Clocking Description Input Scan Enable RSTBYPASS Input Bypass pipelined reset a. Design for test only. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-20 ID073015 Non-Confidential...
Page 379: Mbist Signals
MBIST address MBISTCE Input CLKIN MBIST chip enable MBISTSEL[4:0] Input CLKIN MBIST chip select MBISTWE [7:0] Input CLKIN MBIST write enable MBISTDOUT[77:0] Output CLKIN MBIST data out ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-21 ID073015 Non-Confidential...
Page 380: Validation Signals
Output CLKIN Debug request nVALIRQ Output CLKIN Request for an interrupt nVALFIQ Output CLKIN Request for a Fast Interrupt nVALRESET Output CLKIN Request for a reset ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-22 ID073015 Non-Confidential...
Page 381: Fpu Signals
Masked floating-point underflow exception FPIOC Output CLKIN Masked floating-point invalid operation exception FPDZC Output CLKIN Masked floating-point divide-by-zero exception FPIDC Output CLKIN Masked floating-point input denormal exception ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-23 ID073015 Non-Confidential...
Page 382: Processor Timing
This chapter gives the timing parameters for the processor. It contains the following sections: • Processor timing on page B-2 • Processor timing parameters on page B-3. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 383 The APB debug interface of the processor conforms to the AMBA 3 APB Protocol Specification. For the relevant timing of the APB write and read transfers, and the error response, see the AMBA 3 APB Protocol Specification. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 384: Processor Timing Parameters
Clock uncertainty INITRAMA Clock uncertainty INITRAMB Clock uncertainty LOCZRAMA Clock uncertainty TEINIT Clock uncertainty CFGNMFI Clock uncertainty CFGATCMSZ[3:0] Clock uncertainty CFGBTCMSZ[3:0] Clock uncertainty PARECCENRAM[2:0] Clock uncertainty ERRENRAM[2:0] ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 385 Clock uncertainty WREADYM Clock uncertainty BIDM[3:0] Clock uncertainty BRESPM[1:0] Clock uncertainty BVALIDM Clock uncertainty ARREADYM Clock uncertainty RIDM[3:0] Clock uncertainty RDATAM[63:0] Clock uncertainty RRESPM[1:0] Clock uncertainty RLASTM ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 386 Clock uncertainty ARIDS[7:0] Clock uncertainty ARADDRS[22:0] Clock uncertainty ARLENS[3:0] Clock uncertainty ARSIZES[2:0] Clock uncertainty ARBURSTS[1:0] Clock uncertainty ARPROTS Clock uncertainty ARUSERS[3:0] Clock uncertainty ARVALIDS Clock uncertainty RREADYS ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 387 ETM input ports. Table B-7 ETM input ports timing parameters Input delay Input delay Signal name minimum maximum Clock uncertainty ETMPWRUP Clock uncertainty nETMWFIREADY Clock uncertainty ETMEXTOUT[1:0] ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 388 Clock uncertainty B0TCDATAIN[63:0] Clock uncertainty B0TCPARITYIN[13:0] Clock uncertainty B0TCERROR Clock uncertainty B0TCWAIT Clock uncertainty B0TCLATEERROR Clock uncertainty B0TCRETRY Clock uncertainty B1TCDATAIN[63:0] Clock uncertainty B1TCPARITYIN[13:0] Clock uncertainty B1TCERROR ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 389 Output delay Signal name minimum maximum Clock uncertainty AWIDM[3:0] Clock uncertainty AWADDRM[31:0] Clock uncertainty AWLENM[3:0] Clock uncertainty AWSIZEM[2:0] Clock uncertainty AWBURSTM[1:0] Clock uncertainty AWLOCKM[1:0] Clock uncertainty AWCACHEM[3:0] ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 390 AXI slave output ports. Table B-13 AXI slave output ports timing parameters Output delay Output delay Signal name minimum maximum Clock uncertainty AWREADYS Clock uncertainty WREADYS Clock uncertainty BIDS[7:0] ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 391 Clock uncertainty PREADYDBG Clock uncertainty PSLVERRDBG Clock uncertainty DBGNOPWRDWN Clock uncertainty DBGACK Clock uncertainty DBGTRIGGER Clock uncertainty DBGRESTARTED Clock uncertainty DBGRSTREQ Clock uncertainty COMMTX Clock uncertainty COMMRX ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-10 ID073015 Non-Confidential...
Page 392 Clock uncertainty ATCEN0 Clock uncertainty ATCEN1 Clock uncertainty ATCADDR[22:3] Clock uncertainty ATCBYTEWR[7:0] Clock uncertainty ATCSEQ Clock uncertainty ATCDATAOUT[63:0] Clock uncertainty ATCPARITYOUT[13:0] Clock uncertainty ATCACCTYPE[2:0] Clock uncertainty ATCWE ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-11 ID073015 Non-Confidential...
Page 393 Output delay Output delay Signal name minimum maximum Clock uncertainty FPIXC Clock uncertainty FPOFC Clock uncertainty FPUFC Clock uncertainty FPIOC Clock uncertainty FPDZC Clock uncertainty FPIDC ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-12 ID073015 Non-Confidential...
Page 394 The timing parameters for the dual-redundant core compare logic output buses, DCCMOUT[7:0] and DCCMOUT2[7:0], are implementation-defined. Contact the implementer of the macrocell you are working with. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-13 ID073015 Non-Confidential...
Page 395 Miscellaneous instructions on page C-28 • Floating-point register transfer instructions on page C-29 • Floating-point load/store instructions on page C-30 • Floating-point single-precision data processing instructions on page C-32 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 396 Cycle Timings and Interlock Behavior • Floating-point double-precision data processing instructions on page C-33 • Dual issue on page C-34. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 397: About Cycle Timings And Interlock Behavior
Instructions that require a register at the end of these stages are specified by describing that register as an Early Reg. The following sequence, requiring an Early Reg, takes four cycles: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 398 Late Reg The specified registers are not required until the start of the Wr stage. Subtract one cycle from the Result Latency of the instruction producing this register. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 399 C.1.5 Assembler language syntax The syntax used throughout this chapter is unified assembler and the timings apply to ARM and Thumb instructions. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved.
Page 400: Register Interlock Examples
Takes four cycles because of the result latency of R1, the use of the result of R1 as a Very Early Reg, LDR R1, [R2] LDR R5, [R1] and the use of an LDR to generate R1. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 401: Data Processing Instructions
Requires a shifted source register ADD pc, <Rn>, <Rm>, LSL #<immed> <Rm> > Requires a register controlled shifted ADD pc, <Rn>, <Rm>, LSL <Rs <Rm> source register <Rs> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 402 The register containing the shift distance is an Early Reg. For example, the following sequence takes three cycles to execute: ADD R1, R2, R3 ADD R4, R2, R4, LSL R1 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 403: Qadd, Qdadd, Qsub, And Qdsub Instructions
QADD QDADD QSUB QDSUB Table C-5 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior Instructions Cycles Early Reg Result latency QADD QSUB QDADD QDSUB <Rn> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 404: Media Data-Processing
QSAX SHASX SHSAX UQASX UQSAX UHASX UHSAX <Rd> SBFX UBFX <Rn> <Rd>, <Rn> a. A shift of zero makes a Normal Reg for these instructions. <Rm> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-10 ID073015 Non-Confidential...
Page 405: Sum Of Absolute Differences (Sad)
Takes two cycles. The Result Latency is one less because the result is used as the USAD8 R1,R2,R3 USADA8 R1,R4,R5,R1 accumulate for a subsequent instruction. USADA8 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-11 ID073015 Non-Confidential...
Page 406: Multiplies
<Rn>, <Rm> SMLAD SMLADX <Rn>, <Rm> SMUSD SMUSDX <Rn>, <Rm> SMLSD SMLSDX <Rn>, <Rm> SMMUL SMMULR <Rn>, <Rm> SMMLA SMMLAR <Ra> <Rn>, <Rm> SMMLS SMMLSR <Ra> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-12 ID073015 Non-Confidential...
Page 407 Result Latency is one less if the result is used as the accumulate value for a subsequent multiply accumulate. This only applies if the result is the same width as the accumulate value, that is 32 or 64 bits. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-13 ID073015 Non-Confidential...
Page 408: Divide
• The clz(x) function counts the number of leading zeros in the 32-bit value x. If x is negative, it is negated before this count occurs. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-14 ID073015 Non-Confidential...
Page 409: Branches
Condition code fails TBH [<Rn>, <Rm>, LSL#1] Condition code passes a. Return stack push. b. Return stack pop, if condition passes. are Very Early Regs. <Rn> <Rm> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-15 ID073015 Non-Confidential...
Page 410: Processor State Updating Instructions
All other instructions to the CPSR instructions to the SPSR MSR SPSR Interrupt masks only CPS <effect> <iflags> Mode changing CPS <effect> <iflags>, #<mode> SETEND ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-16 ID073015 Non-Confidential...
Page 411: Single Load And Store Instructions
LDR pc, [sp, #<imm>] (!) predicted correctly LDR pc, [sp], #<imm> Return stack mispredicted, conditional LDR pc, [sp, #<imm>] (!) predicted correctly LDR pc, [sp], #<imm> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-17 ID073015 Non-Confidential...
Page 412 For example, with aligned the following instruction sequence take three cycles to execute: ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-18 ID073015 Non-Confidential...
Page 413 Cycle Timings and Interlock Behavior LDR R5, [R2, #4]! LDR R6, [R2, #0X10]! LDR R7, [R2, #0X20]! ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-19 ID073015 Non-Confidential...
Page 414: Load And Store Double Instructions
LDRD <Rt>, <Rt2>, [<Rn>], +/-<Rm> <Rn>, <Rm> <addr_md_3cycle> If pre-increment addressing with a negative LDRD <Rt>, <Rt2>, [<Rn>, -<Rm>] (!) <Rn>,<Rm> register offset, then 3-issue cycles ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-20 ID073015 Non-Confidential...
Page 415: Load And Store Multiple Instructions
LDMIA <Rn>,{R1,R2,R3,R4,R5,R6,R7} Note The Cycle timing behavior that Table C-17 shows also covers instructions that PUSH behave like store and load multiple instructions with base register write-back. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-21 ID073015 Non-Confidential...
Page 416 POP {R1-R9} ADD R10, R10, R9 The following sequence that has a PUSH instruction takes five cycles to execute: PUSH {R1-R7} ADD R10,R10,R7 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-22 ID073015 Non-Confidential...
Page 417 Cycle Timings and Interlock Behavior Note In the examples, R0 and are 64-bit aligned addresses. The instructions always PUSH use the register for the base address. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-23 ID073015 Non-Confidential...
Page 418: Rfe And Srs Instructions
Table C-19 RFE and SRS instructions cycle timing behavior Example instruction Cycles Memory cycles Address doubleword aligned RFEIA <Rn> SRSIA #<mode> Address not doubleword aligned RFEIA <Rn> SRSIA #<mode> ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-24 ID073015 Non-Confidential...
Page 419: Synchronization Instructions
Address must be 64-bit aligned. The synchronization instructions , and stall the pipeline for a variable number of cycles, depending on the current state of the memory system. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-25 ID073015 Non-Confidential...
Page 420: Coprocessor Instructions
Condition code passes MCR <cond> Condition code fails Condition code passes MRC <cond> Condition code fails Note Some instructions such as cache operations take more cycles. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-26 ID073015 Non-Confidential...
Page 421: Svc, Bkpt, Undefined, And Prefetch Aborted Instructions
Undefined, prefetch aborted instructions cycle timing behavior. Table C-22 SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior Instruction Cycles (formerly BKPT Prefetch Abort Undefined Instruction ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-27 ID073015 Non-Confidential...
Page 422: Miscellaneous Instructions
, and so have the same YIELD cycle timing behavior. instruction stalls the pipeline for a variable number of cycles, depending on the current state of the memory system. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-28 ID073015 Non-Confidential...
Page 423 VMOV <Rt>, <Rt2>, <Sm>, <Sm1> VMOV <Dm>, <Rt>, <Rt2> VMOV <Rt>, <Rt2>, <Dm> Blocking and serializing VMSR <spec_reg>, <Rt> Serializing VMRS <Rt>, <spec_reg> Serializing VMRS APSR_nzcv, FPSCR ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-29 ID073015 Non-Confidential...
Page 424 VLDM{mode}.32 <Rn>{!}, {s1} VLDM{mode}.32 <Rn>{!}, {s1,s2} 1,1,2 VLDM{mode}.32 <Rn>{!}, {s1-s3} 1,1,2,2 VLDM{mode}.32 <Rn>{!}, {s1-s4} VLDM{mode}.64 <Rn>{!}, {d1} VLDM{mode}.64 <Rn>{!}, {d1,d2} 1,2,3 VLDM{mode}.64 <Rn>{!}, {d1-d3} 1,2,3,4 VLDM{mode}.64 <Rn>{!}, {d1-d4} ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-30 ID073015 Non-Confidential...
Page 425 VLDM{mode}.32 <Rn>{!}, {s1} VLDM{mode}.32 <Rn>{!}, {s1,s2} 1,2,2 VLDM{mode}.32 <Rn>{!}, {s1-s3} 1,2,2,3 VLDM{mode}.32 <Rn>{!}, {s1-s4} VLDM{mode}.64 <Rn>{!}, {d1} VLDM{mode}.64 <Rn>{!}, {d1,d2} 2,3,4 VLDM{mode}.64 <Rn>{!}, {d1-d3} 2,3,4,5 VLDM{mode}.64 <Rn>{!}, {d1-d4} ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-31 ID073015 Non-Confidential...
Page 426 Also VCMPE.F32 g. Also VCVT.F32.S32 h. Also , and VCVT.F32.U16 VCVT.F32.S32 VCVT.F32.S16 i. Also , and VCVT.U32.F32 VCVTR.S32.F32 VCVT.S32.F32 j. Also , and VCVT.U16.F32 VCVT.S32.F32 VCVT.S16.F32 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-32 ID073015 Non-Confidential...
Page 427 Also VCMPE.F64 e. Also VCVT.F64.S32 f. Also , and VCVT.F64.U16 VCVT.F64.S32 VCVT.F64.S16 g. Also , and VCVT.U32.F64 VCVTR.S32.F64 VCVT.S32.F64 h. Also , and VCVT.U16.F64 VCVT.S32.F64 VCVT.S16.F64 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-33 ID073015 Non-Confidential...
Page 428: C.23 Dual Issue C
The first instruction must not use the PC as a destination register. • Both instructions must belong to the same instruction set, ARM or Thumb. • There must be no data dependency between the two instructions. That is, the second instruction must not have any source registers that are destination registers of the first instruction.
Page 429 As for case C or C-F. Case F1 Any single-precision , excluding "VMOV.S32 <Sd>, , and #<imm>" VCVT.F64.F32 VABS.F32 VNEG.F32 As for Case B1 or Case B1-F Case F2_ld VLDR.F32 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-35 ID073015 Non-Confidential...
Page 430 Single-precision floating-point multiply-accumulate instructions are , and VMLA.F32 VMLS.F32 VNMLS.F32 VNMLA.F32 p. Multi-cycle multiply instructions are , and SMMUL SMMLA SMMLS SMULL SMLAL UMAAL UMULL UMLAL ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-36 ID073015 Non-Confidential...
Page 431 This appendix describes some of the advantages and disadvantages of the different Error Checking and Correction (ECC) schemes for the TCMs. It contains the following section: • ECC scheme selection guidelines on page D-2. ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 432 ECC Schemes ECC scheme selection guidelines When deciding to implement a Cortex-R4 processor with an ECC scheme on one or both of the TCM interfaces, give careful consideration between using 32-bit or 64-bit ECC. To calculate or check the ECC code for data, the processor must know the value of all bytes in the data chunk protected by the scheme.
Page 433 Little-endian format on page 3-4 nCPUHALT removed from timing diagram Figure 4-1 on page 4-2 Added sections • AMBA interface clocking on page 2-13 • Clock gating on page 2-13 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 434 Dormant mode on page 10-3 Updated the permitted instruction combinations Table C-28 on page C-35 Updated the descriptions for COMMRX and COMMTX signals Table A-13 on page A-17 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...
Page 435 12-60. PollDCC() Updated reset value of MVFR1 Table 11-1 on page 11-4. Updated instruction descriptions to comply with the ARM Appendix C Cycle Timings and Interlock Architecture Reference Manual. Behavior. Clarified configuration signal descriptions and added references Table A-2 on page A-4.
Page 436 Remove Programming and reading Integration Test Registers Chapter 13 Integration Test Registers Update description of ATCEN1 signal Table A-6 on page A-11 Update description of COMMRX and COMMTX Table A-13 on page A-17 ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ID073015 Non-Confidential...

This manual is also suitable for:

Cortex-r4f

ARM Cortex-R4 Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Functional Description

Chapter 3 Programmers Model

Chapter 4 System Control

Chapter 5 Prefetch Unit

Chapter 6 Events and Performance Monitor

Chapter 7 Memory Protection Unit

Chapter 8 Level One Memory System

Chapter 9 Level Two Interface

Chapter 10 Power Control

Chapter 11 FPU Programmers Model

Chapter 12 Debug

Chapter 13 Integration Test Registers

Signal Descriptions

Appendix A Signal Descriptions

Appendix B AC Characteristics

Appendix C Cycle Timings and Interlock Behavior

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Summary of Contents for ARM Cortex-R4