Preview Logic Board Block Diagram - HP PageWriter XL M1705B Service Manual

Preview Loclic Board
The preview logic assembly is diagrammed in Figure 5-13. The
buffers reduce loading on the CPU address, data, and system control
lines and ensure proper logic levels and transitions for the preview
logic circuitry.
The address decoder determines whether the system has access to the
LCD static RAM (SRAM) or the LCD controller. Upon recognition
of the proper addresses, the decoder generates control signals that
provide the following:
n
read/write access to the LCD bit map stored in static RAM
(SRAM) for display data reads and ,writes.
H write-only access to the LCD controller's internal control registers
for I/O register writes (usually done at system initialization).
The SRAM address bus can be driven by the CPU or by the LCD
controller. The address multiplexers, under the control of the LCD
controller, select between these two address sources. In the event of
contention, the LCD controller forces the CPU to wait for access to
the RAM.
DATA
-I/
CONTROLS
CONTROLL& ADDRESS 16,
I I
I
I
I I I I
- I I
LCDON
+5 READ-
Figure 5-13. Preview Logic Board Block Diagram.
Theory of Operation 5-25