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Preface
With the recent advent of home video-game machines that offer a fast, responsive man-machine
interface and high-resolution graphics at a low price, there is a demand for a similar revolution in
graphics quality in the entire home information market, covering such products as car navigation
systems and Internet TVs.
In addition to the need for a powerful and simple means of handling the necessary processing, there
are growing demands for the preservation of upward-compatibility of software and data bases. At
the same time, there is the question of how best to handle the increasingly complex graphics
algorithms required for these applications.
The approach to graphics processing up to now has been to have both geometrical processing and
rendering processing carried out by the CPU, using large amounts of high-speed memory, or to use
a graphics LSI containing as many embedded algorithms as possible at that time. A more desirable
approach, however, is to have geometrical processing handled by the CPU, while rendering and
display processing is carried out by dedicated hardware. The demand has thus arisen for a chip set
combining a microcomputer with a rendering and display LSI.
In response to this demand, Hitachi has developed the Q Series of graphics accelerators, offering
high-speed rendering and display processing in a chip set that includes a SuperH family
microcomputer.
For examples of the use of this LSI, see Q Series Application Notes—HD64411Q2.
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