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Bits 5 and 4—DMA Mode (DMA1, DMA0): These bits specify DMA transfer. Use the
DMA flag (DMF) in SR to check for the start and end of DMA mode.
Bit 5:
Bit 4:
DMA1
DMA0
0
0
1
1
0
1
130
Description
Normal mode is set.
The mode for DMA transfer to memory (UGM) corresponding to CS0 is
set. When the remaining DMA transfer count reaches 0, this bit is
automatically cleared and normal mode is entered. The initial value of the
remaining DMA transfer count is determined by the setting in the DMA
transfer word count register (DMAWR). The remaining DMA transfer count
is an internal value in the LSI, and is decremented by 1 each time a word
is processed.
UGM access by the CPU is disabled in this mode.
Setting prohibited
The mode for DMA transfer to the register [image data entry register
(IDER)] corresponding to CS1 is set. In this mode, register address
incrementing is not performed and all writes are to IDER. When the
remaining DMA transfer count reaches 0, this bit is automatically cleared
and normal mode is entered. The initial value of the remaining DMA
transfer count is determined by the setting in the DMA transfer word
count register (DMAWR). The remaining DMA transfer count is an LSI
internal value, and is decremented by 1 each time a word is processed.
UGM access by the CPU is disabled in this mode.
(Initial value)
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