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CONTROL REGISTERS
LMOD
— LCD Mode Control Register
Bit Identifier
RESET Value
RESET
Read/Write
Addressing Mode
.7–.6
.5–.4
.3–.0
4-16
.7
.6
0
0
–
–
Register addressing mode only
Not used for the S3C8248/C8245/C8247/C8249
LCD Clock (LCDCK) Frequency Selection Bits
0
0
32.768 kHz watch timer clock (fw)/2
0
1
32.768 kHz watch timer clock (fw)/2
1
0
32.768 kHz watch timer clock (fw)/2
1
1
32.768 kHz watch timer clock (fw)/2
Duty and Bias Selection for LCD Display
0
x
x
x
LCD display off (COM and SEG output low)
1
0
0
0
1/4 duty, 1/3 bias
1
0
0
1
1/3 duty, 1/3 bias
1
0
1
1
1/3 duty, 1/2 bias
1
0
1
0
1/2 duty, 1/2 bias
1
1
x
x
Static
S3C8248/C8245/P8245/C8247/C8249/P8249
.5
.4
0
0
R/W
R/W
R/W
D1H
.3
.2
.1
0
0
0
R/W
R/W
9
= 64 Hz
8
= 128 Hz
7
= 256 Hz
6
= 512 Hz
Set 1
.0
0
R/W
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