Sony ZS-M35 Service Manual page 34

• BD BOARD IC121 CXD2654R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
Pin No. Pin Name
1 MNT0 (FOK)
2 MNT1 (SHOCK)
3 MNT2 (XBUSY)
4 MNT3 (SLOCK)
5 SWDT
6 SCLK
7 XLAT
8 SRDT
9 SENS
10 XRST
11 SQSY
12 DQSY
13 RECP
14 XINT
15 TX
16 OSCI
17 OSCO
18 XTSL
19 DIN0
20 DIN1
21 DOUT
22 DATAI
23 LRCKI
24 XBCKI
25 ADDT
26 DADT
27 LRCK
28 XBCK
29 FS256
30 DVDD
31 – 34 A03 – A00
35 A10
36 – 40 A04 – A08
41 A11
42 DVSS
43 XOE
44 XCAS
45 A09
I/O
Focus OK signal output to the MD mechanism controller (IC601)
O
"H" is output when focus is on ("L": NG)
O Track jump detection signal output to the MD mechanism controller (IC601)
O Busy monitor signal output to the MD mechanism controller (IC601)
O Spindle servo lock status monitor signal output to the MD mechanism controller (IC601)
I Writing serial data signal input from the MD mechanism controller (IC601)
I (S) Serial data transfer clock signal input from the MD mechanism controller (IC601)
I (S) Serial data latch pulse signal input from the MD mechanism controller (IC601)
O (3) Reading serial data signal output to the MD mechanism controller (IC601)
O (3) Internal status (SENSE) output to the MD mechanism controller (IC601)
I (S) Reset signal input from the MD mechanism controller (IC601)
Subcode Q sync (SCOR) output to the MD mechanism controller (IC601)
O
"L" is output every 13.3 msec
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism controller
O
(IC601) "L" is output every 13.3 msec
Laser power selection signal input from the MD mechanism controller (IC601)
I
"L": playback mode, "H": recording mode
O Interrupt status output to the MD mechanism controller (IC601)
Recording data output enable signal input from the MD mechanism controller (IC601)
I
Writing data transmission timing input (Also serves as the magnetic head on/off output)
I System clock signal (512 Fs = 22.5792 MHz) input terminal
O System clock signal (512 Fs = 22.5792 MHz) output terminal
Input terminal for the system clock frequency setting
I
"L": 45.1584 MHz, "H": 22.5792 MHz (fixed at "H" in this set)
I Digital audio signal input terminal when recording mode (for digital optical input)
I Digital audio signal input terminal when recording mode (for digital optical input)
Digital audio signal output terminal when playback mode (for digital optical output)
O
Not used
I Serial data input terminal
I L/R sampling clock signal (44.1 kHz) input terminal
I Bit clock signal (2.8224 MHz) input terminal
I Recording data input from the A/D, D/A converter (IC603)
O Playback data output to the A/D, D/A converter (IC603)
O L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC603)
O Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC603)
O Clock signal (11.2896 MHz) output terminal
— Power supply terminal (+3.3 V) (digital system)
O Address signal output to the D-RAM (IC124)
O Address signal output to the external D-RAM
O Address signal output to the D-RAM (IC124)
O Address signal output to the external D-RAM
— Ground terminal (digital system)
O Output enable signal output to the D-RAM (IC124)
O Column address strobe signal output to the D-RAM (IC124)
O Address signal output to the D-RAM (IC124)
Pin Description
Almost all, "H" is output
Almost all, "H" is output
Not used (fixed at "L")
Not used (fixed at "L")
Not used (open)
Not used (open)
Not used (open)
– 34 –
"L": reset
Not used (open)
Not used (fixed at "L")
"L" active
"L" active
Not used