Panasonic KX-FP85 Service Manual page 137

6.3.7. RESET CIRCUIT (WATCH DOG TIMER)
The output signal from pin 1 of the voltage detect IC (IC507) is input to the ASIC (IC501) 136 pin. Then the output signal from pin
133 of the ASIC (IC501) resets the ASIC.
1. During a momentary power interruption, a positive reset pulse of 46~51 msec is generated and the system is reset completely.
2. When pin 132 and 133 of IC501 become low level, they will prohibit the SRAM (IC503) from changing data.
The SRAM (IC504) will go into the backup mode, when they are backed up by a lithium battery.
3. The watch dog timer, built-in the ASIC (IC501), is initialized by the CPU about every 1.5 ms.
When a watch dog error occurs, pin 137 of the ASIC (IC501) becomes low level.
The terminal of the WDERR signal is connected to the reset line, so the WDERR signal works as the reset signal.
137
KX-FP85